- sig_cs = self.cm.request("cs")
- sig_clk = self.cm.request("clk")
- port_cs, port_clk_p, port_clk_n = self.cm.iter_ports()
- self.assertEqual(list(self.cm.iter_single_ended_pins()), [
- (sig_cs, port_cs, {}, True),
- ])
- self.assertEqual(list(self.cm.iter_differential_pins()), [
- (sig_clk, port_clk_p, port_clk_n, {}, True),
- ])
+ cs = self.cm.request("cs")
+ clk = self.cm.request("clk")
+ cs_io, clk_p, clk_n = self.cm.iter_ports()
+
+ cs_info, = self.cm.iter_single_ended_pins()
+ self.assertIs(cs_info[0], cs)
+ self.assertIs(cs_info[1].io, cs_io)
+ self.assertEqual(cs_info[2], {})
+ self.assertEqual(cs_info[3], True)
+
+ clk_info, = self.cm.iter_differential_pins()
+ self.assertIs(clk_info[0], clk)
+ self.assertIs(clk_info[1].p, clk_p)
+ self.assertIs(clk_info[1].n, clk_n)
+ self.assertEqual(clk_info[2], {})
+ self.assertEqual(clk_info[3], True)