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must only try to connect jtag when variant requests it
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 3 May 2021 12:00:10 +0000
(13:00 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 3 May 2021 12:00:10 +0000
(13:00 +0100)
sim.py
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diff --git
a/sim.py
b/sim.py
index 306adf41d2f2b260ad47a2bfeaa9b2de6c406747..550339e46a22169fe19510da5d3032202f3f8aec 100755
(executable)
--- a/
sim.py
+++ b/
sim.py
@@
-165,21
+165,22
@@
class LibreSoCSim(SoCSDRAM):
self.add_constant("MEMTEST_DATA_DEBUG", 1)
self.add_constant("MEMTEST_DATA_DEBUG", 1)
- # add JTAG platform pins
- platform.add_extension([
- ("jtag", 0,
- Subsignal("tck", Pins(1)),
- Subsignal("tms", Pins(1)),
- Subsignal("tdi", Pins(1)),
- Subsignal("tdo", Pins(1)),
- )
- ])
+ if "jtag" in variant:
+ # add JTAG platform pins
+ platform.add_extension([
+ ("jtag", 0,
+ Subsignal("tck", Pins(1)),
+ Subsignal("tms", Pins(1)),
+ Subsignal("tdi", Pins(1)),
+ Subsignal("tdo", Pins(1)),
+ )
+ ])
- jtagpads = platform.request("jtag")
- self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
- self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
- self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
- self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
jtagpads = platform.request("jtag")
+
self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+
self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+
self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+
self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
# Debug ---------------------------------------------------------------
# Debug ---------------------------------------------------------------