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add flexbus as fast interface
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 26 Jul 2018 08:26:18 +0000
(09:26 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 26 Jul 2018 08:26:18 +0000
(09:26 +0100)
src/bsv/bsv_lib/soc_template.bsv
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src/bsv/peripheral_gen/base.py
patch
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src/bsv/peripheral_gen/jtag.py
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src/spec/i_class.py
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diff --git
a/src/bsv/bsv_lib/soc_template.bsv
b/src/bsv/bsv_lib/soc_template.bsv
index 9d853f7f93c4a13b9a7ba6be806541939cfcf34b..e99b9b149839fd4d13e27e87b9b111b615ab5768 100644
(file)
--- a/
src/bsv/bsv_lib/soc_template.bsv
+++ b/
src/bsv/bsv_lib/soc_template.bsv
@@
-109,9
+109,6
@@
package Soc;
interface Vme_out proc_ifc;
interface Data_bus_inf proc_dbus;
`endif
interface Vme_out proc_ifc;
interface Data_bus_inf proc_dbus;
`endif
- `ifdef FlexBus
- interface FlexBus_Master_IFC flexbus_out;
- `endif
{1}
endinterface
{1}
endinterface
@@
-147,10
+144,6
@@
package Soc;
`ifdef VME
Ifc_vme_top vme <-mkvme_top();
`endif
`ifdef VME
Ifc_vme_top vme <-mkvme_top();
`endif
- `ifdef FlexBus
- AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
- flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
- `endif
Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
core_clock, core_reset, uart_clock,
uart_reset, clocked_by slow_clock ,
Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
core_clock, core_reset, uart_clock,
uart_reset, clocked_by slow_clock ,
@@
-219,11
+212,6
@@
package Soc;
[fromInteger(valueOf(VME_slave_num))],
vme.slave_axi_vme);
`endif
[fromInteger(valueOf(VME_slave_num))],
vme.slave_axi_vme);
`endif
- `ifdef FlexBus
- mkConnection (fabric.v_to_slaves
- [fromInteger(valueOf(FlexBus_slave_num))],
- flexbus.axi_side);
- `endif
// fabric connections
{5}
// fabric connections
{5}
@@
-306,9
+294,6
@@
package Soc;
`ifdef VME
interface proc_ifc = vme.proc_ifc;
interface proc_dbus = vme.proc_dbus;
`ifdef VME
interface proc_ifc = vme.proc_ifc;
interface proc_dbus = vme.proc_dbus;
- `endif
- `ifdef FlexBus
- interface flexbus_out = flexbus.flexbus_side;
`endif
method Action boot_sequence(Bit#(1) bootseq) =
core.boot_sequence(bootseq);
`endif
method Action boot_sequence(Bit#(1) bootseq) =
core.boot_sequence(bootseq);
diff --git
a/src/bsv/peripheral_gen/base.py
b/src/bsv/peripheral_gen/base.py
index caad20f510c8ea4fb4d708953f3002cc28d05dc0..0e450f457ba562e962bdc88c272245d7eb7867e1 100644
(file)
--- a/
src/bsv/peripheral_gen/base.py
+++ b/
src/bsv/peripheral_gen/base.py
@@
-266,14
+266,17
@@
else"""
def extfastifinstance(self, name, count):
return ''
def extfastifinstance(self, name, count):
return ''
- def _extifinstance(self, name, count, suffix, prefix, samename=False):
+ def _extifinstance(self, name, count, suffix, prefix, samename=False,
+ ifsuffix=None):
+ if ifsuffix is None:
+ ifsuffix = ''
pname = self.get_iname(count)
if samename:
sname = pname
else:
sname = self.peripheral.iname().format(count)
pname = self.get_iname(count)
if samename:
sname = pname
else:
sname = self.peripheral.iname().format(count)
- template = "interface {0}{3} = {2}{1};"
- return template.format(pname, sname, prefix, suffix)
+ template = "interface {0}{3} = {2}{1}
{4}
;"
+ return template.format(pname, sname, prefix, suffix
, ifsuffix
)
def extifinstance2(self, name, count):
return ''
def extifinstance2(self, name, count):
return ''
@@
-715,6
+718,7
@@
class PFactory(object):
from qspi import qspi, mqspi
from gpio import gpio
from rgbttl import rgbttl
from qspi import qspi, mqspi
from gpio import gpio
from rgbttl import rgbttl
+ from flexbus import flexbus
for k, v in {'uart': uart,
'rs232': rs232,
for k, v in {'uart': uart,
'rs232': rs232,
@@
-729,6
+733,7
@@
class PFactory(object):
'sd': sdmmc,
'jtag': jtag,
'lcd': rgbttl,
'sd': sdmmc,
'jtag': jtag,
'lcd': rgbttl,
+ 'fb': flexbus,
'gpio': gpio
}.items():
if name.startswith(k):
'gpio': gpio
}.items():
if name.startswith(k):
diff --git
a/src/bsv/peripheral_gen/jtag.py
b/src/bsv/peripheral_gen/jtag.py
index bfebe074562fae87eea6f1819f5cd6ceeab4ff55..dd3e2fa10f4043062e6005295c8d59a21953abbe 100644
(file)
--- a/
src/bsv/peripheral_gen/jtag.py
+++ b/
src/bsv/peripheral_gen/jtag.py
@@
-11,7
+11,7
@@
class jtag(PBase):
def fastifdecl(self, name, count):
# YUK!
def fastifdecl(self, name, count):
# YUK!
- return "Ifc_jtagdtm jtag{0}_out;".format(count)
+ return "
interface
Ifc_jtagdtm jtag{0}_out;".format(count)
def mkfast_peripheral(self):
return """\
def mkfast_peripheral(self):
return """\
diff --git
a/src/spec/i_class.py
b/src/spec/i_class.py
index 99c8359f0c806d29cbd586974a51a9d47fdd7854..88cbdcf5936b168ff6a9175dffd05e3752547a42 100644
(file)
--- a/
src/spec/i_class.py
+++ b/
src/spec/i_class.py
@@
-60,7
+60,7
@@
def pinspec():
}
ps = PinSpec(pinbanks, fixedpins, function_names,
}
ps = PinSpec(pinbanks, fixedpins, function_names,
- ['lcd', 'jtag', 'f
lexbus
' ])
+ ['lcd', 'jtag', 'f
b
' ])
# Bank A, 0-27
ps.gpio("", ('A', 0), 0, 0, 28)
# Bank A, 0-27
ps.gpio("", ('A', 0), 0, 0, 28)