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Changed CAM to accept write address. Pushed back and LRU logic to a higher block.
author
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Mon, 18 Feb 2019 01:27:06 +0000
(17:27 -0800)
committer
Daniel Benusovich
<flyingmonkeys1996@gmail.com>
Mon, 18 Feb 2019 01:27:06 +0000
(17:27 -0800)
TLB/CAM.py
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diff --git
a/TLB/CAM.py
b/TLB/CAM.py
index 0c332b960b75a11f8e9f142d49a7b3472d249592..63047d73a0a20020382e8d94728305ca715ff16c 100644
(file)
--- a/
TLB/CAM.py
+++ b/
TLB/CAM.py
@@
-13,13
+13,14
@@
class CAM():
encoder_input = Signal(cam_size)
# Input
encoder_input = Signal(cam_size)
# Input
- self.write = Signal(1)
- self.key = Signal(key_size)
- self.data_in = Signal(key_size)
+ self.write = Signal(1) # Denotes read (0) or write (1)
+ self.address = Signal(max=cam_size) # The address of the CAM to be written
+ self.key = Signal(key_size) # The key to search for or to be written
+ self.data_in = Signal(key_size) # The data to be written
# Output
# Output
- self.data_
match = Signal(1)
- self.data_out = Signal(data_size)
+ self.data_
hit = Signal(1) # Denotes a key data pair was stored at key_in
+ self.data_out = Signal(data_size)
# The data mapped to by key_in
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
@@
-29,10
+30,12
@@
class CAM():
# Set the key value for every CamEntry
for index in range(cam_size):
m.d.sync += [
# Set the key value for every CamEntry
for index in range(cam_size):
m.d.sync += [
- entry_array[index].write.eq(self.write),
- entry_array[index].key_in.eq(self.key),
- entry_array[index].data_in.eq(self.data_in),
- encoder_input[index].eq(entry_array[index].match)
+ If(self.write == 0,
+ entry_array[index].write.eq(self.write),
+ entry_array[index].key_in.eq(self.key),
+ entry_array[index].data_in.eq(self.data_in),
+ encoder_input[index].eq(entry_array[index].match)
+ )
]
]
@@
-43,19
+46,14
@@
class CAM():
If(self.write == 0,
# 0 denotes a mapping was found
If(encoder.n == 0,
If(self.write == 0,
# 0 denotes a mapping was found
If(encoder.n == 0,
- self.data_
match
.eq(0),
+ self.data_
hit
.eq(0),
self.data_out.eq(entry_array[encoder.o].data)
).Else(
self.data_out.eq(entry_array[encoder.o].data)
).Else(
- self.data_
match
.eq(1)
+ self.data_
hit
.eq(1)
)
).Else(
)
).Else(
- # 0 denotes a mapping was found
- If(encoder.n == 0,
- self.data_match.eq(0),
- entry_array[encoder.o].data_in.eq(self.data_in)
- ).Else(
- # LRU algorithm here
- )
+ entry_array[self.address].key_in.eq(self.key_in),
+ entry_array[self.address].data.eq(self.data_in)
)
]
)
]