-python3 src/soc/simple/issuer_verilog.py --fabric-compat --enable-core --enable-mmu --enable-xics --disable-svp64 --disable-pll --debug dmi external_core_top.v
-cp -Rp external_core_top.v /home/src/kestrel/pythondata-cpu-libresoc/pythondata_cpu_libresoc/hdl/external_core_top.v
+python3 src/soc/simple/issuer_verilog.py --fabric-compat --enable-core \
+ --enable-mmu --enable-xics \
+ --disable-svp64 --disable-pll \
+ --debug dmi external_core_top.v
+cp -Rp external_core_top.v \
+ $KESTREL/pythondata-cpu-libresoc/pythondata_cpu_libresoc/hdl/external_core_top.v