+import unittest
+from bigint_presentation_code.compiler_ir import GPR_SIZE_IN_BYTES
+
+from bigint_presentation_code.compiler_ir2 import (Fn, OpKind, PreRASimState)
+
+
+class TestCompilerIR(unittest.TestCase):
+ maxDiff = None
+
+ def test_sim(self):
+ fn = Fn()
+ op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
+ arg = op0.outputs[0]
+ MAXVL = 32
+ op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
+ vl = op1.outputs[0]
+ op2 = fn.append_new_op(
+ OpKind.SvLd, inputs=[arg, vl], immediates=[0], maxvl=MAXVL,
+ name="ld")
+ a = op2.outputs[0]
+ op3 = fn.append_new_op(
+ OpKind.SvLI, inputs=[vl], immediates=[0], maxvl=MAXVL, name="li")
+ b = op3.outputs[0]
+ op4 = fn.append_new_op(OpKind.SetCA, name="ca")
+ ca = op4.outputs[0]
+ op5 = fn.append_new_op(
+ OpKind.SvAddE, inputs=[a, b, ca, vl], maxvl=MAXVL, name="add")
+ s = op5.outputs[0]
+ fn.append_new_op(
+ OpKind.SvStd, inputs=[s, arg, vl], immediates=[0], maxvl=MAXVL,
+ name="st")
+
+ self.assertEqual([repr(i) for i in fn.ops], [
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.FuncArgR3, "
+ "inputs=(), outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet([3])}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), "
+ "tied_input_index=None, spread_index=None),), maxvl=1), "
+ "inputs=OpInputs([], op=...), "
+ "immediates=OpImmediates([], op=...), "
+ "outputs=(<arg#0>,), "
+ "name='arg')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SetVLI, "
+ "inputs=(), outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.VL_MAXVL: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), "
+ "tied_input_index=None, spread_index=None),), maxvl=1), "
+ "inputs=OpInputs([], op=...), "
+ "immediates=OpImmediates([32], op=...), "
+ "outputs=(<vl#0>,), "
+ "name='vl')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SvLd, "
+ "inputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.VL_MAXVL: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), "
+ "tied_input_index=None, spread_index=None)), "
+ "outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None),), maxvl=32), "
+ "inputs=OpInputs([<arg#0>, <vl#0>], op=...), "
+ "immediates=OpImmediates([0], op=...), "
+ "outputs=(<ld#0>,), "
+ "name='ld')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SvLI, "
+ "inputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.VL_MAXVL: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), "
+ "tied_input_index=None, spread_index=None),), outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None),), maxvl=32), "
+ "inputs=OpInputs([<vl#0>], op=...), "
+ "immediates=OpImmediates([0], op=...), "
+ "outputs=(<li#0>,), "
+ "name='li')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SetCA, "
+ "inputs=(), outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.CA: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), "
+ "tied_input_index=None, spread_index=None),), maxvl=1), "
+ "inputs=OpInputs([], op=...), "
+ "immediates=OpImmediates([], op=...), "
+ "outputs=(<ca#0>,), "
+ "name='ca')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SvAddE, "
+ "inputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.CA: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.VL_MAXVL: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), "
+ "tied_input_index=None, spread_index=None)), outputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.CA: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), "
+ "tied_input_index=None, spread_index=None)), maxvl=32), "
+ "inputs=OpInputs([<ld#0>, <li#0>, <ca#0>, <vl#0>], op=...), "
+ "immediates=OpImmediates([], op=...), "
+ "outputs=(<add#0>, <add#1>), "
+ "name='add')",
+ "Op(fn=<Fn>, properties=OpProperties(kind=OpKind.SvStd, "
+ "inputs=("
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet(range(14, 97))}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
+ "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), "
+ "tied_input_index=None, spread_index=None), "
+ "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
+ "LocKind.VL_MAXVL: FBitSet([0])}), "
+ "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), "
+ "tied_input_index=None, spread_index=None)), "
+ "outputs=(), maxvl=32), "
+ "inputs=OpInputs([<add#0>, <arg#0>, <vl#0>], op=...), "
+ "immediates=OpImmediates([0], op=...), outputs=(), "
+ "name='st')",
+ ])
+
+ addr = 0x100
+ state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
+ state.store(addr=addr, value=0xffffffff_ffffffff,
+ size_in_bytes=GPR_SIZE_IN_BYTES)
+ state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
+ size_in_bytes=GPR_SIZE_IN_BYTES)
+ self.assertEqual(
+ repr(state),
+ "PreRASimState(ssa_vals={<arg#0>: (0x100,)}, memory={\n"
+ "0x00100: <0xffffffffffffffff>,\n"
+ "0x00108: <0xabcdef0123456789>})")
+ fn.pre_ra_sim(state)
+ self.assertEqual(
+ repr(state),
+ "PreRASimState(ssa_vals={\n"
+ "<arg#0>: (0x100,),\n"
+ "<vl#0>: (0x20,),\n"
+ "<ld#0>: (\n"
+ " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0),\n"
+ "<li#0>: (\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0),\n"
+ "<ca#0>: (0x1,),\n"
+ "<add#0>: (\n"
+ " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0,\n"
+ " 0x0, 0x0, 0x0, 0x0),\n"
+ "<add#1>: (0x0,),\n"
+ "}, memory={\n"
+ "0x00100: <0x0000000000000000>,\n"
+ "0x00108: <0xabcdef012345678a>,\n"
+ "0x00110: <0x0000000000000000>,\n"
+ "0x00118: <0x0000000000000000>,\n"
+ "0x00120: <0x0000000000000000>,\n"
+ "0x00128: <0x0000000000000000>,\n"
+ "0x00130: <0x0000000000000000>,\n"
+ "0x00138: <0x0000000000000000>,\n"
+ "0x00140: <0x0000000000000000>,\n"
+ "0x00148: <0x0000000000000000>,\n"
+ "0x00150: <0x0000000000000000>,\n"
+ "0x00158: <0x0000000000000000>,\n"
+ "0x00160: <0x0000000000000000>,\n"
+ "0x00168: <0x0000000000000000>,\n"
+ "0x00170: <0x0000000000000000>,\n"
+ "0x00178: <0x0000000000000000>,\n"
+ "0x00180: <0x0000000000000000>,\n"
+ "0x00188: <0x0000000000000000>,\n"
+ "0x00190: <0x0000000000000000>,\n"
+ "0x00198: <0x0000000000000000>,\n"
+ "0x001a0: <0x0000000000000000>,\n"
+ "0x001a8: <0x0000000000000000>,\n"
+ "0x001b0: <0x0000000000000000>,\n"
+ "0x001b8: <0x0000000000000000>,\n"
+ "0x001c0: <0x0000000000000000>,\n"
+ "0x001c8: <0x0000000000000000>,\n"
+ "0x001d0: <0x0000000000000000>,\n"
+ "0x001d8: <0x0000000000000000>,\n"
+ "0x001e0: <0x0000000000000000>,\n"
+ "0x001e8: <0x0000000000000000>,\n"
+ "0x001f0: <0x0000000000000000>,\n"
+ "0x001f8: <0x0000000000000000>})")
+
+
+if __name__ == "__main__":
+ unittest.main()