projects
/
freedom-sifive.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (from parent 1:
6c9b159
)
platforms: fixup to new package names
bump-repos
author
Wesley W. Terpstra
<wesley@sifive.com>
Mon, 5 Mar 2018 23:45:01 +0000
(15:45 -0800)
committer
Wesley W. Terpstra
<wesley@sifive.com>
Mon, 5 Mar 2018 23:45:01 +0000
(15:45 -0800)
src/main/scala/everywhere/e300artydevkit/Config.scala
patch
|
blob
|
history
src/main/scala/everywhere/e300artydevkit/Platform.scala
patch
|
blob
|
history
src/main/scala/everywhere/e300artydevkit/System.scala
patch
|
blob
|
history
src/main/scala/unleashed/u500vc707devkit/Config.scala
patch
|
blob
|
history
src/main/scala/unleashed/u500vc707devkit/System.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/everywhere/e300artydevkit/Config.scala
b/src/main/scala/everywhere/e300artydevkit/Config.scala
index a85d1e65e3008d489b0f72ed92c259118c24d0ca..f8058e95c024edf3206aa0e4700e12e688b01fb2 100644
(file)
--- a/
src/main/scala/everywhere/e300artydevkit/Config.scala
+++ b/
src/main/scala/everywhere/e300artydevkit/Config.scala
@@
-2,7
+2,7
@@
package sifive.freedom.everywhere.e300artydevkit
import freechips.rocketchip.config._
package sifive.freedom.everywhere.e300artydevkit
import freechips.rocketchip.config._
-import freechips.rocketchip.
coreplex
._
+import freechips.rocketchip.
subsystem
._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
diff --git
a/src/main/scala/everywhere/e300artydevkit/Platform.scala
b/src/main/scala/everywhere/e300artydevkit/Platform.scala
index be1789a1272f1f58fa81b869306cab05c306cc89..4e056eb3a256d64a2d133e5f81f10608e114bddd 100644
(file)
--- a/
src/main/scala/everywhere/e300artydevkit/Platform.scala
+++ b/
src/main/scala/everywhere/e300artydevkit/Platform.scala
@@
-4,7
+4,7
@@
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import freechips.rocketchip.config._
import Chisel._
import freechips.rocketchip.config._
-import freechips.rocketchip.
coreplex
._
+import freechips.rocketchip.
subsystem
._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
diff --git
a/src/main/scala/everywhere/e300artydevkit/System.scala
b/src/main/scala/everywhere/e300artydevkit/System.scala
index c3fbd96eac7cc91d1d200e487c15f4d5dad065e9..93d935293b6eafdd3d8e36450db76651a9d0e1e0 100644
(file)
--- a/
src/main/scala/everywhere/e300artydevkit/System.scala
+++ b/
src/main/scala/everywhere/e300artydevkit/System.scala
@@
-4,7
+4,7
@@
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import freechips.rocketchip.config._
import Chisel._
import freechips.rocketchip.config._
-import freechips.rocketchip.
coreplex
._
+import freechips.rocketchip.
subsystem
._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
@@
-21,7
+21,7
@@
import sifive.blocks.devices.i2c._
// E300ArtyDevKitSystem
//-------------------------------------------------------------------------
// E300ArtyDevKitSystem
//-------------------------------------------------------------------------
-class E300ArtyDevKitSystem(implicit p: Parameters) extends Rocket
Coreplex
+class E300ArtyDevKitSystem(implicit p: Parameters) extends Rocket
Subsystem
with HasPeripheryMaskROMSlave
with HasPeripheryDebug
with HasPeripheryMockAON
with HasPeripheryMaskROMSlave
with HasPeripheryDebug
with HasPeripheryMockAON
@@
-35,7
+35,7
@@
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketCoreplex
}
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
}
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
- extends Rocket
CoreplexModule
(_outer)
+ extends Rocket
SubsystemModuleImp
(_outer)
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
diff --git
a/src/main/scala/unleashed/u500vc707devkit/Config.scala
b/src/main/scala/unleashed/u500vc707devkit/Config.scala
index 4aa736255cda1b346ba05d0391c1ffa1f1046bed..7a02daca6eab9cb83d1cc0224ba6dcf235d531e8 100644
(file)
--- a/
src/main/scala/unleashed/u500vc707devkit/Config.scala
+++ b/
src/main/scala/unleashed/u500vc707devkit/Config.scala
@@
-2,7
+2,7
@@
package sifive.freedom.unleashed.u500vc707devkit
import freechips.rocketchip.config._
package sifive.freedom.unleashed.u500vc707devkit
import freechips.rocketchip.config._
-import freechips.rocketchip.
coreplex
._
+import freechips.rocketchip.
subsystem
._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
diff --git
a/src/main/scala/unleashed/u500vc707devkit/System.scala
b/src/main/scala/unleashed/u500vc707devkit/System.scala
index 1a02d0e3df532207ec00d19c62ba71c4b9b2e56b..90ffdf00587843203dc37f65b27e5147ac1175ab 100644
(file)
--- a/
src/main/scala/unleashed/u500vc707devkit/System.scala
+++ b/
src/main/scala/unleashed/u500vc707devkit/System.scala
@@
-4,7
+4,7
@@
package sifive.freedom.unleashed.u500vc707devkit
import Chisel._
import freechips.rocketchip.config._
import Chisel._
import freechips.rocketchip.config._
-import freechips.rocketchip.
coreplex
._
+import freechips.rocketchip.
subsystem
._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
@@
-21,7
+21,7
@@
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
// U500VC707DevKitSystem
//-------------------------------------------------------------------------
// U500VC707DevKitSystem
//-------------------------------------------------------------------------
-class U500VC707DevKitSystem(implicit p: Parameters) extends Rocket
Coreplex
+class U500VC707DevKitSystem(implicit p: Parameters) extends Rocket
Subsystem
with HasPeripheryMaskROMSlave
with HasPeripheryDebug
with HasSystemErrorSlave
with HasPeripheryMaskROMSlave
with HasPeripheryDebug
with HasSystemErrorSlave
@@
-34,7
+34,7
@@
class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
}
class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
}
class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
- extends Rocket
CoreplexModule
(_outer)
+ extends Rocket
SubsystemModuleImp
(_outer)
with HasRTCModuleImp
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp
with HasRTCModuleImp
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp