[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Fri, 3 Apr 2020 12:52:17 +0000 (12:52 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 3 Apr 2020 12:52:19 +0000 (13:52 +0100)
30/d984386e1cc797a2f520c2c7d8e5f2839651b7 [new file with mode: 0644]

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+Date: Fri, 03 Apr 2020 12:52:17 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: whitequark@whitequark.org
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-276-13-nIGR4uF6jp@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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