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soc_sdram: remove upper limit on usable main RAM
authorGabriel Somlo <gsomlo@gmail.com>
Thu, 31 Oct 2019 20:23:36 +0000 (16:23 -0400)
committerGabriel Somlo <gsomlo@gmail.com>
Fri, 1 Nov 2019 12:55:15 +0000 (08:55 -0400)
Revert commit #68a503174.

litex/soc/integration/soc_sdram.py patch | blob | history

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index f16e596ad0e736c07ff4625990f4b8e9fe5fac54..71f54b177438c573632b49153e86e991d1dc1bd0 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -61,7 +61,6 @@ class SoCSDRAM(SoCCore):
         main_ram_size = 2**(geom_settings.bankbits +
                             geom_settings.rowbits +
                             geom_settings.colbits)*phy.settings.databits//8
-        main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
 
         # SoC [<--> L2 Cache] <--> LiteDRAM ----------------------------------------------------
         if self.cpu.name == "rocket":