RISC-V: Added half-precision floating-point v1.0 instructions.

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Added implicit f
	and zicsr for zfh.
	(riscv_supported_std_z_ext): Added default v1.0 version for zfh.
	(riscv_multi_subset_supports): Handle INSN_CLASS_ZFH,
	INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH.
gas/
	* config/tc-riscv.c (FLT_CHARS): Added "hH".
	(macro): Expand Pseudo M_FLH and M_FSH.
	(riscv_pseudo_table): Added .float16 directive.
	* testsuite/gas/riscv/float16-be.d: New testcase for .float16.
	* testsuite/gas/riscv/float16-le.d: Likewise.
	* testsuite/gas/riscv/float16.s: Likewise.
	* testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh.
	* testsuite/gas/riscv/fp-zfh-insns.s: Likewise.
include/
	* opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh.
	* opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh.
opcodes/
	* riscv-opc.c (riscv_opcodes): Added zfh instructions.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb2cc146c04bf4be7f867f7bb7ee6e148f36154e..05e8272e0e9d893fee72d4f13b62547b8dd402e5 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1100,6 +1100,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvl64b", "zvl32b",         check_implicit_always},
   {"d", "f",           check_implicit_always},
   {"f", "zicsr",       check_implicit_always},
+  {"zfh", "f",         check_implicit_always},
+  {"zfh", "zicsr",     check_implicit_always},
   {"zqinx", "zdinx",   check_implicit_always},
   {"zdinx", "zfinx",   check_implicit_always},
   {"zk", "zkn",                check_implicit_always},
@@ -1180,6 +1182,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",         ISA_SPEC_CLASS_20191213,        2, 0,  0 },
   {"zifencei",         ISA_SPEC_CLASS_20190608,        2, 0,  0 },
   {"zihintpause",      ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zfh",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zfinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zdinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zqinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2358,6 +2361,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_Q_OR_ZQINX:
       return (riscv_subset_supports (rps, "q")
              || riscv_subset_supports (rps, "zqinx"));
+    case INSN_CLASS_ZFH:
+      return riscv_subset_supports (rps, "zfh");
+    case INSN_CLASS_D_AND_ZFH:
+      return (riscv_subset_supports (rps, "d")
+             && riscv_subset_supports (rps, "zfh") );
+    case INSN_CLASS_Q_AND_ZFH:
+      return (riscv_subset_supports (rps, "q")
+             && riscv_subset_supports (rps, "zfh"));
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index fb3fc649802cfa8e3c5d1da362f640be26d748be..1b730b4be36afc08729cdcf8ec9cb12719e42f40 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -389,7 +389,7 @@ const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant.
    As in 0f12.456 or 0d1.2345e12.  */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
+const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
 
 /* Indicate we are already assemble any instructions or not.  */
 static bool start_assemble = false;
@@ -1908,6 +1908,15 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
       vector_macro (ip);
       break;
 
+    case M_FLH:
+      pcrel_load (rd, rs1, imm_expr, "flh",
+                 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+      break;
+    case M_FSH:
+      pcrel_store (rs2, rs1, imm_expr, "fsh",
+                  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+      break;
+
     default:
       as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
       break;
@@ -4569,6 +4578,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
   {"insn", s_riscv_insn, 0},
   {"attribute", s_riscv_attribute, 0},
   {"variant_cc", s_variant_cc, 0},
+  {"float16", float_cons, 'h'},
 
   { NULL, NULL, 0 },
 };

diff --git a/gas/testsuite/gas/riscv/float16-be.d b/gas/testsuite/gas/riscv/float16-be.d
new file mode 100644 (file)
index 0000000..daec7b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/float16-be.d
@@ -0,0 +1,10 @@
+# source: float16.s
+# objdump: -sj .data
+# as: -mbig-endian
+
+.*:[   ]+file format .*bigriscv
+
+Contents of section \.data:
+ 0000 4a002fdf 1c197bff 000103ff 04003c00.*
+ 0010 3c017fff 7c00fc00 00008000 bc00bbe7.*
+ 0020 fbff4200 4a00603e 7e007c01.*

diff --git a/gas/testsuite/gas/riscv/float16-le.d b/gas/testsuite/gas/riscv/float16-le.d
new file mode 100644 (file)
index 0000000..5591148
--- /dev/null
+++ b/gas/testsuite/gas/riscv/float16-le.d
@@ -0,0 +1,10 @@
+# source: float16.s
+# objdump: -sj .data
+# as: -mlittle-endian
+
+.*:[   ]+file format .*littleriscv
+
+Contents of section \.data:
+ 0000 004adf2f 191cff7b 0100ff03 0004003c.*
+ 0010 013cff7f 007c00fc 00000080 00bce7bb.*
+ 0020 fffb0042 004a3e60 007e017c.*

diff --git a/gas/testsuite/gas/riscv/float16.s b/gas/testsuite/gas/riscv/float16.s
new file mode 100644 (file)
index 0000000..c206385
--- /dev/null
+++ b/gas/testsuite/gas/riscv/float16.s
@@ -0,0 +1,21 @@
+.data
+       .float16 12.0
+       .float16 0.123
+       .float16 0.004
+       .float16 65504
+       .float16 5.9605e-8
+       .float16 6.0976e-5
+       .float16 6.1035e-5
+       .float16 1
+       .float16 1.001
+       .float16 NaN
+       .float16 +Inf
+       .float16 -Inf
+       .float16 +0
+       .float16 -0
+       .float16 -1
+       .float16 -0.98765
+       .float16 -65504
+       .float16 3.0, 12.0, 543.123
+       .float16 0h:7e00        # qNaNh
+       .float16 0h:7c01        # sNaNh

diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.d b/gas/testsuite/gas/riscv/fp-zfh-insns.d
new file mode 100644 (file)
index 0000000..a0bb069
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-zfh-insns.d
@@ -0,0 +1,71 @@
+#as: -march=rv64ifdq_zfh
+#source: fp-zfh-insns.s
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+00059507[     ]+flh[  ]+fa0,0\(a1\)
+[      ]+[0-9a-f]+:[   ]+00a59027[     ]+fsh[  ]+fa0,0\(a1\)
+[      ]+[0-9a-f]+:[   ]+24b58553[     ]+fmv.h[        ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+24b59553[     ]+fneg.h[       ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+24b5a553[     ]+fabs.h[       ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+24c58553[     ]+fsgnj.h[      ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+24c59553[     ]+fsgnjn.h[     ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+24c5a553[     ]+fsgnjx.h[     ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+04c5f553[     ]+fadd.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+04c58553[     ]+fadd.h[       ]+fa0,fa1,fa2,rne
+[      ]+[0-9a-f]+:[   ]+0cc5f553[     ]+fsub.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+0cc58553[     ]+fsub.h[       ]+fa0,fa1,fa2,rne
+[      ]+[0-9a-f]+:[   ]+14c5f553[     ]+fmul.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+14c58553[     ]+fmul.h[       ]+fa0,fa1,fa2,rne
+[      ]+[0-9a-f]+:[   ]+1cc5f553[     ]+fdiv.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+1cc58553[     ]+fdiv.h[       ]+fa0,fa1,fa2,rne
+[      ]+[0-9a-f]+:[   ]+5c05f553[     ]+fsqrt.h[      ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+5c058553[     ]+fsqrt.h[      ]+fa0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+2cc58553[     ]+fmin.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+2cc59553[     ]+fmax.h[       ]+fa0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+6cc5f543[     ]+fmadd.h[      ]+fa0,fa1,fa2,fa3
+[      ]+[0-9a-f]+:[   ]+6cc58543[     ]+fmadd.h[      ]+fa0,fa1,fa2,fa3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54f[     ]+fnmadd.h[     ]+fa0,fa1,fa2,fa3
+[      ]+[0-9a-f]+:[   ]+6cc5854f[     ]+fnmadd.h[     ]+fa0,fa1,fa2,fa3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f547[     ]+fmsub.h[      ]+fa0,fa1,fa2,fa3
+[      ]+[0-9a-f]+:[   ]+6cc58547[     ]+fmsub.h[      ]+fa0,fa1,fa2,fa3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54b[     ]+fnmsub.h[     ]+fa0,fa1,fa2,fa3
+[      ]+[0-9a-f]+:[   ]+6cc5854b[     ]+fnmsub.h[     ]+fa0,fa1,fa2,fa3,rne
+[      ]+[0-9a-f]+:[   ]+c405f553[     ]+fcvt.w.h[     ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+c4058553[     ]+fcvt.w.h[     ]+a0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+c415f553[     ]+fcvt.wu.h[    ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+c4158553[     ]+fcvt.wu.h[    ]+a0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+d405f553[     ]+fcvt.h.w[     ]+fa0,a1
+[      ]+[0-9a-f]+:[   ]+d4058553[     ]+fcvt.h.w[     ]+fa0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d415f553[     ]+fcvt.h.wu[    ]+fa0,a1
+[      ]+[0-9a-f]+:[   ]+d4158553[     ]+fcvt.h.wu[    ]+fa0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c425f553[     ]+fcvt.l.h[     ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+c4258553[     ]+fcvt.l.h[     ]+a0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+c435f553[     ]+fcvt.lu.h[    ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+c4358553[     ]+fcvt.lu.h[    ]+a0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+d425f553[     ]+fcvt.h.l[     ]+fa0,a1
+[      ]+[0-9a-f]+:[   ]+d4258553[     ]+fcvt.h.l[     ]+fa0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d435f553[     ]+fcvt.h.lu[    ]+fa0,a1
+[      ]+[0-9a-f]+:[   ]+d4358553[     ]+fcvt.h.lu[    ]+fa0,a1,rne
+[      ]+[0-9a-f]+:[   ]+e4058553[     ]+fmv.x.h[      ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+f4058553[     ]+fmv.h.x[      ]+fa0,a1
+[      ]+[0-9a-f]+:[   ]+40258553[     ]+fcvt.s.h[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+42258553[     ]+fcvt.d.h[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+46258553[     ]+fcvt.q.h[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+4405f553[     ]+fcvt.h.s[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+44058553[     ]+fcvt.h.s[     ]+fa0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+4415f553[     ]+fcvt.h.d[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+44158553[     ]+fcvt.h.d[     ]+fa0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+4435f553[     ]+fcvt.h.q[     ]+fa0,fa1
+[      ]+[0-9a-f]+:[   ]+44358553[     ]+fcvt.h.q[     ]+fa0,fa1,rne
+[      ]+[0-9a-f]+:[   ]+e4059553[     ]+fclass.h[     ]+a0,fa1
+[      ]+[0-9a-f]+:[   ]+a4c5a553[     ]+feq.h[        ]+a0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,fa1,fa2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,fa1,fa2

diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.s b/gas/testsuite/gas/riscv/fp-zfh-insns.s
new file mode 100644 (file)
index 0000000..1a04cc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-zfh-insns.s
@@ -0,0 +1,68 @@
+       flh             fa0, 0(a1)
+       fsh             fa0, 0(a1)
+
+       fmv.h           fa0, fa1
+       fneg.h          fa0, fa1
+       fabs.h          fa0, fa1
+       fsgnj.h         fa0, fa1, fa2
+       fsgnjn.h        fa0, fa1, fa2
+       fsgnjx.h        fa0, fa1, fa2
+
+       fadd.h          fa0, fa1, fa2
+       fadd.h          fa0, fa1, fa2, rne
+       fsub.h          fa0, fa1, fa2
+       fsub.h          fa0, fa1, fa2, rne
+       fmul.h          fa0, fa1, fa2
+       fmul.h          fa0, fa1, fa2, rne
+       fdiv.h          fa0, fa1, fa2
+       fdiv.h          fa0, fa1, fa2, rne
+       fsqrt.h         fa0, fa1
+       fsqrt.h         fa0, fa1, rne
+       fmin.h          fa0, fa1, fa2
+       fmax.h          fa0, fa1, fa2
+
+       fmadd.h         fa0, fa1, fa2, fa3
+       fmadd.h         fa0, fa1, fa2, fa3, rne
+       fnmadd.h        fa0, fa1, fa2, fa3
+       fnmadd.h        fa0, fa1, fa2, fa3, rne
+       fmsub.h         fa0, fa1, fa2, fa3
+       fmsub.h         fa0, fa1, fa2, fa3, rne
+       fnmsub.h        fa0, fa1, fa2, fa3
+       fnmsub.h        fa0, fa1, fa2, fa3, rne
+
+       fcvt.w.h        a0, fa1
+       fcvt.w.h        a0, fa1, rne
+       fcvt.wu.h       a0, fa1
+       fcvt.wu.h       a0, fa1, rne
+       fcvt.h.w        fa0, a1
+       fcvt.h.w        fa0, a1, rne
+       fcvt.h.wu       fa0, a1
+       fcvt.h.wu       fa0, a1, rne
+       fcvt.l.h        a0, fa1
+       fcvt.l.h        a0, fa1, rne
+       fcvt.lu.h       a0, fa1
+       fcvt.lu.h       a0, fa1, rne
+       fcvt.h.l        fa0, a1
+       fcvt.h.l        fa0, a1, rne
+       fcvt.h.lu       fa0, a1
+       fcvt.h.lu       fa0, a1, rne
+
+       fmv.x.h         a0, fa1
+       fmv.h.x         fa0, a1
+
+       fcvt.s.h        fa0, fa1
+       fcvt.d.h        fa0, fa1
+       fcvt.q.h        fa0, fa1
+       fcvt.h.s        fa0, fa1
+       fcvt.h.s        fa0, fa1, rne
+       fcvt.h.d        fa0, fa1
+       fcvt.h.d        fa0, fa1, rne
+       fcvt.h.q        fa0, fa1
+       fcvt.h.q        fa0, fa1, rne
+       fclass.h        a0, fa1
+
+       feq.h           a0, fa1, fa2
+       flt.h           a0, fa1, fa2
+       fle.h           a0, fa1, fa2
+       fgt.h           a0, fa2, fa1
+       fge.h           a0, fa2, fa1

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 15e405bc14ea952ea5bfabd2b0eb0799cf6b5b6a..ecbb8b8487b4865db1e081d163bbbe23f8ee0ca8 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -705,6 +705,78 @@
 #define MASK_AES64DSM  0xfe00707f
 #define MATCH_AES64DS 0x3a000033
 #define MASK_AES64DS  0xfe00707f
+#define MATCH_FADD_H 0x4000053
+#define MASK_FADD_H 0xfe00007f
+#define MATCH_FSUB_H 0xc000053
+#define MASK_FSUB_H 0xfe00007f
+#define MATCH_FMUL_H 0x14000053
+#define MASK_FMUL_H 0xfe00007f
+#define MATCH_FDIV_H 0x1c000053
+#define MASK_FDIV_H 0xfe00007f
+#define MATCH_FSGNJ_H 0x24000053
+#define MASK_FSGNJ_H 0xfe00707f
+#define MATCH_FSGNJN_H 0x24001053
+#define MASK_FSGNJN_H 0xfe00707f
+#define MATCH_FSGNJX_H 0x24002053
+#define MASK_FSGNJX_H 0xfe00707f
+#define MATCH_FMIN_H 0x2c000053
+#define MASK_FMIN_H 0xfe00707f
+#define MATCH_FMAX_H 0x2c001053
+#define MASK_FMAX_H 0xfe00707f
+#define MATCH_FCVT_H_S 0x44000053
+#define MASK_FCVT_H_S 0xfff0007f
+#define MATCH_FCVT_S_H 0x40200053
+#define MASK_FCVT_S_H 0xfff0007f
+#define MATCH_FSQRT_H 0x5c000053
+#define MASK_FSQRT_H 0xfff0007f
+#define MATCH_FLE_H 0xa4000053
+#define MASK_FLE_H 0xfe00707f
+#define MATCH_FLT_H 0xa4001053
+#define MASK_FLT_H 0xfe00707f
+#define MATCH_FEQ_H 0xa4002053
+#define MASK_FEQ_H 0xfe00707f
+#define MATCH_FCVT_W_H 0xc4000053
+#define MASK_FCVT_W_H 0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H 0xfff0007f
+#define MATCH_FMV_X_H 0xe4000053
+#define MASK_FMV_X_H 0xfff0707f
+#define MATCH_FCLASS_H 0xe4001053
+#define MASK_FCLASS_H 0xfff0707f
+#define MATCH_FCVT_H_W 0xd4000053
+#define MASK_FCVT_H_W 0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU 0xfff0007f
+#define MATCH_FMV_H_X 0xf4000053
+#define MASK_FMV_H_X 0xfff0707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH 0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH 0x707f
+#define MATCH_FMADD_H 0x4000043
+#define MASK_FMADD_H 0x600007f
+#define MATCH_FMSUB_H 0x4000047
+#define MASK_FMSUB_H 0x600007f
+#define MATCH_FNMSUB_H 0x400004b
+#define MASK_FNMSUB_H 0x600007f
+#define MATCH_FNMADD_H 0x400004f
+#define MASK_FNMADD_H 0x600007f
+#define MATCH_FCVT_H_D 0x44100053
+#define MASK_FCVT_H_D 0xfff0007f
+#define MATCH_FCVT_D_H 0x42200053
+#define MASK_FCVT_D_H 0xfff0007f
+#define MATCH_FCVT_H_Q 0x44300053
+#define MASK_FCVT_H_Q 0xfff0007f
+#define MATCH_FCVT_Q_H 0x46200053
+#define MASK_FCVT_Q_H 0xfff0007f
+#define MATCH_FCVT_L_H 0xc4200053
+#define MASK_FCVT_L_H 0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H 0xfff0007f
+#define MATCH_FCVT_H_L 0xd4200053
+#define MASK_FCVT_H_L 0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU 0xfff0007f
 #define MATCH_VSETVL  0x80007057
 #define MASK_VSETVL  0xfe00707f
 #define MATCH_VSETIVLI  0xc0007057

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b769769b4ecadd03b4a03e0ba010da9bb81fb09b..0d1fbcf8fc5e10333f05b860f78f0905f6b20ac0 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -370,6 +370,9 @@ enum riscv_insn_class
   INSN_CLASS_F_OR_ZFINX,
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,
+  INSN_CLASS_ZFH,
+  INSN_CLASS_D_AND_ZFH,
+  INSN_CLASS_Q_AND_ZFH,
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,
@@ -498,6 +501,8 @@ enum
   M_SEXTH,
   M_VMSGE,
   M_VMSGEU,
+  M_FLH,
+  M_FSH,
   M_NUM_MACROS
 };
 

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 00108ff24ae4c013f85fd5f9d43e593b1666eb63..7524be7feae6e8a8f378f4626383da163608c743 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -572,6 +572,71 @@ const struct riscv_opcode riscv_opcodes[] =
 {"remw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
 {"remuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
+/* Half-precision floating-point instruction subset.  */
+{"flh",        0, INSN_CLASS_ZFH,  "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh",        0, INSN_CLASS_ZFH,  "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
+{"fsh",        0, INSN_CLASS_ZFH,  "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh",        0, INSN_CLASS_ZFH,  "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
+{"fmv.h",      0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.h",     0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h",     0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h",    0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h",   0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h",   0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH,  "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH,  "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h",   0, INSN_CLASS_ZFH,  "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH,  "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH,  "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFH,  "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFH,  "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,  "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,  "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,  "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,  "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fclass.h",   0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h",      0, INSN_CLASS_ZFH,  "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h",      0, INSN_CLASS_ZFH,  "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fmv.x.h",    0, INSN_CLASS_ZFH,  "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x",    0, INSN_CLASS_ZFH,  "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+
 /* Single-precision floating-point instruction subset.  */
 {"frcsr",      0, INSN_CLASS_F,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
 {"frsr",       0, INSN_CLASS_F,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },