[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Fri, 22 May 2020 20:31:58 +0000 (20:31 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 22 May 2020 20:32:00 +0000 (21:32 +0100)
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+Date: Fri, 22 May 2020 20:31:58 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-195-13-95mAS6gszf@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 195] Formal correctness framework is needed
+ for Power ISA
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