build/
autom4te.cache/
+.*.swp
#define NFPR (h->get_ct_state()->nfpr)
#define MAXVL (h->get_ct_state()->maxvl)
#define VL (h->get_ct_state()->vl)
+#define UTIDX (h->get_ct_state()->count)
#define VF_PC (h->get_ct_state()->vf_pc)
#define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
#define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
#define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
#define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
+#define WRITE_UTIDX(value) (h->get_ct_state()->count = (value))
#define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
#define INSN_RS1 (insn.rs1())
#include "hwacha.h"
#include "hwacha_xcpt.h"
-#define UTIDX (i)
-
#undef RS1
#undef RS2
#undef WRITE_RD
#undef require_fp
#define require_fp
-// YUNSUP FIXME
-#undef set_fp_exceptions
-#define set_fp_exceptions
-
#endif
#include "hwacha.h"
#include "hwacha_xcpt.h"
+#include "mmu.h"
#include "trap.h"
+#include <stdexcept>
void ct_state_t::reset()
{
- vl = 0;
- maxvl = 32;
nxpr = 32;
nfpr = 32;
+ maxvl = 32;
+ vl = 0;
+ count = 0;
vf_pc = -1;
-
- cause = 0;
- aux = 0;
}
void ut_state_t::reset()
return false;
}
-void hwacha_t::take_exception(reg_t cause, reg_t aux)
+void hwacha_t::take_exception(reg_t c, reg_t a)
{
- get_ct_state()->cause = cause;
- get_ct_state()->aux = aux;
+ cause = c;
+ aux = a;
raise_interrupt();
if (!(p->get_state()->sr & SR_EI))
throw std::logic_error("hwacha exception posted, but SR_EI bit not set!");
uint32_t nfpr;
uint32_t maxvl;
uint32_t vl;
+ uint32_t count;
reg_t vf_pc;
-
- reg_t cause;
- reg_t aux;
};
struct ut_state_t
class hwacha_t : public extension_t
{
public:
+ hwacha_t() : cause(0), aux(0), debug(false) {}
std::vector<insn_desc_t> get_instructions();
+ std::vector<disasm_insn_t*> get_disasms();
const char* name() { return "hwacha"; }
void reset();
+ void set_debug(bool value) { debug = value; }
ct_state_t* get_ct_state() { return &ct_state; }
ut_state_t* get_ut_state(int idx) { return &ut_state[idx]; }
bool vf_active();
+ reg_t get_cause() { return cause; }
+ reg_t get_aux() { return aux; }
void take_exception(reg_t, reg_t);
void clear_exception() { clear_interrupt(); }
-private:
+ bool get_debug() { return debug; }
+ disassembler_t* get_ut_disassembler() { return &ut_disassembler; }
+
static const int max_uts = 2048;
+
+private:
ct_state_t ct_state;
ut_state_t ut_state[max_uts];
+ reg_t cause;
+ reg_t aux;
+
+ disassembler_t ut_disassembler;
+ bool debug;
};
REGISTER_EXTENSION(hwacha, []() { return new hwacha_t; })
hwacha_hdrs = \
hwacha.h \
+ hwacha_xcpt.h \
decode_hwacha.h \
decode_hwacha_ut.h \
opcodes_hwacha.h \
hwacha_srcs = \
hwacha.cc \
+ hwacha_disasm.cc \
$(hwacha_gen_srcs) \
$(hwacha_ut_gen_srcs) \
--- /dev/null
+#include "hwacha.h"
+
+static const char* xpr[] = {
+ "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
+ "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp",
+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp"
+};
+
+static const char* fpr[] = {
+ "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
+ "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+ "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5"
+};
+
+static const char* vxpr[] = {
+ "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7",
+ "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
+ "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
+ "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
+};
+
+static const char* vfpr[] = {
+ "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7",
+ "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
+ "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
+ "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
+};
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return xpr[insn.rs1()];
+ }
+} xrs1;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return xpr[insn.rs2()];
+ }
+} xrs2;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return xpr[insn.rd()];
+ }
+} xrd;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return fpr[insn.rd()];
+ }
+} frd;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return fpr[insn.rs1()];
+ }
+} frs1;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return fpr[insn.rs2()];
+ }
+} frs2;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return fpr[insn.rs3()];
+ }
+} frs3;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return vxpr[insn.rd()];
+ }
+} vxrd;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return vxpr[insn.rs1()];
+ }
+} vxrs1;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return vfpr[insn.rd()];
+ }
+} vfrd;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return vfpr[insn.rs1()];
+ }
+} vfrs1;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return std::to_string(insn.i_imm() & 0x3f);
+ }
+} nxregs;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return std::to_string((insn.i_imm() >> 6) & 0x3f);
+ }
+} nfregs;
+
+struct : public arg_t {
+ std::string to_string(insn_t insn) const {
+ return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
+ }
+} vf_addr;
+
+std::vector<disasm_insn_t*> hwacha_t::get_disasms()
+{
+ std::vector<disasm_insn_t*> insns;
+
+ #define DECLARE_INSN(code, match, mask) \
+ const uint32_t match_##code = match; \
+ const uint32_t mask_##code = mask;
+ #include "opcodes_hwacha.h"
+ #undef DECLARE_INSN
+
+ #define DISASM_INSN(name, code, extra, ...) \
+ insns.push_back(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
+
+ DISASM_INSN("vsetcfg", vsetcfg, 0, {&xrs1, &nxregs, &nfregs});
+ DISASM_INSN("vsetvl", vsetvl, 0, {&xrd, &xrs1});
+ DISASM_INSN("vgetcfg", vgetcfg, 0, {&xrd});
+ DISASM_INSN("vgetvl", vgetvl, 0, {&xrd});
+
+ DISASM_INSN("vmvv", vmvv, 0, {&vxrd, &vxrs1});
+ DISASM_INSN("vmsv", vmsv, 0, {&vxrd, &xrs1});
+ DISASM_INSN("vf", vf, 0, {&vf_addr});
+
+ DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});
+ DISASM_INSN("vxcptaux", vxcptaux, 0, {&xrd});
+ DISASM_INSN("vxcptsave", vxcptsave, 0, {&xrs1});
+ DISASM_INSN("vxcptrestore", vxcptrestore, 0, {&xrs1});
+ DISASM_INSN("vxcptkill", vxcptkill, 0, {});
+
+ const uint32_t mask_vseglen = 0x7UL << 29;
+
+ #define DISASM_VMEM_INSN(name1, name2, code, ...) \
+ DISASM_INSN(name1, code, mask_vseglen, __VA_ARGS__) \
+ DISASM_INSN(name2, code, 0, __VA_ARGS__) \
+
+ DISASM_VMEM_INSN("vld", "vlsegd", vlsegd, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlw", "vlsegw", vlsegw, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlwu", "vlsegwu", vlsegwu, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlh", "vlsegh", vlsegh, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlhu", "vlseghu", vlseghu, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlb", "vlsegb", vlsegb, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vlbu", "vlsegbu", vlsegbu, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vfld", "vflsegd", vflsegd, {&vfrd, &xrs1});
+ DISASM_VMEM_INSN("vflw", "vflsegw", vflsegw, {&vfrd, &xrs1});
+
+ DISASM_VMEM_INSN("vlstd", "vlsegstd", vlsegstd, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlstw", "vlsegstw", vlsegstw, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlstwu", "vlsegstwu", vlsegstwu, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlsth", "vlsegsth", vlsegsth, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlsthu", "vlsegsthu", vlsegsthu, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlstb", "vlsegstb", vlsegstb, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vlstbu", "vlsegstbu", vlsegstbu, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vflstd", "vflsegstd", vflsegstd, {&vfrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vflstw", "vflsegstw", vflsegstw, {&vfrd, &xrs1, &xrs2});
+
+ DISASM_VMEM_INSN("vsd", "vssegd", vssegd, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vsw", "vssegw", vssegw, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vsh", "vssegh", vssegh, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vsb", "vssegb", vssegb, {&vxrd, &xrs1});
+ DISASM_VMEM_INSN("vfsd", "vfssegd", vfssegd, {&vfrd, &xrs1});
+ DISASM_VMEM_INSN("vfsw", "vfssegw", vfssegw, {&vfrd, &xrs1});
+
+ DISASM_VMEM_INSN("vsstd", "vssegstd", vssegstd, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vsstw", "vssegstw", vssegstw, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vssth", "vssegsth", vssegsth, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vsstb", "vssegstb", vssegstb, {&vxrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vfsstd", "vfssegstd", vfssegstd, {&vfrd, &xrs1, &xrs2});
+ DISASM_VMEM_INSN("vfsstw", "vfssegstw", vfssegstw, {&vfrd, &xrs1, &xrs2});
+
+ #define DECLARE_INSN(code, match, mask) \
+ const uint32_t match_##code = match; \
+ const uint32_t mask_##code = mask;
+ #include "opcodes_hwacha_ut.h"
+ #undef DECLARE_INSN
+
+ #define DISASM_UT_INSN(name, code, extra, ...) \
+ ut_disassembler.add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
+
+ DISASM_UT_INSN("stop", ut_stop, 0, {});
+ DISASM_UT_INSN("utidx", ut_utidx, 0, {&xrd});
+ DISASM_UT_INSN("movz", ut_movz, 0, {&xrd, &xrs1, &xrs2});
+ DISASM_UT_INSN("movn", ut_movn, 0, {&xrd, &xrs1, &xrs2});
+ DISASM_UT_INSN("fmovz", ut_fmovz, 0, {&frd, &xrs1, &frs2});
+ DISASM_UT_INSN("fmovn", ut_fmovn, 0, {&frd, &xrs1, &frs2});
+
+ return insns;
+}
int xprlen = 64;
reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
- for (uint32_t i=0; i<VL; i++) {
+ do {
#include "insns_ut/NAME.h"
- }
+ WRITE_UTIDX(UTIDX+1);
+ } while (UTIDX < VL);
+ WRITE_UTIDX(0);
return npc;
}
h->get_ut_state(i)->run = true;
}
+vf_loop:
+
if (VF_PC & 3)
h->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH, VF_PC);
- mmu_t::insn_fetch_t ut_fetch = p->get_mmu()->load_insn(VF_PC);
- insn_t ut_insn = ut_fetch.insn.insn;
+ insn_t ut_insn = p->get_mmu()->load_insn(VF_PC).insn.insn;
bool matched = false;
if (!matched)
h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION, VF_PC);
- // if vf is still running, rewind pc so that it will execute again
- if (h->vf_active())
- npc = pc;
+ if (!h->get_debug()) {
+ if (h->vf_active())
+ goto vf_loop;
+ } else {
+ fprintf(stderr, "vf block: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+ VF_PC, ut_insn.bits(), h->get_ut_disassembler()->disassemble(ut_insn).c_str());
+ if (h->vf_active())
+ npc = pc;
+ }
}
require_supervisor_hwacha;
-xd = h->get_ct_state()->aux;
+xd = h->get_aux();
require_supervisor_hwacha;
h->clear_exception();
-xd = h->get_ct_state()->cause;
+xd = h->get_cause();
require_supervisor_hwacha;
-for (uint32_t i=0; i<VL; i++)
- h->get_ut_state(i)->run = false;
+h->get_ct_state()->reset();
+for (uint32_t i=0; i<h->max_uts; i++)
+ h->get_ut_state(i)->reset();
require_supervisor_hwacha;
+reg_t addr = XS1;
+
+#define LOAD_B(addr) \
+ (addr += 1, p->get_mmu()->load_uint8(addr-1))
+
+#define LOAD_W(addr) \
+ (addr += 4, p->get_mmu()->load_uint32(addr-4))
+
+#define LOAD_D(addr) \
+ (addr += 8, p->get_mmu()->load_uint64(addr-8))
+
+
+WRITE_NXPR(LOAD_W(addr));
+WRITE_NFPR(LOAD_W(addr));
+WRITE_MAXVL(LOAD_W(addr));
+WRITE_VL(LOAD_W(addr));
+WRITE_UTIDX(LOAD_W(addr));
+addr += 4;
+WRITE_VF_PC(LOAD_D(addr));
+
+for (uint32_t x=1; x<NXPR; x++) {
+ for (uint32_t i=0; i<VL; i++) {
+ UT_WRITE_XPR(i, x, LOAD_D(addr));
+ }
+}
+
+for (uint32_t f=0; f<NFPR; f++) {
+ for (uint32_t i=0; i<VL; i++) {
+ UT_WRITE_FPR(i, f, LOAD_D(addr));
+ }
+}
+
+for (uint32_t i=0; i<VL; i++) {
+ h->get_ut_state(i)->run = LOAD_B(addr);
+}
+
+#undef LOAD_B
+#undef LOAD_W
+#undef LOAD_D
require_supervisor_hwacha;
+reg_t addr = XS1;
+
+#define STORE_B(addr, value) \
+ p->get_mmu()->store_uint8(addr, value); \
+ addr += 1; \
+
+#define STORE_W(addr, value) \
+ p->get_mmu()->store_uint32(addr, value); \
+ addr += 4; \
+
+#define STORE_D(addr, value) \
+ p->get_mmu()->store_uint64(addr, value); \
+ addr += 8; \
+
+STORE_W(addr, NXPR);
+STORE_W(addr, NFPR);
+STORE_W(addr, MAXVL);
+STORE_W(addr, VL);
+STORE_W(addr, UTIDX);
+addr += 4;
+STORE_D(addr, VF_PC);
+
+for (uint32_t x=1; x<NXPR; x++) {
+ for (uint32_t i=0; i<VL; i++) {
+ STORE_D(addr, UT_READ_XPR(i, x));
+ }
+}
+
+for (uint32_t f=0; f<NFPR; f++) {
+ for (uint32_t i=0; i<VL; i++) {
+ STORE_D(addr, UT_READ_FPR(i, f));
+ }
+}
+
+for (uint32_t i=0; i<VL; i++) {
+ STORE_B(addr, h->get_ut_state(i)->run);
+}
+
+#undef STORE_B
+#undef STORE_W
+#undef STORE_D
+
+#include "insns/vxcptkill.h"
+++ /dev/null
-../../riscv/insns/frsr.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fssr.h
\ No newline at end of file
DECLARE_INSN(ut_fcvt_s_wu, 0x78000053, 0xfff0007f)
DECLARE_INSN(ut_fcvt_d_l, 0x62000053, 0xfff0007f)
DECLARE_INSN(ut_lh, 0x1003, 0x707f)
-DECLARE_INSN(ut_frsr, 0xe8000053, 0xfffff07f)
DECLARE_INSN(ut_fcvt_d_w, 0x72000053, 0xfff0007f)
DECLARE_INSN(ut_lw, 0x2003, 0x707f)
DECLARE_INSN(ut_add, 0x33, 0xfe00707f)
DECLARE_INSN(ut_fsgnj_d, 0x2a000053, 0xfe00707f)
DECLARE_INSN(ut_mulhu, 0x2003033, 0xfe00707f)
DECLARE_INSN(ut_fcvt_l_d, 0x42000053, 0xfff0007f)
-DECLARE_INSN(ut_fssr, 0xf8000053, 0xfff0707f)
DECLARE_INSN(ut_fcvt_lu_s, 0x48000053, 0xfff0007f)
DECLARE_INSN(ut_fcvt_s_l, 0x60000053, 0xfff0007f)
DECLARE_INSN(ut_auipc, 0x17, 0x7f)
#include <cstdarg>
#include <sstream>
#include <stdlib.h>
-using namespace std;
-
-class arg_t
-{
- public:
- virtual string to_string(insn_t val) const = 0;
- virtual ~arg_t() {}
-};
static const char* xpr[] = {
"zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
"fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5"
};
-static const char* vxpr[] = {
- "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7",
- "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
- "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
- "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
-};
-
-static const char* vfpr[] = {
- "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7",
- "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
- "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
- "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
-};
-
struct : public arg_t {
- string to_string(insn_t insn) const {
- return ::to_string((int)insn.i_imm()) + '(' + xpr[insn.rs1()] + ')';
+ std::string to_string(insn_t insn) const {
+ return std::to_string((int)insn.i_imm()) + '(' + xpr[insn.rs1()] + ')';
}
} load_address;
struct : public arg_t {
- string to_string(insn_t insn) const {
- return ::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
+ std::string to_string(insn_t insn) const {
+ return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
}
} store_address;
struct : public arg_t {
- string to_string(insn_t insn) const {
- return string("0(") + xpr[insn.rs1()] + ')';
+ std::string to_string(insn_t insn) const {
+ return std::string("0(") + xpr[insn.rs1()] + ')';
}
} amo_address;
struct : public arg_t {
std::string to_string(insn_t insn) const {
- return vxpr[insn.rd()];
- }
-} vxrd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vxpr[insn.rs1()];
- }
-} vxrs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vfpr[insn.rd()];
- }
-} vfrd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vfpr[insn.rs1()];
- }
-} vfrs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return ::to_string(insn.i_imm() & 0x3f);
- }
-} nxregs;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return ::to_string((insn.i_imm() >> 6) & 0x3f);
- }
-} nfregs;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return string("pcr") + xpr[insn.rs1()];
+ return std::string("pcr") + xpr[insn.rs1()];
}
} pcr;
struct : public arg_t {
std::string to_string(insn_t insn) const {
- return ::to_string((int)insn.i_imm());
+ return std::to_string((int)insn.i_imm());
}
} imm;
}
} jump_target;
-class disasm_insn_t
-{
- public:
- disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
- const std::vector<const arg_t*>& args)
- : match(match), mask(mask), args(args), name(name) {}
-
- bool operator == (insn_t insn) const
- {
- return (insn.bits() & mask) == match;
- }
-
- std::string to_string(insn_t insn) const
- {
- std::stringstream s;
- int len;
- for (len = 0; name[len]; len++)
- s << (name[len] == '_' ? '.' : name[len]);
-
- if (args.size())
- {
- s << std::string(std::max(1, 8 - len), ' ');
- for (size_t i = 0; i < args.size()-1; i++)
- s << args[i]->to_string(insn) << ", ";
- s << args[args.size()-1]->to_string(insn);
- }
- return s.str();
- }
-
- uint32_t get_match() const { return match; }
- uint32_t get_mask() const { return mask; }
-
- private:
- uint32_t match;
- uint32_t mask;
- std::vector<const arg_t*> args;
- const char* name;
-};
-
-std::string disassembler::disassemble(insn_t insn)
+std::string disassembler_t::disassemble(insn_t insn)
{
const disasm_insn_t* disasm_insn = lookup(insn);
return disasm_insn ? disasm_insn->to_string(insn) : "unknown";
}
-disassembler::disassembler()
+disassembler_t::disassembler_t()
{
const uint32_t mask_rd = 0x1fUL << 7;
const uint32_t match_rd_ra = 1UL << 7;
#undef DECLARE_INSN
}
-const disasm_insn_t* disassembler::lookup(insn_t insn)
+const disasm_insn_t* disassembler_t::lookup(insn_t insn)
{
size_t idx = insn.bits() % HASH_SIZE;
for (size_t j = 0; j < chain[idx].size(); j++)
return NULL;
}
-void disassembler::add_insn(disasm_insn_t* insn)
+void disassembler_t::add_insn(disasm_insn_t* insn)
{
size_t idx = HASH_SIZE;
if (insn->get_mask() % HASH_SIZE == HASH_SIZE - 1)
chain[idx].push_back(insn);
}
-disassembler::~disassembler()
+disassembler_t::~disassembler_t()
{
for (size_t i = 0; i < HASH_SIZE+1; i++)
for (size_t j = 0; j < chain[i].size(); j++)
#include "decode.h"
#include <string>
+#include <sstream>
#include <vector>
-struct disasm_insn_t;
+class arg_t
+{
+ public:
+ virtual std::string to_string(insn_t val) const = 0;
+ virtual ~arg_t() {}
+};
-class disassembler
+class disasm_insn_t
{
public:
- disassembler();
- ~disassembler();
+ disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
+ const std::vector<const arg_t*>& args)
+ : match(match), mask(mask), args(args), name(name) {}
+
+ bool operator == (insn_t insn) const
+ {
+ return (insn.bits() & mask) == match;
+ }
+
+ std::string to_string(insn_t insn) const
+ {
+ std::stringstream s;
+ int len;
+ for (len = 0; name[len]; len++)
+ s << (name[len] == '_' ? '.' : name[len]);
+
+ if (args.size())
+ {
+ s << std::string(std::max(1, 8 - len), ' ');
+ for (size_t i = 0; i < args.size()-1; i++)
+ s << args[i]->to_string(insn) << ", ";
+ s << args[args.size()-1]->to_string(insn);
+ }
+ return s.str();
+ }
+
+ uint32_t get_match() const { return match; }
+ uint32_t get_mask() const { return mask; }
+
+ private:
+ uint32_t match;
+ uint32_t mask;
+ std::vector<const arg_t*> args;
+ const char* name;
+};
+
+class disassembler_t
+{
+ public:
+ disassembler_t();
+ ~disassembler_t();
std::string disassemble(insn_t insn);
+ void add_insn(disasm_insn_t* insn);
private:
static const int HASH_SIZE = 256;
std::vector<const disasm_insn_t*> chain[HASH_SIZE+1];
- void add_insn(disasm_insn_t* insn);
const disasm_insn_t* lookup(insn_t insn);
};
#define _RISCV_COPROCESSOR_H
#include "processor.h"
+#include "disasm.h"
#include <map>
#include <string>
#include <vector>
{
public:
virtual std::vector<insn_desc_t> get_instructions() = 0;
+ virtual std::vector<disasm_insn_t*> get_disasms() = 0;
virtual const char* name() = 0;
virtual void reset() {};
+ virtual void set_debug(bool value) {};
virtual ~extension_t();
void set_processor(processor_t* _p) { p = _p; }
if (!(ss >> cmd))
{
- step(1, true);
+ set_procs_debug(true);
+ step(1);
continue;
}
{
size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
ctrlc_pressed = false;
+ set_procs_debug(noisy);
for (size_t i = 0; i < steps && !ctrlc_pressed; i++)
- step(1, noisy);
+ step(1);
}
void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args)
}
catch (trap_t t) {}
- step(1, false);
+ set_procs_debug(false);
+ step(1);
}
}
#define SR_U64 0x00000020
#define SR_S64 0x00000040
#define SR_VM 0x00000080
-#define SR_EV 0x00000100
+#define SR_EA 0x00000100
#define SR_IM 0x00FF0000
#define SR_IP 0xFF000000
-#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
+#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
#define SR_IM_SHIFT 16
#define SR_IP_SHIFT 24
#include <stdexcept>
processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
- : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
+ : sim(_sim), mmu(_mmu), ext(NULL), id(_id), debug(false), opcode_bits(0)
{
reset(true);
mmu->set_processor(this);
load_reservation = -1;
}
+void processor_t::set_debug(bool value)
+{
+ debug = value;
+ if (ext)
+ ext->set_debug(value);
+}
+
void processor_t::reset(bool value)
{
if (run == !value)
throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
}
-void processor_t::step(size_t n, bool noisy)
+void processor_t::step(size_t n)
{
if(!run)
return;
#define execute_insn(noisy) \
do { \
mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
- if(noisy) disasm(fetch.insn.insn, npc); \
+ if(noisy) disasm(fetch.insn.insn); \
npc = fetch.func(this, fetch.insn.insn, npc); \
} while(0)
#define execute_insn(noisy) \
do { \
mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
- if(noisy) disasm(fetch.insn.insn, npc); \
+ if(noisy) disasm(fetch.insn.insn); \
bool in_spvr = state.sr & SR_S; \
if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
/*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
} while(0)
#endif
- if(noisy) for( ; i < n; i++) // print out instructions as we go
+ if(debug) for( ; i < n; i++) // print out instructions as we go
execute_insn(true);
else
{
}
catch(trap_t& t)
{
- take_trap(npc, t, noisy);
+ take_trap(npc, t);
}
state.cycle += i;
set_interrupt(IRQ_TIMER, true);
}
-void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
+void processor_t::take_trap(reg_t pc, trap_t& t)
{
- if (noisy)
+ if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), pc);
set_pcr(PCR_CLR_IPI, 1);
}
-void processor_t::disasm(insn_t insn, reg_t pc)
+void processor_t::disasm(insn_t insn)
{
// the disassembler is stateless, so we share it
- static disassembler disasm;
fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
- id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
+ id, state.pc, insn.bits(), disassembler.disassemble(insn).c_str());
}
reg_t processor_t::set_pcr(int which, reg_t val)
#ifndef RISCV_ENABLE_FPU
state.sr &= ~SR_EF;
#endif
-#ifndef RISCV_ENABLE_VEC
- state.sr &= ~SR_EV;
-#endif
+ if (!ext)
+ state.sr &= ~SR_EA;
state.sr &= ~SR_ZERO;
mmu->flush_tlb();
break;
{
for (auto insn : x->get_instructions())
register_insn(insn);
+ for (auto disasm_insn : x->get_disasms())
+ disassembler.add_insn(disasm_insn);
if (ext != NULL)
throw std::logic_error("only one extension may be registered");
ext = x;
// See LICENSE for license details.
-
#ifndef _RISCV_PROCESSOR_H
#define _RISCV_PROCESSOR_H
#include "decode.h"
+#include "disasm.h"
#include <cstring>
#include "config.h"
#include <map>
processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
~processor_t();
+ void set_debug(bool value);
void reset(bool value);
- void step(size_t n, bool noisy); // run for n cycles
+ void step(size_t n); // run for n cycles
void deliver_ipi(); // register an interprocessor interrupt
bool running() { return run; }
reg_t set_pcr(int which, reg_t val);
sim_t* sim;
mmu_t* mmu; // main memory is always accessed via the mmu
extension_t* ext;
+ disassembler_t disassembler;
state_t state;
uint32_t id;
bool run; // !reset
+ bool debug;
unsigned opcode_bits;
std::multimap<uint32_t, insn_desc_t> opcode_map;
void take_interrupt(); // take a trap if any interrupts are pending
- void take_trap(reg_t pc, trap_t& t, bool noisy); // take an exception
- void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
+ void take_trap(reg_t pc, trap_t& t); // take an exception
+ void disasm(insn_t insn); // disassemble and print an instruction
friend class sim_t;
friend class mmu_t;
int main()
{
string s;
- disassembler d;
+ disassembler_t d;
while (getline(cin, s))
{
insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
return insns;
}
+
+std::vector<disasm_insn_t*> rocc_t::get_disasms()
+{
+ std::vector<disasm_insn_t*> insns;
+ return insns;
+}
virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2);
virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2);
std::vector<insn_desc_t> get_instructions();
+ std::vector<disasm_insn_t*> get_disasms();
};
#endif
}
}
-void sim_t::run()
+int sim_t::run()
{
while (htif->tick())
{
if (debug || ctrlc_pressed)
interactive();
else
- step(INTERLEAVE, false);
+ step(INTERLEAVE);
}
+ return htif->exit_code();
}
-void sim_t::step(size_t n, bool noisy)
+void sim_t::step(size_t n)
{
for (size_t i = 0, steps = 0; i < n; i += steps)
{
steps = std::min(n - i, INTERLEAVE - current_step);
- procs[current_proc]->step(steps, noisy);
+ procs[current_proc]->step(steps);
current_step += steps;
if (current_step == INTERLEAVE)
while (htif->tick())
;
}
+
+void sim_t::set_debug(bool value)
+{
+ debug = value;
+}
+
+void sim_t::set_procs_debug(bool value)
+{
+ for (size_t i=0; i< procs.size(); i++)
+ procs[i]->set_debug(value);
+}
~sim_t();
// run the simulation to completion
- void run();
+ int run();
bool running();
void stop();
- void set_debug(bool value) { debug = value; }
+ void set_debug(bool value);
+ void set_procs_debug(bool value);
// deliver an IPI to a specific processor
void send_ipi(reg_t who);
mmu_t* debug_mmu; // debug port into main memory
std::vector<processor_t*> procs;
- void step(size_t n, bool noisy); // step through simulation
+ void step(size_t n); // step through simulation
static const size_t INTERLEAVE = 5000;
size_t current_step;
size_t current_proc;
}
s.set_debug(debug);
- s.run();
+ return s.run();
}
projects / riscv-isa-sim.git / commitdiff