set reset from ResetSignal not straight to 1 for HyperRAM

put correct IOPad names into HyperRAMResource for arty a7

diff --git a/src/ls2.py b/src/ls2.py
index 688fea120e94b97bd4e34d28a27746a88e468b65..21a71fa81659772dc403fe217cc4f63a3f4134b2 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -484,7 +484,7 @@ class DDR3SoC(SoC, Elaboratable):
             comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack)
             # set 3 top CSn lines to zero for now
             if self.fpga == 'arty_a7':
-                comb += hyperram.phy.rst_n.eq(1)
+                comb += hyperram.phy.rst_n.eq(ResetSignal())
 
         # add blinky lights so we know FPGA is alive
         if platform is not None:
@@ -646,7 +646,7 @@ def build_platform(fpga, firmware):
     if platform is None:
         hyperram_pins = HyperRAMPads()
     elif fpga in ['isim']:
-        hyperram_ios = HyperRAMResource(0, cs_n="V12 V14 V12 U12",
+        hyperram_ios = HyperRAMResource(0, cs_n="V12 V14 U12 U14",
                                         dq="D4 D3 F4 F3 G2 H2 D2 E2",
                                         rwds="U13", rst_n="T13", ck_p="V10",
                                         # ck_n="V11" - for later (DDR)
@@ -656,10 +656,10 @@ def build_platform(fpga, firmware):
         print ("isim a7 hyperram", hyperram_ios)
     # Digilent Arty A7-100t
     elif platform is not None and fpga in ['arty_a7']:
-        hyperram_ios = HyperRAMResource(0, cs_n="B11",
+        hyperram_ios = HyperRAMResource(0, cs_n="V12 V14 U12 U14",
                                         dq="D4 D3 F4 F3 G2 H2 D2 E2",
                                         rwds="U13", rst_n="T13", ck_p="V10",
-                                        # ck_n="D12" - for later (DDR)
+                                        # ck_n="V11" - for later (DDR)
                                         attrs=Attrs(IOSTANDARD="LVCMOS33"))
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")