---------- Begin Simulation Statistics ----------
-sim_seconds 2.607938 # Number of seconds simulated
-sim_ticks 2607938427000 # Number of ticks simulated
-final_tick 2607938427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.607932 # Number of seconds simulated
+sim_ticks 2607931908500 # Number of ticks simulated
+final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67776 # Simulator instruction rate (inst/s)
-host_op_rate 81630 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2816320200 # Simulator tick rate (ticks/s)
-host_mem_usage 438748 # Number of bytes of host memory used
-host_seconds 926.01 # Real time elapsed on the host
-sim_insts 62761521 # Number of instructions simulated
-sim_ops 75590331 # Number of ops (including micro ops) simulated
+host_inst_rate 52184 # Simulator instruction rate (inst/s)
+host_op_rate 62850 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2168410643 # Simulator tick rate (ticks/s)
+host_mem_usage 492092 # Number of bytes of host memory used
+host_seconds 1202.69 # Real time elapsed on the host
+sim_insts 62761278 # Number of instructions simulated
+sim_ops 75589768 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 121488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 457468 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 4606656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 70992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 622136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 5389248 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132379476 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 121488 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 70992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 192480 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4393536 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7422672 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 4422 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 7207 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 71979 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1152 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9739 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 84207 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15317537 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 68649 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 825933 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46439182 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 98 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 46584 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 175414 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 1766398 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 27222 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 238555 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 2066478 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50760200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 46584 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 27222 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 73805 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1684678 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 1154987 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2846184 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1684678 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46439182 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 98 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 46584 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 181932 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 1766398 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 27222 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1393542 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 2066478 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53606384 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15317537 # Number of read requests accepted
-system.physmem.writeReqs 825933 # Number of write requests accepted
-system.physmem.readBursts 15317537 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 825933 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 976408384 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3913984 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7445376 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 132379476 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7422672 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 61156 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709570 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 15921 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 957324 # Per bank write bursts
-system.physmem.perBankRdBursts::1 954296 # Per bank write bursts
-system.physmem.perBankRdBursts::2 951048 # Per bank write bursts
-system.physmem.perBankRdBursts::3 951190 # Per bank write bursts
-system.physmem.perBankRdBursts::4 960560 # Per bank write bursts
-system.physmem.perBankRdBursts::5 954642 # Per bank write bursts
-system.physmem.perBankRdBursts::6 950634 # Per bank write bursts
-system.physmem.perBankRdBursts::7 950367 # Per bank write bursts
-system.physmem.perBankRdBursts::8 957475 # Per bank write bursts
-system.physmem.perBankRdBursts::9 955236 # Per bank write bursts
-system.physmem.perBankRdBursts::10 950657 # Per bank write bursts
-system.physmem.perBankRdBursts::11 950055 # Per bank write bursts
-system.physmem.perBankRdBursts::12 957021 # Per bank write bursts
-system.physmem.perBankRdBursts::13 954396 # Per bank write bursts
-system.physmem.perBankRdBursts::14 950984 # Per bank write bursts
-system.physmem.perBankRdBursts::15 950496 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7473 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7236 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7209 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7113 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7623 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7510 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7170 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7098 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7538 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7733 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7167 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6553 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7248 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7122 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7350 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7191 # Per bank write bursts
+system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15317443 # Number of read requests accepted
+system.physmem.writeReqs 825902 # Number of write requests accepted
+system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 957415 # Per bank write bursts
+system.physmem.perBankRdBursts::1 954356 # Per bank write bursts
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+system.physmem.perBankRdBursts::6 950562 # Per bank write bursts
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+system.physmem.perBankRdBursts::10 950399 # Per bank write bursts
+system.physmem.perBankRdBursts::11 949996 # Per bank write bursts
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+system.physmem.perBankRdBursts::13 954231 # Per bank write bursts
+system.physmem.perBankRdBursts::14 950565 # Per bank write bursts
+system.physmem.perBankRdBursts::15 950154 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7537 # Per bank write bursts
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+system.physmem.perBankWrBursts::2 7519 # Per bank write bursts
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+system.physmem.perBankWrBursts::4 7525 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7506 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7304 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7173 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7520 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7613 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6934 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6533 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7225 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7011 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7249 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7053 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2607936588500 # Total gap between requests
+system.physmem.totGap 2607930021000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 59 # Read request sizes (log2)
system.physmem.readPktSize::3 15138841 # Read request sizes (log2)
-system.physmem.readPktSize::4 3422 # Read request sizes (log2)
+system.physmem.readPktSize::4 3437 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 175215 # Read request sizes (log2)
+system.physmem.readPktSize::6 175106 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 68649 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1023042 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1020695 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 981592 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 75 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 23 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 17 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 68618 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 963.858515 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 884.982288 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 219.503901 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 33091 3.24% 3.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19420 1.90% 5.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8756 0.86% 6.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2666 0.26% 6.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3150 0.31% 6.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2102 0.21% 6.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8576 0.84% 7.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1045 0.10% 7.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 941939 92.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1020745 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6738 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2264.229742 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 98171.784681 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6732 99.91% 99.91% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads
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-system.physmem.totQLat 399562219250 # Total ticks spent queuing
-system.physmem.totMemAccLat 685619363000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76281905000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26189.84 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44939.84 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 374.40 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 2.95 # Data bus utilization in percentage
system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.38 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.08 # Average write queue length when enqueuing
-system.physmem.readRowHits 14264224 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87746 # Number of row buffer hits during writes
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+system.physmem.writeRowHits 87526 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.41 # Row buffer hit rate for writes
-system.physmem.avgGap 161547.46 # Average gap between requests
+system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes
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system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2277806510000 # Time in different power states
-system.physmem.memoryStateTime::REF 87084660000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 243043451250 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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-system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 16496833 # Transaction distribution
-system.membus.trans_dist::ReadResp 16496833 # Transaction distribution
-system.membus.trans_dist::WriteReq 769198 # Transaction distribution
-system.membus.trans_dist::WriteResp 769198 # Transaction distribution
-system.membus.trans_dist::Writeback 68649 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58344 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 23631 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15921 # Transaction distribution
-system.membus.trans_dist::ReadExReq 15704 # Transaction distribution
-system.membus.trans_dist::ReadExResp 8956 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384374 # Packet count per connected master and slave (bytes)
+system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ)
+system.physmem.averagePower::0 697.255251 # Core power per rank (mW)
+system.physmem.averagePower::1 697.172828 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 16496763 # Transaction distribution
+system.membus.trans_dist::ReadResp 16496763 # Transaction distribution
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+system.membus.trans_dist::ReadExResp 8933 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13882 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 1651156 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1651155 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 769198 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 769198 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 213952 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 63434 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 23959 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 87393 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 23242 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 23242 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760832 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337498 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5098330 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18164043 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24784826 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 42948869 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 177697 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 784039 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 177868 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 784039 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 784039 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2614289788 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1150553389 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2660791344 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution
+system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution
system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8838 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2384374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32662006 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17676 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 2392689 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 123503217 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4425000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2376290000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38179589169 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 6443222 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4514499 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 302125 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3729781 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2837348 # Number of BTB hits
+system.cpu0.branchPred.lookups 6445077 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 76.072777 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 778118 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 15176 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 6735842 # DTB read hits
-system.cpu0.dtb.read_misses 20815 # DTB read misses
-system.cpu0.dtb.write_hits 5107742 # DTB write hits
-system.cpu0.dtb.write_misses 5078 # DTB write misses
+system.cpu0.dtb.read_hits 6738270 # DTB read hits
+system.cpu0.dtb.read_misses 20792 # DTB read misses
+system.cpu0.dtb.write_hits 5108254 # DTB write hits
+system.cpu0.dtb.write_misses 4938 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 367 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 6756657 # DTB read accesses
-system.cpu0.dtb.write_accesses 5112820 # DTB write accesses
+system.cpu0.dtb.read_accesses 6759062 # DTB read accesses
+system.cpu0.dtb.write_accesses 5113192 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 11843584 # DTB hits
-system.cpu0.dtb.misses 25893 # DTB misses
-system.cpu0.dtb.accesses 11869477 # DTB accesses
+system.cpu0.dtb.hits 11846524 # DTB hits
+system.cpu0.dtb.misses 25730 # DTB misses
+system.cpu0.dtb.accesses 11872254 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 11247992 # ITB inst hits
-system.cpu0.itb.inst_misses 5846 # ITB inst misses
+system.cpu0.itb.inst_hits 11251934 # ITB inst hits
+system.cpu0.itb.inst_misses 5844 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1213 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2388 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 11253838 # ITB inst accesses
-system.cpu0.itb.hits 11247992 # DTB hits
-system.cpu0.itb.misses 5846 # DTB misses
-system.cpu0.itb.accesses 11253838 # DTB accesses
-system.cpu0.numCycles 70572029 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses
+system.cpu0.itb.hits 11251934 # DTB hits
+system.cpu0.itb.misses 5844 # DTB misses
+system.cpu0.itb.accesses 11257778 # DTB accesses
+system.cpu0.numCycles 70547986 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 4765934 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 34354024 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6443222 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3615466 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 61748976 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 827418 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 76155 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 31280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 103338 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 2296149 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 8939 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 11248771 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 69018 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 1645 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 69444480 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.597050 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.081482 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 50353589 72.51% 72.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 6606705 9.51% 82.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 2597434 3.74% 85.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 9886752 14.24% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 69444480 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.091300 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.486794 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 6420501 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 48533578 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 12241748 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1929473 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 319180 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 871648 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 96104 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 34913571 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 1200749 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 319180 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 8404067 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 22318095 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 11023940 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 12127048 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 15252150 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 33557627 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 347095 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 4724247 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 2950612 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 10590884 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 2755476 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 34851569 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 154470161 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 39932563 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 3839 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30129647 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4721913 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 454205 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 374005 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4735093 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 6116299 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5560853 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 585692 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 726458 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 32313533 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 795864 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 32787954 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 169648 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 3622039 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 7620869 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 145783 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 69444480 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.472146 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.871579 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 50308599 72.44% 72.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9186806 13.23% 85.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 6613722 9.52% 95.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2968134 4.27% 99.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 366793 0.53% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 426 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 69444480 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 2914015 33.72% 33.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 370 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 2945355 34.08% 67.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 2781781 32.19% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14545 0.04% 0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 20237485 61.72% 61.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 42714 0.13% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 61.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 7055748 21.52% 83.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5436782 16.58% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 32787954 # Type of FU issued
-system.cpu0.iq.rate 0.464603 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 8641521 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.263558 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 143819965 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 36733067 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 31072945 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 11591 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes
+system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued
+system.cpu0.iq.rate 0.464855 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 41407644 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 7286 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 165926 # Number of loads that had data forwarded from stores
+system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 774444 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 6361 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 333599 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 1087774 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 167955 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 319180 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 7637637 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 6671195 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 33211836 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 6116299 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5560853 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 485055 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 10847 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 6650997 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 6361 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 101358 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 128388 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 229746 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 32419905 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 6900946 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 342549 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 102439 # number of nop insts executed
-system.cpu0.iew.exec_refs 12280176 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4698919 # Number of branches executed
-system.cpu0.iew.exec_stores 5379230 # Number of stores executed
-system.cpu0.iew.exec_rate 0.459387 # Inst execution rate
-system.cpu0.iew.wb_sent 32226620 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 31076783 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 15728135 # num instructions producing a value
-system.cpu0.iew.wb_consumers 27168028 # num instructions consuming a value
+system.cpu0.iew.exec_nop 102446 # number of nop insts executed
+system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4700114 # Number of branches executed
+system.cpu0.iew.exec_stores 5379801 # Number of stores executed
+system.cpu0.iew.exec_rate 0.459648 # Inst execution rate
+system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 15739944 # num instructions producing a value
+system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.440356 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.578921 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 3251168 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 650081 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 207596 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 68809072 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.427174 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.181510 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 54941660 79.85% 79.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7926001 11.52% 91.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2553754 3.71% 95.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1118993 1.63% 96.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 777653 1.13% 97.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 424728 0.62% 98.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 260082 0.38% 98.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 241415 0.35% 99.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 564786 0.82% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 68809072 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24063345 # Number of instructions committed
-system.cpu0.commit.committedOps 29393425 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24068410 # Number of instructions committed
+system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 10569108 # Number of memory references committed
-system.cpu0.commit.loads 5341854 # Number of loads committed
-system.cpu0.commit.membars 231843 # Number of memory barriers committed
-system.cpu0.commit.branches 4350514 # Number of branches committed
+system.cpu0.commit.refs 10570507 # Number of memory references committed
+system.cpu0.commit.loads 5342633 # Number of loads committed
+system.cpu0.commit.membars 231974 # Number of memory barriers committed
+system.cpu0.commit.branches 4351471 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 25739481 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 499600 # Number of function calls committed.
+system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 499778 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 18783880 63.91% 63.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 39757 0.14% 64.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 64.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 5341854 18.17% 82.22% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5227254 17.78% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 29393425 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 564786 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 100015321 # The number of ROB reads
-system.cpu0.rob.rob_writes 65887471 # The number of ROB writes
-system.cpu0.timesIdled 89304 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 1127549 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5145313600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23982603 # Number of Instructions Simulated
-system.cpu0.committedOps 29312683 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.942634 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.942634 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.339832 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.339832 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 37149809 # number of integer regfile reads
-system.cpu0.int_regfile_writes 18849024 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads
+system.cpu0.rob.rob_reads 99997744 # The number of ROB reads
+system.cpu0.rob.rob_writes 65895627 # The number of ROB writes
+system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23987668 # Number of Instructions Simulated
+system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads
+system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads
system.cpu0.fp_regfile_writes 840 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 113743711 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 12811786 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 112044501 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 501943 # number of misc regfile writes
-system.cpu0.toL2Bus.trans_dist::ReadReq 900890 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 693810 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 10816 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 10816 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 228377 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 268020 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 56323 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24618 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 62769 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 133666 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 124628 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651345 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1224806 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16460 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46873 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 1939484 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20679616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38657675 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 81552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 59446187 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 639427 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 1524092 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.371625 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.483239 # Request fanout histogram
+system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes
+system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 640729 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 957702 62.84% 62.84% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 566390 37.16% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 1524092 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 762289909 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 71149999 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 488209636 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 613845688 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 9628741 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 26509702 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 321808 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.716294 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 10911549 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 322320 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 33.853155 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6537059000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.716294 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999446 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999446 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 322116 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745799 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745799 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.944101 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.944101 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses
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system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190386 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190386 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115622 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for overall accesses
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+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses
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+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18865.953776 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20035.364652 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41507.282127 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17989.309343 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17989.309343 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14585.513234 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14585.513234 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 259000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 259000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26586.979184 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26586.979184 # average ReadExReq mshr miss latency
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.758765 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35905.242643 # average overall mshr miss latency
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+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency
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+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 297776 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 472.735885 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 9026842 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 298288 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 30.262169 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 297335 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.735885 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923312 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.923312 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 20884973 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 20884973 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4735429 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 4735429 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3898152 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3898152 # number of WriteReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 45417 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135242 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 135242 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133435 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 133435 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8633581 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 8633581 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8678998 # number of overall hits
-system.cpu0.dcache.overall_hits::total 8678998 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 322548 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 322548 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 908505 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 908505 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74956 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 74956 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10777 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 10777 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11487 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 11487 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1231053 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1231053 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1306009 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1306009 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3690700649 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 3690700649 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13101093488 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 13101093488 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182297251 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 182297251 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273170236 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 273170236 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 708000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 708000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 16791794137 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 16791794137 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 16791794137 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 16791794137 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 5057977 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 5057977 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4806657 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4806657 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120373 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 120373 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146019 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 146019 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144922 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 144922 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 9864634 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 9864634 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 9985007 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 9985007 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063770 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.063770 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.189010 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.189010 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.622698 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.622698 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073805 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073805 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079263 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079263 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124795 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.124795 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130797 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.130797 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11442.329976 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11442.329976 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14420.496847 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14420.496847 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16915.398627 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16915.398627 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23780.816227 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23780.816227 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits
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+system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13640.187821 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13640.187821 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12857.334166 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12857.334166 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 95 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 1898059 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 100067 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.916667 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 18.967882 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 228377 # number of writebacks
-system.cpu0.dcache.writebacks::total 228377 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162400 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 162400 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 764106 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 764106 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1174 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1174 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.demand_mshr_hits::total 926506 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 926506 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 926506 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 160148 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144399 # number of WriteReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 44137 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9603 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9603 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11487 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 11487 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 304547 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 304547 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 348684 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 348684 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1658754828 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1658754828 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2155336775 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2155336775 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 705733496 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 705733496 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 146716749 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146716749 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 248972764 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 248972764 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 670000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 670000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3814091603 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 3814091603 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 4519825099 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541509738 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541509738 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345509995 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345509995 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15887019733 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031662 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031662 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030041 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030041 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366669 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366669 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065765 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065765 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079263 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079263 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030873 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.030873 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034921 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.034921 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10357.636861 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10357.636861 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14926.258319 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14926.258319 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15989.611800 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15989.611800 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15278.220244 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15278.220244 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21674.306956 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21674.306956 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks
+system.cpu0.dcache.writebacks::total 228050 # number of writebacks
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12523.819322 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12523.819322 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12962.525091 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12962.525091 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9152424 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6787583 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 422463 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 5824908 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 4287107 # Number of BTB hits
+system.cpu1.branchPred.lookups 9149866 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.599566 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 928023 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 19411 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25102485 # DTB read hits
-system.cpu1.dtb.read_misses 30131 # DTB read misses
-system.cpu1.dtb.write_hits 6842228 # DTB write hits
-system.cpu1.dtb.write_misses 6831 # DTB write misses
+system.cpu1.dtb.read_hits 25102636 # DTB read hits
+system.cpu1.dtb.read_misses 30137 # DTB read misses
+system.cpu1.dtb.write_hits 6841685 # DTB write hits
+system.cpu1.dtb.write_misses 6769 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1185 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 216 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 721 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25132616 # DTB read accesses
-system.cpu1.dtb.write_accesses 6849059 # DTB write accesses
+system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25132773 # DTB read accesses
+system.cpu1.dtb.write_accesses 6848454 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31944713 # DTB hits
-system.cpu1.dtb.misses 36962 # DTB misses
-system.cpu1.dtb.accesses 31981675 # DTB accesses
+system.cpu1.dtb.hits 31944321 # DTB hits
+system.cpu1.dtb.misses 36906 # DTB misses
+system.cpu1.dtb.accesses 31981227 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 16807994 # ITB inst hits
-system.cpu1.itb.inst_misses 6151 # ITB inst misses
+system.cpu1.itb.inst_hits 16803682 # ITB inst hits
+system.cpu1.itb.inst_misses 6173 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1324 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 2317 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 16814145 # ITB inst accesses
-system.cpu1.itb.hits 16807994 # DTB hits
-system.cpu1.itb.misses 6151 # DTB misses
-system.cpu1.itb.accesses 16814145 # DTB accesses
-system.cpu1.numCycles 436928341 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses
+system.cpu1.itb.hits 16803682 # DTB hits
+system.cpu1.itb.misses 6173 # DTB misses
+system.cpu1.itb.accesses 16809855 # DTB accesses
+system.cpu1.numCycles 436917069 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 7782698 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 51596763 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9152424 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5215130 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 424941710 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 1120750 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 78139 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 42302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 114025 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 2394073 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 15193 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 16805493 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 110231 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 1848 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 435928515 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.141220 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 0.582447 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 407583971 93.50% 93.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 9418988 2.16% 95.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 4633784 1.06% 96.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 14291772 3.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 435928515 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.020947 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.118090 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 9900364 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 404223223 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 17614980 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3776395 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 413553 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1053442 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 149008 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 53092008 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 1695759 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 413553 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 13042723 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 210396712 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 23472613 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 17904868 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 170698046 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51368721 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 446510 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 60461955 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 44486739 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 161543607 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 5691516 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 54461405 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 239791189 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 64663371 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6318 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 48773612 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 5687793 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 755066 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 650305 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 9515083 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9672416 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 7398818 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 540509 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 901013 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 49760651 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1064041 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 65151517 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 226257 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 4310331 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 9274124 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 164398 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 435928515 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.149455 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.502708 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 391744994 89.86% 89.86% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 28933513 6.64% 96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 10221564 2.34% 98.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 4339119 1.00% 99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 689106 0.16% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 219 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 435928515 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 4423159 17.50% 17.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 17781771 70.36% 87.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 3065221 12.13% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 14259 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 32355462 49.66% 49.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 60215 0.09% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 25491374 39.13% 88.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7228505 11.09% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 65151517 # Type of FU issued
-system.cpu1.iq.rate 0.149113 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 25270842 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.387878 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 591706993 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 55136909 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 48344835 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 21655 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8050 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6779 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 90394215 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 13885 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 164856 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued
+system.cpu1.iq.rate 0.149104 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 923073 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 694 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 9989 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 405691 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16016634 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 154537 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 413553 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 90101438 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 101307050 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 50914326 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9672416 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 7398818 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 775912 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 15376 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 101229610 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 9989 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 133261 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 167875 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 301136 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 64660152 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25297767 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 454579 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 89634 # number of nop insts executed
-system.cpu1.iew.exec_refs 32444465 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6847399 # Number of branches executed
-system.cpu1.iew.exec_stores 7146698 # Number of stores executed
-system.cpu1.iew.exec_rate 0.147988 # Inst execution rate
-system.cpu1.iew.wb_sent 64445126 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 48351614 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 25812211 # num instructions producing a value
-system.cpu1.iew.wb_consumers 39463324 # num instructions consuming a value
+system.cpu1.iew.exec_nop 89541 # number of nop insts executed
+system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6846575 # Number of branches executed
+system.cpu1.iew.exec_stores 7146063 # Number of stores executed
+system.cpu1.iew.exec_rate 0.147981 # Inst execution rate
+system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 25811466 # num instructions producing a value
+system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.110663 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.654081 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 3859606 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 899643 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 275641 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 435147565 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.106509 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 0.626853 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 413414233 95.01% 95.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 12938839 2.97% 97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 3517188 0.81% 98.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1361627 0.31% 99.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1314784 0.30% 99.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 785099 0.18% 99.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 557735 0.13% 99.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 306330 0.07% 99.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 951730 0.22% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 435147565 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38848557 # Number of instructions committed
-system.cpu1.commit.committedOps 46347287 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38843249 # Number of instructions committed
+system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 15742470 # Number of memory references committed
-system.cpu1.commit.loads 8749343 # Number of loads committed
-system.cpu1.commit.membars 195410 # Number of memory barriers committed
-system.cpu1.commit.branches 6420016 # Number of branches committed
+system.cpu1.commit.refs 15740654 # Number of memory references committed
+system.cpu1.commit.loads 8748353 # Number of loads committed
+system.cpu1.commit.membars 195273 # Number of memory barriers committed
+system.cpu1.commit.branches 6419002 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 41063846 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 553629 # Number of function calls committed.
+system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 553431 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 30544997 65.90% 65.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 8749343 18.88% 84.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6993127 15.09% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 46347287 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 951730 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 483333475 # The number of ROB reads
-system.cpu1.rob.rob_writes 101149089 # The number of ROB writes
-system.cpu1.timesIdled 117660 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 999826 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4778389305 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38778918 # Number of Instructions Simulated
-system.cpu1.committedOps 46277648 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 11.267162 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 11.267162 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.088753 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.088753 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 76052012 # number of integer regfile reads
-system.cpu1.int_regfile_writes 30999334 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 5023 # number of floating regfile reads
+system.cpu1.rob.rob_reads 483317632 # The number of ROB reads
+system.cpu1.rob.rob_writes 101136219 # The number of ROB writes
+system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 38773610 # Number of Instructions Simulated
+system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads
+system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 220747200 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 19380007 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 519889697 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 723831 # number of misc regfile writes
-system.cpu1.toL2Bus.trans_dist::ReadReq 2172389 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1977860 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 758382 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 758382 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 290106 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 274324 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 56101 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25225 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 54306 # Transaction distribution
+system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes
+system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 157043 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 149501 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1094031 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4942031 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17483 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65557 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 6119102 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34999952 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51368490 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29544 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 86517802 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 597240 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1872325 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.291637 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.454516 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 595717 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1326285 70.84% 70.84% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 546040 29.16% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1872325 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2993294877 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 46728999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 821422427 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 2122306221 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 10104485 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 36085284 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.icache.tags.replacements 546512 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.931613 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 16242826 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 547024 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 29.693077 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 73724433000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.931613 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974476 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.974476 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 546235 # number of replacements
+system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 34157735 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 34157735 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 16242826 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 16242826 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 16242826 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 16242826 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 16242826 # number of overall hits
-system.cpu1.icache.overall_hits::total 16242826 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 562520 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 562520 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 562520 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 562520 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 562520 # number of overall misses
-system.cpu1.icache.overall_misses::total 562520 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4745618430 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4745618430 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4745618430 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4745618430 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4745618430 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4745618430 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 16805346 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 16805346 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 16805346 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 16805346 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 16805346 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 16805346 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033473 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.033473 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033473 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.033473 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033473 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.033473 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.355027 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.355027 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8436.355027 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8436.355027 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 306365 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 1 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 40679 # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits
+system.cpu1.icache.overall_hits::total 16238797 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses
+system.cpu1.icache.overall_misses::total 562244 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.531281 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets 1 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15477 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 15477 # number of ReadReq MSHR hits
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7985.014503 # Average occupied blocks per requestor
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29160.699614 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29160.699614 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22739.122704 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43894.350508 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency
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+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency
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+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 381157 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 482.358158 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 12336025 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 381566 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 32.329990 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 70967583500 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.ReadReq_hits::cpu1.data 7207091 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 7207091 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 24710 # number of SoftPFReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::total 94182 # number of LoadLockedReq hits
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-system.cpu1.dcache.ReadReq_misses::total 361330 # number of ReadReq misses
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-system.cpu1.dcache.SoftPFReq_misses::total 47195 # number of SoftPFReq misses
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-system.cpu1.dcache.LoadLockedReq_misses::total 14954 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 14399 # number of StoreCondReq misses
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-system.cpu1.dcache.demand_misses::total 1327889 # number of demand (read+write) misses
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-system.cpu1.dcache.overall_misses::total 1375084 # number of overall misses
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-system.cpu1.dcache.ReadReq_miss_latency::total 4284258220 # number of ReadReq miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 19922244666 # number of overall miss cycles
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-system.cpu1.dcache.overall_accesses::total 13466549 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.047742 # miss rate for ReadReq accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 11856.912573 # average ReadReq miss latency
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-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16179.029367 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17047.997058 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17047.997058 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23033.636225 # average StoreCondReq miss latency
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+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
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+system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses
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+system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits
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+system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles
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+system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15002.944272 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15002.944272 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14488.020125 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14488.020125 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 5063 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 2164841 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 227 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 93890 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.303965 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 23.057205 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 290106 # number of writebacks
-system.cpu1.dcache.writebacks::total 290106 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147611 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 147611 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 796581 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 796581 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1422 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 944192 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 944192 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 944192 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 944192 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213719 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 213719 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 169978 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 169978 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30150 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 30150 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13532 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13532 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14399 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 14399 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 383697 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 383697 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 413847 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 413847 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2234589083 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2234589083 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2566083982 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2566083982 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 631981244 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 631981244 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208947501 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208947501 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 301752672 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 301752672 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1311000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1311000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4800673065 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4800673065 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5432654309 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5432654309 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183654680990 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183654680990 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50890148887 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50890148887 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234544829877 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234544829877 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028238 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028238 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029175 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029175 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.419303 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.419303 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123992 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123992 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133441 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133441 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028646 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030731 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030731 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10455.734319 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10455.734319 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15096.565332 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15096.565332 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20961.235290 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20961.235290 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15440.991797 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15440.991797 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20956.501979 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20956.501979 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks
+system.cpu1.dcache.writebacks::total 291033 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12511.625228 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12511.625228 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13127.204762 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13127.204762 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1735774629169 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1735774629169 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 42920 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 50586 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff