update experiment4 to use pads.useCoreSize

diff --git a/experiments4/coriolis2/ioring.py b/experiments4/coriolis2/ioring.py
index b3628116e4f695087bda2ed8186c2fd7a55a46c0..5b43d14fee0ec5fd3a1234a74c030637f0691295 100644 (file)
--- a/experiments4/coriolis2/ioring.py
+++ b/experiments4/coriolis2/ioring.py
@@ -31,8 +31,9 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
             [ 'p_b1', 'p_vddeck_0', 'p_b0'        , 'p_vsseck_0', 'rst' ],
        'pads.west'       :
             [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1'       , 'p_f0' ],
-       'core.size'       : ( l( 800), l( 800) ),
-       'chip.size'       : ( l(2000), l(2000) ),
+       'core.size'       : ( l( 1200), l( 1200) ),
+       'chip.size'       : ( l(3200), l(3200) ),
+       'pads.useCoreSize'  : True,
        'chip.clockTree'  : True,
        }