Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

diff --combined src/soc/experiment/pimem.py
index b84b3040da3be6b250e52c554e94c022831ece3b,7e92e9674ab07f477f1af71b3b82128c8b3a5cfc..b9c05df5567378f736a9872511f751e39d2a6017
--- 1/src/soc/experiment/pimem.py
--- 2/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@@ -32,6 -32,8 +32,6 @@@ from soc.experiment.mem_types import LD
  from soc.experiment.testmem import TestMemory
  #from soc.scoreboard.addr_split import LDSTSplitter
  from nmutil.util import Display
 -from collections import namedtuple
 -MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"]) # used in unit tests
  
  import unittest
  
@@@ -226,6 -228,7 +226,7 @@@ class PortInterfaceBase(Elaboratable)
          pr = ~pi.priv_mode
          dr = pi.virt_mode   # not yet used
          sf = pi.mode_32bit   # not yet used
+         msr = MSRSpec(pr=pr, dr=dr, sf=sf)
  
          # detect busy "edge"
          busy_delay = Signal()