Merge remote-tracking branch 'origin/master' into xaig_dff

diff --cc techlibs/xilinx/cells_sim.v
Simple merge

diff --cc techlibs/xilinx/synth_xilinx.cc
index a5358cf6400e07a10c26df0fe7ca6b12733a6998,3d4a65c5dfe1aa2c3f08f574c27d3acbaa474c2f..b5c203d1f209bf008661f52737bc17815586b4ca
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -283,30 -291,12 +291,13 @@@ struct SynthXilinxPass : public ScriptP
                        ff_map_file = "+/xilinx/xc7_ff_map.v";
  
                if (check_label("begin")) {
 +                      std::string read_args;
                        if (vpr)
 -                              run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 -                      else
 -                              run("read_verilog -lib +/xilinx/cells_sim.v");
 +                              read_args += " -D_EXPLICIT_CARRY";
 +                      read_args += " -lib +/xilinx/cells_sim.v";
 +                      run("read_verilog" + read_args);
  
-                       if (help_mode)
-                               run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
-                       else if (family == "xc6s")
-                               run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
-                       else if (family == "xc6v")
-                               run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
-                       else if (family == "xc7")
-                               run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
-                       else if (family == "xcu" || family == "xcup")
-                               run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
- 
-                       if (help_mode) {
-                               run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
-                       } else if (family == "xc6s") {
-                               run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
-                       } else if (family == "xc6v" || family == "xc7") {
-                               run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
-                       }
+                       run("read_verilog -lib +/xilinx/cells_xtra.v");
  
                        run(stringf("hierarchy -check %s", top_opt.c_str()));
                }