Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

diff --combined src/main/scala/devices/gpio/GPIOPeriphery.scala
index cd658f17dd30625004f39fbfd49113d0e562c483,109ffb82991df1dcea50c16d013624b5f81373fb..d3b9cf5f17a49ba0c67aa54cdf27832f2267d158
--- 1/src/main/scala/devices/gpio/GPIOPeriphery.scala
--- 2/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@@ -3,19 -3,18 +3,18 @@@ package sifive.blocks.devices.gpi
  
  import Chisel._
  import freechips.rocketchip.config.Field
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.TLFragmenter
  import freechips.rocketchip.util.HeterogeneousBag
  
  case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
  
- trait HasPeripheryGPIO extends HasSystemNetworks {
+ trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
    val gpioParams = p(PeripheryGPIOKey)
-   val gpios = gpioParams map {params =>
-     val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-     gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := gpio.intnode
 -  val gpio = gpioParams map { params =>
++  val gpios = gpioParams map { params =>
+     val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+     gpio.node := pbus.toVariableWidthSlaves
+     ibus.fromSync := gpio.intnode
      gpio
    }
  }
@@@ -28,7 -27,7 +27,7 @@@ trait HasPeripheryGPIOModuleImp extend
    val outer: HasPeripheryGPIO
    val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
  
 -  (gpio zip outer.gpio) foreach { case (io, device) =>
 +  (gpio zip outer.gpios) foreach { case (io, device) =>
      io <> device.module.io.port
    }
  }

diff --combined src/main/scala/devices/i2c/I2CPeriphery.scala
index 6444a397a9bbd1047383aa17203fb40e0fffbda0,1cc927f46adf7b5243c76d31c23c0f703e4ac295..f4394073eceb3784414b66a756dea9c184f2f7a0
--- 1/src/main/scala/devices/i2c/I2CPeriphery.scala
--- 2/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@@ -3,31 -3,36 +3,30 @@@ package sifive.blocks.devices.i2
  
  import Chisel._
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.{HasSystemNetworks}
- import freechips.rocketchip.tilelink.TLFragmenter
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
  
  case object PeripheryI2CKey extends Field[Seq[I2CParams]]
  
- trait HasPeripheryI2C extends HasSystemNetworks {
+ trait HasPeripheryI2C extends HasPeripheryBus {
    val i2cParams = p(PeripheryI2CKey)
    val i2c = i2cParams map { params =>
-     val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
-     i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := i2c.intnode
+     val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
+     i2c.node := pbus.toVariableWidthSlaves
+     ibus.fromSync := i2c.intnode
      i2c
    }
  }
  
  trait HasPeripheryI2CBundle {
 -  val i2cs: Vec[I2CPort]
 -
 -  def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
 -    val pins = Module(new I2CGPIOPort(syncStages))
 -    pins.io.i2c <> i
 -    pins.io.pins
 -  }
 +  val i2c: Vec[I2CPort]
  }
  
  trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
    val outer: HasPeripheryI2C
 -  val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
 +  val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
  
 -  (i2cs zip outer.i2c).foreach { case (io, device) =>
 +  (i2c zip outer.i2c).foreach { case (io, device) =>
      io <> device.module.io.port
    }
  }

diff --combined src/main/scala/devices/pwm/PWMPeriphery.scala
index f83cbafdfe9780ea83e865a8d94b65c4de9a8c4a,5ff9ccfe8f5b23dc17c79886c6afd2722a493070..ff5b6bbe1a20aff22e859e3a27c5b65f1ad0a430
--- 1/src/main/scala/devices/pwm/PWMPeriphery.scala
--- 2/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@@ -3,53 -3,56 +3,52 @@@ package sifive.blocks.devices.pw
  
  import Chisel._
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.TLFragmenter
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
  import freechips.rocketchip.util.HeterogeneousBag
- import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 -import sifive.blocks.devices.gpio._
++import sifive.blocks.devices.pinctrl.{Pin}
  
  class PWMPortIO(val c: PWMParams) extends Bundle {
    val port = Vec(c.ncmp, Bool()).asOutput
    override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  }
  
 -class PWMPinsIO(val c: PWMParams) extends Bundle {
 -  val pwm = Vec(c.ncmp, new GPIOPin)
 -}
 +class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
  
 -class PWMGPIOPort(val c: PWMParams) extends Module {
 -  val io = new Bundle {
 -    val pwm = new PWMPortIO(c).flip()
 -    val pins = new PWMPinsIO(c)
 -  }
 +  val pwm: Vec[T] = Vec(c.ncmp, pingen())
 +
 +  override def cloneType: this.type =
 +    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  
 -  GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
 +  def fromPWMPort(port: PWMPortIO) {
 +    (pwm zip port.port)  foreach {case (pin, port) =>
 +      pin.outputPin(port)
 +    }
 +  }
  }
  
  case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  
- trait HasPeripheryPWM extends HasSystemNetworks {
+ trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
    val pwmParams = p(PeripheryPWMKey)
    val pwms = pwmParams map { params =>
-     val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-     pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := pwm.intnode
+     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+     pwm.node := pbus.toVariableWidthSlaves
+     ibus.fromSync := pwm.intnode
      pwm
    }
  }
  
  trait HasPeripheryPWMBundle {
 -  val pwms: HeterogeneousBag[PWMPortIO]
 +  val pwm: HeterogeneousBag[PWMPortIO]
  
 -  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
 -    val pins = Module(new PWMGPIOPort(p.c))
 -    pins.io.pwm <> p
 -    pins.io.pins
 -  }
  }
  
  trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
    val outer: HasPeripheryPWM
 -  val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
 +  val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  
 -  (pwms zip outer.pwms) foreach { case (io, device) =>
 +  (pwm zip outer.pwms) foreach { case (io, device) =>
      io.port := device.module.io.gpio
    }
  }

diff --combined src/main/scala/devices/spi/SPIPeriphery.scala
index f2b3b4198fc1e7ce96b02d612581c38f5d5dca2e,37151bd06cda84a0e8a5f6b9178824418c024e64..80978946103eec972449e71d82227beceb2b3e86
--- 1/src/main/scala/devices/spi/SPIPeriphery.scala
--- 2/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@@ -3,46 -3,51 +3,46 @@@ package sifive.blocks.devices.sp
  
  import Chisel._
  import freechips.rocketchip.config.Field
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+ import freechips.rocketchip.tilelink.{TLFragmenter}
  import freechips.rocketchip.util.HeterogeneousBag
  
  case object PeripherySPIKey extends Field[Seq[SPIParams]]
  
- trait HasPeripherySPI extends HasSystemNetworks {
+ trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
    val spiParams = p(PeripherySPIKey)  
    val spis = spiParams map { params =>
-     val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
-     spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := spi.intnode
+     val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+     spi.rnode := pbus.toVariableWidthSlaves
+     ibus.fromSync := spi.intnode
      spi
    }
  }
  
  trait HasPeripherySPIBundle {
 -  val spis: HeterogeneousBag[SPIPortIO]
 +  val spi: HeterogeneousBag[SPIPortIO]
  
 -  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = spis.map { s =>
 -    val pins = Module(new SPIGPIOPort(s.c, syncStages))
 -    pins.io.spi <> s
 -    pins.io.pins
 -  }
  }
  
  trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
    val outer: HasPeripherySPI
 -  val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
 +  val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
  
 -  (spis zip outer.spis).foreach { case (io, device) =>
 +  (spi zip outer.spis).foreach { case (io, device) =>
      io <> device.module.io.port
    }
  }
  
  case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
  
- trait HasPeripherySPIFlash extends HasSystemNetworks {
+ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
    val spiFlashParams = p(PeripherySPIFlashKey)  
 -  val qspi = spiFlashParams map { params =>
 +  val qspis = spiFlashParams map { params =>
-     val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
-     qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-     intBus.intnode := qspi.intnode
+     val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+     qspi.rnode := pbus.toVariableWidthSlaves
+     qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+     ibus.fromSync := qspi.intnode
      qspi
    }
  }
@@@ -50,14 -55,21 +50,13 @@@
  trait HasPeripherySPIFlashBundle {
    val qspi: HeterogeneousBag[SPIPortIO]
  
 -  // It is important for SPIFlash that the syncStages is agreed upon, because
 -  // internally it needs to realign the input data to the output SCK.
 -  // Therefore, we rely on the syncStages parameter.
 -  def SPIFlashtoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = qspi.map { s =>
 -    val pins = Module(new SPIGPIOPort(s.c, syncStages))
 -    pins.io.spi <> s
 -    pins.io.pins
 -  }
  }
  
  trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
    val outer: HasPeripherySPIFlash
    val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
  
 -  (qspi zip outer.qspi) foreach { case (io, device) => 
 +  (qspi zip outer.qspis) foreach { case (io, device) => 
      io <> device.module.io.port
    }
  }
- 

diff --combined src/main/scala/devices/uart/UARTPeriphery.scala
index 105592d2042e7a6f19d265d37c45f3e5ff771c46,c925a38a0e47307e281788a7e30abb195ab8eb27..d42850f88eca4388a571ac86e47743c69406beef
--- 1/src/main/scala/devices/uart/UARTPeriphery.scala
--- 2/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@@ -2,57 -2,59 +2,56 @@@
  package sifive.blocks.devices.uart
  
  import Chisel._
 +import chisel3.experimental.{withClockAndReset}
  import freechips.rocketchip.config.Field
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.TLFragmenter
- import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 -import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
++import sifive.blocks.devices.pinctrl.{Pin}
  import sifive.blocks.util.ShiftRegisterInit
  
  case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  
- trait HasPeripheryUART extends HasSystemNetworks {
+ trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
    val uartParams = p(PeripheryUARTKey)  
    val uarts = uartParams map { params =>
-     val uart = LazyModule(new TLUART(peripheryBusBytes, params))
-     uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := uart.intnode
+     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+     uart.node := pbus.toVariableWidthSlaves
+     ibus.fromSync := uart.intnode
      uart
    }
  }
  
  trait HasPeripheryUARTBundle {
 -  val uarts: Vec[UARTPortIO]
 +  val uart: Vec[UARTPortIO]
  
    def tieoffUARTs(dummy: Int = 1) {
 -    uarts.foreach { _.rxd := UInt(1) }
 +    uart.foreach { _.rxd := UInt(1) }
    }
  
 -  def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
 -    val pins = Module(new UARTGPIOPort(syncStages))
 -    pins.io.uart <> u
 -    pins.io.pins
 -  }
  }
  
  trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
    val outer: HasPeripheryUART
 -  val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
 +  val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  
 -  (uarts zip outer.uarts).foreach { case (io, device) =>
 +  (uart zip outer.uarts).foreach { case (io, device) =>
      io <> device.module.io.port
    }
  }
  
 -class UARTPinsIO extends Bundle {
 -  val rxd = new GPIOPin
 -  val txd = new GPIOPin
 -}
 +class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
 +  val rxd = pingen()
 +  val txd = pingen()
  
 -class UARTGPIOPort(syncStages: Int = 0) extends Module {
 -  val io = new Bundle{
 -    val uart = new UARTPortIO().flip()
 -    val pins = new UARTPinsIO
 -  }
 +  override def cloneType: this.type =
 +    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  
 -  GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
 -  val rxd = GPIOInputPinCtrl(io.pins.rxd)
 -  io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
 +  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
 +    withClockAndReset(clock, reset) {
 +      txd.outputPin(uart.txd)
 +      val rxd_t = rxd.inputPin()
 +      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
 +    }
 +  }
  }
 +