[libre-riscv-dev] [Bug 270] investigate nmigen clock gating
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Sat, 28 Mar 2020 16:20:53 +0000 (16:20 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 28 Mar 2020 16:20:54 +0000 (16:20 +0000)
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+Date: Sat, 28 Mar 2020 16:20:53 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: staf@fibraservi.eu
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-270-13-XWpq1sp4fd@http.bugs.libre-riscv.org/>
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+References: <bug-270-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 270] investigate nmigen clock gating
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