link page on pipeline operands

diff --git a/3d_gpu/architecture/pipeline_operands.mdwn b/3d_gpu/architecture/pipeline_operands.mdwn
deleted file mode 100644 (file)
index 568b7dc..0000000
--- a/3d_gpu/architecture/pipeline_operands.mdwn
+++ /dev/null
@@ -1,118 +0,0 @@
-# Condition Register Pipeline
-
-Input:
-'''
-    64 - Port 1   32 - Port 2
-    -----------   -----------
-    RA            CR
-'''
-
-Output:
-'''
-    64 - Port 1   32 - Port 2
-    -----------   -----------
-    RA            CR
-'''
-
-# Branch Register Pipeline
-
-Input:
-'''
-    insn       PC   32-CR  64-SPR1  64-SPR2    64-SPR3
-    ----       --   --     ----     ----       ----
-    op_b       CIA  xx     xx       xx         xx
-    op_ba      CIA  xx     xx       xx         xx
-    op_bl      CIA  xx     xx       xx         xx
-    op_bla     CIA  xx     xx       xx         xx
-    op_bc      CIA  CR     xx       CTR        xx
-    op_bca     CIA  CR     xx       CTR        xx
-    op_bcl     CIA  CR     xx       CTR        xx
-    op_bcla    CIA  CR     xx       CTR        xx
-    op_bclr    CIA  CR     LR       CTR        xx
-    op_bclrl   CIA  CR     LR       CTR        xx
-    op_bcctr   CIA  CR     xx       CTR        xx
-    op_bcctrl  CIA  CR     xx       CTR        xx
-    op_bctar   CIA  CR     TAR      CTR        xx
-    op_bctarl  CIA  CR     TAR      CTR        xx
-
-    op_sc      CIA  xx     xx       xx         MSR
-    op_scv     CIA  xx     LR       SRR1       MSR
-    op_rfscv   CIA  xx     LR       CTR        MSR
-    op_rfid    CIA  xx     SRR0     SRR1       MSR
-    op_hrfid   CIA  xx     HSRR0    HSRR1      MSR
-'''
-
-Output:
-'''
-    insn       PC   LR   64-SPR2
-    ----       --   --   ----
-    op_b       NIA  xx   xx
-    op_ba      NIA  xx   xx
-    op_bl      NIA  xx   xx
-    op_bla     NIA  xx   xx
-    op_bc      NIA  xx   CTR
-    op_bca     NIA  xx   CTR
-    op_bcl     NIA  xx   CTR
-    op_bcla    NIA  xx   CTR
-    op_bclr    NIA  LR   CTR
-    op_bclrl   NIA  LR   CTR
-    op_bcctr   NIA  xx   CTR
-    op_bcctrl  NIA  xx   CTR
-    op_bctar   NIA  xx   CTR
-    op_bctarl  NIA  xx   CTR
-
-    op_sc      NIA  xx   xx
-    op_scv     NIA  LR   xx
-    op_rfscv   NIA  LR   CTR
-    op_rfid    NIA  xx   xx
-    op_hrfid   NIA  xx   xx
-'''
-
-# Logical Register Pipeline
-
-Input:
-'''
-    64 - Port 1   64 - Port 2  1 - SO  1 - Carry
-    -----------   -----------  ------  ---------
-    RA/RS         RB           so      carry_in
-'''
-
-Output:
-'''
-    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
-    -----------   -----------  ------  ----------------- -----------
-    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
-'''
-
-# Arithmetic Register Pipeline
-
-Input:
-'''
-    64 - Port 1   64 - Port 2  1 - SO  1 - Carry
-    -----------   -----------  ------  ---------
-    RA            RB/immed     so      carry_in
-'''
-
-Output:
-'''
-    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
-    -----------   -----------  ------  ----------------- -----------
-    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
-'''
-
-# Shift Register Pipeline
-
-Input:
-'''
-    64 - Port 1   64 - Port 2  64 - Port 3  1 - SO  1 - Carry
-    -----------   -----------  -----------  ------  ---------
-    RA            RB/immed     RS           so      carry_in
-'''
-
-Output:
-'''
-    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
-    -----------   -----------  ------  ----------------- -----------
-    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
-'''
-

diff --git a/openpower.mdwn b/openpower.mdwn
index 7cbbbceb7b0f457a72a9037093b43e57ac0e3f1a..5e534f619e4b55f7659b12415aa080d6479dc827 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -9,6 +9,7 @@ Links
 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
 * [[openpower/gem5]]
 * [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
 * [[3d_gpu/architecture/decoder]]
 * <https://forums.raptorcs.com/>
 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>

diff --git a/openpower/pipeline_operands.mdwn b/openpower/pipeline_operands.mdwn
new file mode 100644 (file)
index 0000000..568b7dc
--- /dev/null
+++ b/openpower/pipeline_operands.mdwn
@@ -0,0 +1,118 @@
+# Condition Register Pipeline
+
+Input:
+'''
+    64 - Port 1   32 - Port 2
+    -----------   -----------
+    RA            CR
+'''
+
+Output:
+'''
+    64 - Port 1   32 - Port 2
+    -----------   -----------
+    RA            CR
+'''
+
+# Branch Register Pipeline
+
+Input:
+'''
+    insn       PC   32-CR  64-SPR1  64-SPR2    64-SPR3
+    ----       --   --     ----     ----       ----
+    op_b       CIA  xx     xx       xx         xx
+    op_ba      CIA  xx     xx       xx         xx
+    op_bl      CIA  xx     xx       xx         xx
+    op_bla     CIA  xx     xx       xx         xx
+    op_bc      CIA  CR     xx       CTR        xx
+    op_bca     CIA  CR     xx       CTR        xx
+    op_bcl     CIA  CR     xx       CTR        xx
+    op_bcla    CIA  CR     xx       CTR        xx
+    op_bclr    CIA  CR     LR       CTR        xx
+    op_bclrl   CIA  CR     LR       CTR        xx
+    op_bcctr   CIA  CR     xx       CTR        xx
+    op_bcctrl  CIA  CR     xx       CTR        xx
+    op_bctar   CIA  CR     TAR      CTR        xx
+    op_bctarl  CIA  CR     TAR      CTR        xx
+
+    op_sc      CIA  xx     xx       xx         MSR
+    op_scv     CIA  xx     LR       SRR1       MSR
+    op_rfscv   CIA  xx     LR       CTR        MSR
+    op_rfid    CIA  xx     SRR0     SRR1       MSR
+    op_hrfid   CIA  xx     HSRR0    HSRR1      MSR
+'''
+
+Output:
+'''
+    insn       PC   LR   64-SPR2
+    ----       --   --   ----
+    op_b       NIA  xx   xx
+    op_ba      NIA  xx   xx
+    op_bl      NIA  xx   xx
+    op_bla     NIA  xx   xx
+    op_bc      NIA  xx   CTR
+    op_bca     NIA  xx   CTR
+    op_bcl     NIA  xx   CTR
+    op_bcla    NIA  xx   CTR
+    op_bclr    NIA  LR   CTR
+    op_bclrl   NIA  LR   CTR
+    op_bcctr   NIA  xx   CTR
+    op_bcctrl  NIA  xx   CTR
+    op_bctar   NIA  xx   CTR
+    op_bctarl  NIA  xx   CTR
+
+    op_sc      NIA  xx   xx
+    op_scv     NIA  LR   xx
+    op_rfscv   NIA  LR   CTR
+    op_rfid    NIA  xx   xx
+    op_hrfid   NIA  xx   xx
+'''
+
+# Logical Register Pipeline
+
+Input:
+'''
+    64 - Port 1   64 - Port 2  1 - SO  1 - Carry
+    -----------   -----------  ------  ---------
+    RA/RS         RB           so      carry_in
+'''
+
+Output:
+'''
+    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
+    -----------   -----------  ------  ----------------- -----------
+    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
+'''
+
+# Arithmetic Register Pipeline
+
+Input:
+'''
+    64 - Port 1   64 - Port 2  1 - SO  1 - Carry
+    -----------   -----------  ------  ---------
+    RA            RB/immed     so      carry_in
+'''
+
+Output:
+'''
+    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
+    -----------   -----------  ------  ----------------- -----------
+    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
+'''
+
+# Shift Register Pipeline
+
+Input:
+'''
+    64 - Port 1   64 - Port 2  64 - Port 3  1 - SO  1 - Carry
+    -----------   -----------  -----------  ------  ---------
+    RA            RB/immed     RS           so      carry_in
+'''
+
+Output:
+'''
+    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
+    -----------   -----------  ------  ----------------- -----------
+    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
+'''
+