Add $lut support to Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 44e4e5f9783ba3c56ed331788878a9b0e59fb608..d3262ec47c23af420925ae0c713882b125fba1e3 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
+       if (cell->type == "$lut")
+       {
+               f << stringf("%s" "assign ", indent.c_str());
+               dump_sigspec(f, cell->getPort("\\Y"));
+               f << stringf(" = ");
+               dump_const(f, cell->parameters.at("\\LUT"));
+               f << stringf(" >> ");
+               dump_attributes(f, "", cell->attributes, ' ');
+               dump_sigspec(f, cell->getPort("\\A"));
+               f << stringf(";\n");
+               return true;
+       }
+
        if (cell->type == "$dffsr")
        {
                SigSpec sig_clk = cell->getPort("\\CLK");