add f32/f64 fclass
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 28 Jul 2019 10:21:12 +0000 (11:21 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 28 Jul 2019 10:21:12 +0000 (11:21 +0100)
src/ieee754/fclass/pipeline.py
src/ieee754/fclass/test/test_fclass_pipe.py

index 6a3ddb381c145a7f9858afcca9b21ab7a236f4f7..6550e684feca2e8daaba8bc43e32e8f89e871d06 100644 (file)
@@ -52,7 +52,7 @@ class FPClassMod(Elaboratable):
     def setup(self, m, i):
         """ links module to inputs and outputs
         """
-        m.submodules.upconvert = self
+        m.submodules.fclass = self
         m.d.comb += self.i.eq(i)
 
     def process(self, i):
@@ -116,7 +116,7 @@ class FPClassBasePipe(ControlBase):
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.down = self.pipe1
+        m.submodules.fclass = self.pipe1
         m.d.comb += self._eqs
         return m
 
index 8c4726b82378756ef5f488c0e7759a75d9a8690c..9ebfcb87c335cde14ea0b2fa10a14c51eb0d55bd 100644 (file)
@@ -44,12 +44,34 @@ def fclass_16(x):
     return fclass(16, x)
 
 
+def fclass_32(x):
+    return fclass(32, x)
+
+
+def fclass_64(x):
+    return fclass(64, x)
+
+
 def test_class_pipe_f16():
     dut = FPClassMuxInOut(16, 16, 4, op_wid=1)
-    runfp(dut, 16, "test_fcvt_class_pipe_f16", Float16, fclass_16,
+    runfp(dut, 16, "test_fclass_pipe_f16", Float16, fclass_16,
+                True, n_vals=100)
+
+
+def test_class_pipe_f32():
+    dut = FPClassMuxInOut(32, 32, 4, op_wid=1)
+    runfp(dut, 32, "test_fclass_pipe_f32", Float32, fclass_32,
+                True, n_vals=100)
+
+
+def test_class_pipe_f64():
+    dut = FPClassMuxInOut(64, 64, 4, op_wid=1)
+    runfp(dut, 64, "test_fclass_pipe_f64", Float64, fclass_64,
                 True, n_vals=100)
 
 
 if __name__ == '__main__':
     for i in range(200):
         test_class_pipe_f16()
+        test_class_pipe_f32()
+        test_class_pipe_f64()