Add a simple example for Spartan 6

diff --git a/examples/mimas2/README b/examples/mimas2/README
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+++ b/examples/mimas2/README
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+A simple example design, based on the Numato Labs Mimas V2 board
+================================================================
+
+This example uses Yosys for synthesis and Xilinx ISE
+for place&route and bit-stream creation.
+
+To synthesize:
+  bash run.sh

diff --git a/examples/mimas2/example.ucf b/examples/mimas2/example.ucf
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+++ b/examples/mimas2/example.ucf
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+CONFIG VCCAUX = "3.3" ;
+
+
+NET "CLK"                   LOC = D9      | IOSTANDARD = LVCMOS33 | PERIOD = 12MHz ;
+
+NET "LED[7]"                     LOC = P15     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[6]"                     LOC = P16     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[5]"                     LOC = N15     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[4]"                     LOC = N16     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[3]"                     LOC = U17     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[2]"                     LOC = U18     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[1]"                     LOC = T17     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[0]"                     LOC = T18     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v
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+++ b/examples/mimas2/example.v
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+module example(
+       input wire CLK,
+       output wire [7:0] LED
+);
+
+reg [27:0] ctr;
+initial ctr = 0;
+
+always @(posedge CLK)
+       ctr <= ctr + 1;
+
+assign LED = ctr[27:20];
+
+endmodule

diff --git a/examples/mimas2/run.sh b/examples/mimas2/run.sh
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+++ b/examples/mimas2/run.sh
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+#!/bin/sh
+set -e
+yosys run_yosys.ys
+edif2ngd example.edif
+ngdbuild example -uc example.ucf -p xc6slx9csg324-3
+map -w example
+par -w example.ncd example_par.ncd
+bitgen -w example_par.ncd -g StartupClk:JTAGClk

diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
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+++ b/examples/mimas2/run_yosys.ys
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+read_verilog example.v
+synth_xilinx -top example -family xc6s
+iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+write_edif -pvector bra example.edif