nir: gather all IO info from IO intrinsics
authorMarek Olšák <marek.olsak@amd.com>
Fri, 14 Aug 2020 23:31:46 +0000 (19:31 -0400)
committerMarge Bot <eric+marge@anholt.net>
Mon, 24 Aug 2020 19:07:18 +0000 (19:07 +0000)
nir_io_add_const_offset_to_base will shrink num_slots, so it's better to
call it before nir_shader_gather_info.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>

src/compiler/nir/nir_gather_info.c

index 5f59dd21dd0c833b46ae760cf932616fe869fe18..03f0d15f73eac52be8b6e7bfee6dbc295ea67516 100644 (file)
@@ -297,6 +297,14 @@ static void
 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
                       void *dead_ctx)
 {
+   unsigned slot_mask = 0;
+
+   if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
+      nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
+
+      slot_mask = BITFIELD64_RANGE(semantics.location, semantics.num_slots);
+   }
+
    switch (instr->intrinsic) {
    case nir_intrinsic_demote:
    case nir_intrinsic_demote_if:
@@ -345,6 +353,41 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
       break;
    }
 
+   case nir_intrinsic_load_input:
+      if (shader->info.stage == MESA_SHADER_TESS_EVAL)
+         shader->info.patch_inputs_read |= slot_mask;
+      else
+         shader->info.inputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_per_vertex_input:
+   case nir_intrinsic_load_input_vertex:
+   case nir_intrinsic_load_interpolated_input:
+      shader->info.inputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_output:
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
+         shader->info.patch_outputs_read |= slot_mask;
+      else
+         shader->info.outputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_per_vertex_output:
+      shader->info.outputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_store_output:
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
+         shader->info.patch_outputs_written |= slot_mask;
+      else
+         shader->info.outputs_written |= slot_mask;
+      break;
+
+   case nir_intrinsic_store_per_vertex_output:
+      shader->info.outputs_written |= slot_mask;
+      break;
+
    case nir_intrinsic_load_draw_id:
    case nir_intrinsic_load_frag_coord:
    case nir_intrinsic_load_point_coord: