Support PRIM_BUFIF1 primitive

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 74638dc8d700d5c8d75e8f94aab103c9a51c6642..fcacbd086df5d1c1acd085a7f146627f13c3c03d 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -371,7 +371,7 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
                return true;
        }
 
-       if (inst->Type() == PRIM_TRI) {
+       if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
                module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
                return true;
        }
@@ -497,7 +497,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
                return true;
        }
 
-       if (inst->Type() == PRIM_TRI) {
+       if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
                cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
                import_attributes(cell->attributes, inst);
                return true;