rename to memory from add

diff --git a/experiments12/Makefile b/experiments12/Makefile
index 2343504c448fb3c2d236899f6f5f6aed15f00a9f..acd76db2e60ca5af0adfff2cafa561bf12c441c8 100755 (executable)
--- a/experiments12/Makefile
+++ b/experiments12/Makefile
@@ -6,7 +6,7 @@
 
 #           YOSYS_FLATTEN = Yes
                      CHIP = chip
-                     CORE = add
+                     CORE = memory
                    MARGIN = 2
                   BOOMOPT =  # -A
                   BOOGOPT =
@@ -18,14 +18,14 @@
 #                 RM_CHIP = Yes
 
                  NETLISTS = $(shell cat nets.txt)
-#                PATTERNS = add_r
+#                PATTERNS = memory_r
 
 
  include ./mk/design-flow.mk
 
 
-blif:      add.blif
-vst:       add.vst
+blif:      memory.blif
+vst:       memory.vst
 
 lvx:       lvx-chip_cts_r
 druc:      druc-chip_cts_r
@@ -40,4 +40,4 @@ cif:             chip_cts_r.cif
 
 
 view:      cgt-chip_cts_r
-sim:       asimut-add_cts_r
+sim:       asimut-memory_cts_r

diff --git a/experiments12/add.py b/experiments12/add.py
deleted file mode 100644 (file)
index 68aecc1..0000000
--- a/experiments12/add.py
+++ /dev/null
@@ -1,24 +0,0 @@
-from nmigen import *
-from nmigen.cli import rtlil
-
-
-class ADD(Elaboratable):
-    def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.f   = Signal(width)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.sync += self.f.eq(self.a + self.b)
-        return m
-
-
-def create_ilang(dut, ports, test_name):
-    vl = rtlil.convert(dut, name=test_name, ports=ports)
-    with open("%s.il" % test_name, "w") as f:
-        f.write(vl)
-
-if __name__ == "__main__":
-    alu = ADD(width=4)
-    create_ilang(alu, [alu.a, alu.b, alu.f], "add")

diff --git a/experiments12/memory.py b/experiments12/memory.py
new file mode 100644 (file)
index 0000000..84fcdcf
--- /dev/null
+++ b/experiments12/memory.py
@@ -0,0 +1,30 @@
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class ADD(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.f   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.f.eq(self.a + self.b)
+        #a = Signal(9)
+        #q = Signal(64)
+        #d = Signal(64)
+        #we = Signal(8)
+        #sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
+        #m.submodules += sram
+        return m
+
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+if __name__ == "__main__":
+    alu = ADD(width=4)
+    create_ilang(alu, [alu.a, alu.b, alu.f], "memory")

diff --git a/experiments12/nets.txt b/experiments12/nets.txt
index 76d4bb83f8dab3933a481bd2d65fbcc1283ef9b7..2142c3ad3ce3e2246b36e4196e0c6acd540f84a7 100644 (file)
--- a/experiments12/nets.txt
+++ b/experiments12/nets.txt
@@ -1 +1 @@
-add
+memory