Merge pull request #177 from mattvenn/tristate-example
authorJannis Harder <me@jix.one>
Tue, 14 Jun 2022 13:54:09 +0000 (15:54 +0200)
committerGitHub <noreply@github.com>
Tue, 14 Jun 2022 13:54:09 +0000 (15:54 +0200)
Tristate example

docs/examples/tristate/Makefile [new file with mode: 0644]
docs/examples/tristate/README.md [new file with mode: 0644]
docs/examples/tristate/tristate.sby [new file with mode: 0644]
docs/examples/tristate/tristates.v [new file with mode: 0644]

diff --git a/docs/examples/tristate/Makefile b/docs/examples/tristate/Makefile
new file mode 100644 (file)
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--- /dev/null
@@ -0,0 +1,3 @@
+SUBDIR=../docs/examples/tristate
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk
diff --git a/docs/examples/tristate/README.md b/docs/examples/tristate/README.md
new file mode 100644 (file)
index 0000000..155fab2
--- /dev/null
@@ -0,0 +1,13 @@
+# Tristate demo
+
+Run 
+
+    sby -f tristate.sby pass
+
+to run the pass task. This uses the top module that exclusively enables each of the submodules.
+
+Run 
+
+    sby -f tristate.sby fail
+
+to run the fail task. This uses the top module that allows submodule to independently enable its tristate outputs.
diff --git a/docs/examples/tristate/tristate.sby b/docs/examples/tristate/tristate.sby
new file mode 100644 (file)
index 0000000..f85e937
--- /dev/null
@@ -0,0 +1,20 @@
+[tasks]
+pass
+fail
+
+[options]
+fail: expect fail
+mode prove
+depth 5
+
+[engines]
+smtbmc
+
+[script]
+read -sv tristates.v
+pass: prep -top top_pass
+fail: prep -top top_fail
+flatten; tribuf -formal
+
+[files]
+tristates.v
diff --git a/docs/examples/tristate/tristates.v b/docs/examples/tristate/tristates.v
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+`default_nettype none
+module module1 (input wire active, output wire tri_out);
+    assign tri_out = active ? 1'b0 : 1'bz;
+endmodule
+
+module module2 (input wire active, output wire tri_out);
+    assign tri_out = active ? 1'b0 : 1'bz;
+endmodule
+
+module top_pass (input wire clk, input wire active1, output wire out);
+    module1 module1 (.active(active1), .tri_out(out));
+    module2 module2 (.active(!active1), .tri_out(out));
+endmodule
+
+module top_fail (input wire clk, input wire active1, input wire active2, output wire out);
+    module1 module1 (.active(active1), .tri_out(out));
+    module2 module2 (.active(active2), .tri_out(out));
+endmodule