set only div/rem supported

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index ac3e434ab3320165037413ab8165e835ed84b4c8..3a7f35d28af4575bfc1596d8f11e79d7418ffcbf 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -3,7 +3,7 @@ from soc.fu.pipe_data import IntegerData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 from ieee754.div_rem_sqrt_rsqrt.core import (
-    DivPipeCoreConfig, DivPipeCoreInputData,
+    DivPipeCoreConfig, DivPipeCoreInputData, DP,
     DivPipeCoreInterstageData, DivPipeCoreOutputData)
 
 
@@ -24,6 +24,7 @@ class DIVPipeSpec(CommonPipeSpec):
         bit_width=64,
         fract_width=64,
         log2_radix=1,
+        supported=[DP.UDivRem]
     )