add new ls180

diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn
index 4664238a907fb0b83c8297749c892d622c2bd212..7eb146278b219f94df921ad022e9ffc42ad0e63f 100644 (file)
--- a/180nm_Oct2020/ls180.mdwn
+++ b/180nm_Oct2020/ls180.mdwn
@@ -8,8 +8,8 @@ auto-generated by [[pinouts.py]]
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|   0 | N VSS_0     |             |
-|   1 | N VDD_0     |             |
+|   0 | N VSSI_0    |             |
+|   1 | N VDDE_0    |             |
 |   2 | N SDR_DQM0  |             |
 |   3 | N SDR_D0    |             |
 |   4 | N SDR_D1    |             |
@@ -37,14 +37,14 @@ auto-generated by [[pinouts.py]]
 |  26 | N SDR_CASn  |             |
 |  27 | N SDR_WEn   |             |
 |  28 | N SDR_CSn0  |             |
-|  30 | N VSS_1     |             |
-|  31 | N VDD_1     |             |
+|  30 | N VSSE_0    |             |
+|  31 | N VDDI_0    |             |
 
 ## Bank E (32 pins, width 2)
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  32 | E VSS_2     |             |
+|  32 | E VSSE_1    |             |
 |  33 | E SDR_AD10  |             |
 |  34 | E SDR_AD11  |             |
 |  35 | E SDR_AD12  |             |
@@ -57,7 +57,7 @@ auto-generated by [[pinouts.py]]
 |  42 | E SDR_D13   |             |
 |  43 | E SDR_D14   |             |
 |  44 | E SDR_D15   |             |
-|  45 | E VDD_2     |             |
+|  45 | E VDDE_1    |             |
 |  46 | E GPIOE_E8  |             |
 |  47 | E GPIOE_E9  |             |
 |  48 | E GPIOE_E10 |             |
@@ -66,18 +66,18 @@ auto-generated by [[pinouts.py]]
 |  51 | E GPIOE_E13 |             |
 |  52 | E GPIOE_E14 |             |
 |  53 | E GPIOE_E15 |             |
-|  55 | E VSS_3     |             |
+|  55 | E VSSI_1    |             |
 |  56 | E JTAG_TMS  |             |
 |  57 | E JTAG_TDI  |             |
 |  58 | E JTAG_TDO  |             |
 |  59 | E JTAG_TCK  |             |
-|  63 | E VDD_3     |             |
+|  63 | E VDDI_1    |             |
 
 ## Bank S (32 pins, width 2)
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  64 | S VSS_4     |             |
+|  64 | S VSSI_2    |             |
 |  65 | S SYS_CLK   |             |
 |  66 | S SYS_RST   |             |
 |  67 | S SYS_PLLCLK |             |
@@ -85,16 +85,16 @@ auto-generated by [[pinouts.py]]
 |  69 | S SYS_CSEL0 |             |
 |  70 | S SYS_CSEL1 |             |
 |  71 | S SYS_CSEL2 |             |
-|  72 | S VDD_4     |             |
-|  73 | S TWI_SDA   |             |
-|  74 | S TWI_SCL   |             |
+|  72 | S VDDI_2    |             |
+|  73 | S MTWI_SDA  |             |
+|  74 | S MTWI_SCL  |             |
 |  79 | S MSPI0_CK  |             |
 |  80 | S MSPI0_NSS |             |
 |  81 | S MSPI0_MOSI |             |
 |  82 | S MSPI0_MISO |             |
 |  84 | S UART0_TX  |             |
 |  85 | S UART0_RX  |             |
-|  86 | S VSS_5     |             |
+|  86 | S VSSI_3    |             |
 |  87 | S GPIOS_S0  |             |
 |  88 | S GPIOS_S1  |             |
 |  89 | S GPIOS_S2  |             |
@@ -103,13 +103,13 @@ auto-generated by [[pinouts.py]]
 |  92 | S GPIOS_S5  |             |
 |  93 | S GPIOS_S6  |             |
 |  94 | S GPIOS_S7  |             |
-|  95 | S VDD_5     |             |
+|  95 | S VDDI_3    |             |
 
 ## Bank W (32 pins, width 2)
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  96 | W VSS_6     |             |
+|  96 | W VSSI_4    |             |
 |  97 | W PWM_0     |             |
 |  98 | W PWM_1     |             |
 |  99 | W EINT_0    |             |
@@ -119,15 +119,15 @@ auto-generated by [[pinouts.py]]
 | 103 | W MSPI1_NSS |             |
 | 104 | W MSPI1_MOSI |             |
 | 105 | W MSPI1_MISO |             |
-| 106 | W VDD_6     |             |
+| 106 | W VDDE_2    |             |
 | 107 | W SD0_CMD   |             |
 | 108 | W SD0_CLK   |             |
 | 109 | W SD0_D0    |             |
 | 110 | W SD0_D1    |             |
 | 111 | W SD0_D2    |             |
 | 112 | W SD0_D3    |             |
-| 113 | W VSS_7     |             |
-| 127 | W VDD_7     |             |
+| 113 | W VSSE_2    |             |
+| 127 | W VDDI_4    |             |
 
 # Pinouts (Fixed function)
 
@@ -191,6 +191,13 @@ SPI Master 2 (SDCard)
 * MSPI1_MOSI : W8/0
 * MSPI1_NSS : W7/0
 
+## MTWI
+
+I2C Master 1
+
+* MTWI_SCL  : S10/0
+* MTWI_SDA  : S9/0
+
 ## PWM
 
 PWM
@@ -265,13 +272,6 @@ System Control
 * SYS_PLLOUT : S4/0
 * SYS_RST   : S2/0
 
-## TWI
-
-I2C Master 1
-
-* TWI_SCL   : S10/0
-* TWI_SDA   : S9/0
-
 ## UART0
 
 UART (TX/RX) 1
@@ -283,27 +283,27 @@ UART (TX/RX) 1
 
 Power
 
-* VDD_0     : N1/0
-* VDD_1     : N31/0
-* VDD_2     : E13/0
-* VDD_3     : E31/0
-* VDD_4     : S8/0
-* VDD_5     : S31/0
-* VDD_6     : W10/0
-* VDD_7     : W31/0
+* VDDE_0    : N1/0
+* VDDE_1    : E13/0
+* VDDE_2    : W10/0
+* VDDI_0    : N31/0
+* VDDI_1    : E31/0
+* VDDI_2    : S8/0
+* VDDI_3    : S31/0
+* VDDI_4    : W31/0
 
 ## VSS
 
 GND
 
-* VSS_0     : N0/0
-* VSS_1     : N30/0
-* VSS_2     : E0/0
-* VSS_3     : E23/0
-* VSS_4     : S0/0
-* VSS_5     : S22/0
-* VSS_6     : W0/0
-* VSS_7     : W17/0
+* VSSE_0    : N30/0
+* VSSE_1    : E0/0
+* VSSE_2    : W17/0
+* VSSI_0    : N0/0
+* VSSI_1    : E23/0
+* VSSI_2    : S0/0
+* VSSI_3    : S22/0
+* VSSI_4    : W0/0
 
 # Pinmap for Libre-SOC 180nm
 
@@ -368,25 +368,15 @@ and UART2, for debug purposes
 
 ## VDD
 
-* VDD_0 1 N1/0
-* VDD_1 31 N31/0
-* VDD_2 45 E13/0
-* VDD_3 63 E31/0
-* VDD_4 72 S8/0
-* VDD_5 95 S31/0
-* VDD_6 106 W10/0
-* VDD_7 127 W31/0
+* VDDE_0 1 N1/0
+* VDDI_0 31 N31/0
+* VDDE_1 45 E13/0
 
 ## VSS
 
-* VSS_0 0 N0/0
-* VSS_1 30 N30/0
-* VSS_2 32 E0/0
-* VSS_3 55 E23/0
-* VSS_4 64 S0/0
-* VSS_5 86 S22/0
-* VSS_6 96 W0/0
-* VSS_7 113 W17/0
+* VSSI_0 0 N0/0
+* VSSE_0 30 N30/0
+* VSSE_1 32 E0/0
 
 ## SYS
 
@@ -400,13 +390,13 @@ and UART2, for debug purposes
 * SYS_CSEL1 70 S6/0
 * SYS_CSEL2 71 S7/0
 
-## TWI
+## MTWI
 
 I2C.
 
 
-* TWI_SDA 73 S9/0
-* TWI_SCL 74 S10/0
+* MTWI_SDA 73 S9/0
+* MTWI_SCL 74 S10/0
 
 ## MSPI0
 
@@ -472,6 +462,16 @@ I2C.
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
+|  55 | E VSSI_1    |             |             |             |
+|  63 | E VDDI_1    |             |             |             |
+|  64 | S VSSI_2    |             |             |             |
+|  72 | S VDDI_2    |             |             |             |
+|  86 | S VSSI_3    |             |             |             |
+|  95 | S VDDI_3    |             |             |             |
+|  96 | W VSSI_4    |             |             |             |
+| 106 | W VDDE_2    |             |             |             |
+| 113 | W VSSE_2    |             |             |             |
+| 127 | W VDDI_4    |             |             |             |
 
 # Reference Datasheets