rs6000: Fix formatting of *mov{si,di}_internal.*

	* config/rs6000/rs6000.md (*movsi_internal1): Fix formatting.  Improve
	formatting.
	(*movdi_internal64): Ditto.

From-SVN: r278822

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3c8f8d3346e974b9aaec695333da6ea971ed01d1..7eed4b2047a8587036ac0836cf4ed7029278028c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (*movsi_internal1): Fix formatting.  Improve
+       formatting.
+       (*movdi_internal64): Ditto.
+
 2019-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
 
        PR target/92602

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0187ba0a1a33cd73cc6b945a3012bd51297e0d6b..f3c8eb06fc1d3be54bed5ba5370eae14d5bcf75a 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6889,34 +6889,34 @@
                                 UNSPEC_MOVSI_GOT))]
   "")
 
-;;             MR           LA
-;;             LWZ          LFIWZX      LXSIWZX
-;;             STW          STFIWX      STXSIWX
-;;             LI           LIS         #
-;;             XXLOR        XXSPLTIB 0  XXSPLTIB -1 VSPLTISW
-;;             XXLXOR 0     XXLORC -1   P9 const
-;;             MTVSRWZ      MFVSRWZ
-;;             MF%1         MT%0        NOP
+;;        MR          LA
+;;        LWZ         LFIWZX      LXSIWZX
+;;        STW         STFIWX      STXSIWX
+;;        LI          LIS         #
+;;        XXLOR       XXSPLTIB 0  XXSPLTIB -1 VSPLTISW
+;;        XXLXOR 0    XXLORC -1   P9 const
+;;        MTVSRWZ     MFVSRWZ
+;;        MF%1        MT%0        NOP
 
 (define_insn "*movsi_internal1"
   [(set (match_operand:SI 0 "nonimmediate_operand"
-               "=r,         r,
-               r,           d,          v,
-               m,           Z,          Z,
-               r,           r,          r,
-               wa,          wa,         wa,         v,
-               wa,          v,          v,
-               wa,          r,
-               r,           *h,         *h")
+         "=r,         r,
+          r,          d,          v,
+          m,          Z,          Z,
+          r,          r,          r,
+          wa,         wa,         wa,         v,
+          wa,         v,          v,
+          wa,         r,
+          r,          *h,         *h")
        (match_operand:SI 1 "input_operand"
-               "r,          U,
-               m,           Z,          Z,
-               r,           d,          v,
-               I,           L,          n,
-               wa,          O,          wM,         wB,
-               O,           wM,         wS,
-               r,           wa,
-               *h,          r,          0"))]
+         "r,          U,
+          m,          Z,          Z,
+          r,          d,          v,
+          I,          L,          n,
+          wa,         O,          wM,         wB,
+          O,          wM,         wS,
+          r,          wa,
+          *h,         r,          0"))]
   "gpc_reg_operand (operands[0], SImode)
    || gpc_reg_operand (operands[1], SImode)"
   "@
@@ -6944,32 +6944,32 @@
    mt%0 %1
    nop"
   [(set_attr "type"
-               "*,         *,
-               load,       fpload,     fpload,
-               store,      fpstore,    fpstore,
-               *,          *,          *,
-               veclogical, vecsimple,  vecsimple,  vecsimple,
-               veclogical, veclogical, vecsimple,
-               mffgpr,     mftgpr,
-               *,          *,          *")
+         "*,          *,
+          load,       fpload,     fpload,
+          store,      fpstore,    fpstore,
+          *,          *,          *,
+          veclogical, vecsimple,  vecsimple,  vecsimple,
+          veclogical, veclogical, vecsimple,
+          mffgpr,     mftgpr,
+          *,          *,          *")
    (set_attr "length"
-               "*,         *,
-               *,          *,           *,
-               *,          *,           *,
-               *,          *,           8,
-               *,          *,           *,          *,
-               *,          *,           8,
-               *,          *,
-               *,          *,           *")
+         "*,          *,
+          *,          *,          *,
+          *,          *,          *,
+          *,          *,          8,
+          *,          *,          *,          *,
+          *,          *,          8,
+          *,          *,
+          *,          *,          *")
    (set_attr "isa"
-               "*,          *,
-               *,           p8v,       p8v,
-               *,           p8v,       p8v,
-               *,           *,         *,
-               p8v,         p9v,       p9v,       p8v,
-               p9v,         p8v,       p9v,
-               p8v,         p8v,
-               *,           *,         *")])
+         "*,          *,
+          *,          p8v,        p8v,
+          *,          p8v,        p8v,
+          *,          *,          *,
+          p8v,        p9v,        p9v,        p8v,
+          p9v,        p8v,        p9v,
+          p8v,        p8v,
+          *,          *,          *")])
 
 ;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
 ;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
@@ -8827,33 +8827,33 @@
   DONE;
 })
 
-;;             GPR store  GPR load   GPR move
-;;             GPR li     GPR lis    GPR #
-;;             FPR store  FPR load   FPR move
-;;             AVX store  AVX store  AVX load   AVX load   VSX move
-;;             P9 0       P9 -1      AVX 0/-1   VSX 0      VSX -1
-;;             P9 const   AVX const
-;;             From SPR   To SPR     SPR<->SPR
-;;             VSX->GPR   GPR->VSX
+;;        GPR store   GPR load    GPR move
+;;        GPR li      GPR lis     GPR #
+;;        FPR store   FPR load    FPR move
+;;        AVX store   AVX store   AVX load    AVX load    VSX move
+;;        P9 0        P9 -1       AVX 0/-1    VSX 0       VSX -1
+;;        P9 const    AVX const
+;;        From SPR    To SPR      SPR<->SPR
+;;        VSX->GPR    GPR->VSX
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-               "=YZ,       r,          r,
-               r,          r,          r,
-               m,          ^d,         ^d,
-               wY,         Z,          $v,         $v,         ^wa,
-               wa,         wa,         v,          wa,         wa,
-               v,          v,
-               r,          *h,         *h,
-               ?r,         ?wa")
+         "=YZ,        r,          r,
+          r,          r,          r,
+          m,          ^d,         ^d,
+          wY,         Z,          $v,         $v,         ^wa,
+          wa,         wa,         v,          wa,         wa,
+          v,          v,
+          r,          *h,         *h,
+          ?r,         ?wa")
        (match_operand:DI 1 "input_operand"
-               "r,         YZ,         r,
-               I,          L,          nF,
-               ^d,         m,          ^d,
-               ^v,         $v,         wY,         Z,          ^wa,
-               Oj,         wM,         OjwM,       Oj,         wM,
-               wS,         wB,
-               *h,         r,          0,
-               wa,         r"))]
+         "r,          YZ,         r,
+          I,          L,          nF,
+          ^d,         m,          ^d,
+          ^v,         $v,         wY,         Z,          ^wa,
+          Oj,         wM,         OjwM,       Oj,         wM,
+          wS,         wB,
+          *h,         r,          0,
+          wa,         r"))]
   "TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
@@ -8885,33 +8885,33 @@
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
   [(set_attr "type"
-               "store,      load,       *,
-               *,           *,          *,
-               fpstore,     fpload,     fpsimple,
-               fpstore,     fpstore,    fpload,     fpload,     veclogical,
-               vecsimple,   vecsimple,  vecsimple,  veclogical, veclogical,
-               vecsimple,   vecsimple,
-               mfjmpr,      mtjmpr,     *,
-               mftgpr,      mffgpr")
+         "store,      load,       *,
+          *,          *,          *,
+          fpstore,    fpload,     fpsimple,
+          fpstore,    fpstore,    fpload,     fpload,     veclogical,
+          vecsimple,  vecsimple,  vecsimple,  veclogical, veclogical,
+          vecsimple,  vecsimple,
+          mfjmpr,     mtjmpr,     *,
+          mftgpr,     mffgpr")
    (set_attr "size" "64")
    (set_attr "length"
-               "*,         *,          *,
-               *,          *,          20,
-               *,          *,          *,
-               *,          *,          *,          *,          *,
-               *,          *,          *,          *,          *,
-               8,          *,
-               *,          *,          *,
-               *,          *")
+         "*,          *,          *,
+          *,          *,          20,
+          *,          *,          *,
+          *,          *,          *,          *,          *,
+          *,          *,          *,          *,          *,
+          8,          *,
+          *,          *,          *,
+          *,          *")
    (set_attr "isa"
-               "*,         *,          *,
-               *,          *,          *,
-               *,          *,          *,
-               p9v,        p7v,        p9v,        p7v,        *,
-               p9v,        p9v,        p7v,        *,          *,
-               p7v,        p7v,
-               *,          *,          *,
-               p8v,        p8v")])
+         "*,          *,          *,
+          *,          *,          *,
+          *,          *,          *,
+          p9v,        p7v,        p9v,        p7v,        *,
+          p9v,        p9v,        p7v,        *,          *,
+          p7v,        p7v,
+          *,          *,          *,
+          p8v,        p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.