start on unit test

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 94c4396c740bd9f41c1fb96b60f063b832a688f5..a095c353dedc0dc72534a807b4fec250b974dfd1 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -199,29 +199,23 @@ class Scoreboard(Elaboratable):
     def ports(self):
         return list(self)
 
+IADD = 0
+ISUB = 1
+
+def int_instr(dut, op, src1, src2, dest):
+    yield dut.int_dest_i.eq(dest)
+    yield dut.int_src1_i.eq(src1)
+    yield dut.int_src2_i.eq(src2)
+    #yield dut.int_insn_i[op].eq(1)
+
 
 def scoreboard_sim(dut):
-    yield dut.dest_i.eq(1)
-    yield dut.issue_i.eq(1)
-    yield
-    yield dut.issue_i.eq(0)
-    yield
-    yield dut.src1_i.eq(1)
-    yield dut.issue_i.eq(1)
-    yield
-    yield
-    yield
-    yield dut.issue_i.eq(0)
-    yield
-    yield dut.go_read_i.eq(1)
-    yield
-    yield dut.go_read_i.eq(0)
-    yield
-    yield dut.go_write_i.eq(1)
-    yield
-    yield dut.go_write_i.eq(0)
+    for i in range(1, dut.n_regs):
+        yield dut.intregs.regs[i].reg.eq(i)
+    yield from int_instr(dut, IADD, 1, 2, 5)
     yield
 
+
 def test_scoreboard():
     dut = Scoreboard(32, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
@@ -230,5 +224,6 @@ def test_scoreboard():
 
     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 
+
 if __name__ == '__main__':
     test_scoreboard()

diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py
index 3cb5ef4507711a02ae2ebf3f22657c904e5255bd..091cf7eca57b74b3966be64b3b0718d620a14639 100644 (file)
--- a/src/regfile/regfile.py
+++ b/src/regfile/regfile.py
@@ -31,7 +31,7 @@ class Register(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        reg = Signal(self.width, name="reg")
+        self.reg = reg = Signal(self.width, name="reg")
 
         # read ports. has write-through detection (returns data written)
         for rp in self._rdports: