#### Quick intro
```python
-from migen.fhdl.std import *
+from migen import *
from migen.build.platforms import m1
plat = m1.Platform()
led = plat.request("user_led")
.. [myhdl] http://www.myhdl.org
-FHDL is made of several elements, which are briefly explained below. They all can be imported from the ``migen.fhdl.std`` module.
+FHDL is made of several elements, which are briefly explained below. They all can be imported directly from the ``migen`` module.
Expressions
***********
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
outa = Array(Signal() for a in range(dy))
self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
-print(verilog.convert(Example()))
+if __name__ == "__main__":
+ print(verilog.convert(Example()))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
-from migen.genlib.fsm import FSM, NextState, NextValue
-
class Example(Module):
def __init__(self):
self.bl = myfsm.before_leaving("FOO")
self.al = myfsm.after_leaving("FOO")
-example = Example()
-print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
+if __name__ == "__main__":
+ example = Example()
+ print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
from random import Random
-from migen.fhdl.std import *
+from migen import *
from migen.genlib.cdc import GrayCounter
-from migen.sim import Simulator
def tb(dut):
import subprocess
-from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
+from migen import *
from migen.fhdl.verilog import convert
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
from migen.genlib.divider import Divider
self.submodules.foo = CDM()
self.submodules.bar = CDM()
-mm = MultiMod()
-print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
+if __name__ == "__main__":
+ mm = MultiMod()
+ print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re}
-example = Example()
-print(verilog.convert(example, example.ios))
+
+if __name__ == "__main__":
+ example = Example()
+ print(verilog.convert(example, example.ios))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
from functools import reduce
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl.specials import SynthesisDirective
from migen.fhdl import verilog
from migen.genlib.cdc import *
def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
-ps = PulseSynchronizer("from", "to")
-v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
-print(v)
+
+if __name__ == "__main__":
+ ps = PulseSynchronizer("from", "to")
+ v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
+ print(v)
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
-from migen.genlib.record import *
+
L = [
("position", [
slave = Record(L)
self.comb += master.connect(slave)
-print(verilog.convert(Test()))
-print(layout_len(L))
-print(layout_partial(L, "position/x", "color"))
+
+if __name__ == "__main__":
+ print(verilog.convert(Test()))
+ print(layout_len(L))
+ print(layout_partial(L, "position/x", "color"))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
self.comb += s3.eq(0)
self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
-print(verilog.convert(Example()))
+
+if __name__ == "__main__":
+ print(verilog.convert(Example()))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
self.t = TSTriple(n)
self.specials += self.t.get_tristate(self.pad)
-e = Example()
-print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
+if __name__ == "__main__":
+ e = Example()
+ print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
from migen.genlib import divider
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
-example = Example(16)
-print(verilog.convert(example, example.ios | {example.ce, example.reset}))
+if __name__ == "__main__":
+ example = Example(16)
+ print(verilog.convert(example, example.ios | {example.ce, example.reset}))
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
# Our simple counter, which increments at every cycle.
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
# A slightly more elaborate counter.
+from functools import reduce
+from operator import add
+
from math import cos, pi
from scipy import signal
import matplotlib.pyplot as plt
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl import verilog
-from migen.sim import Simulator
-from functools import reduce
-from operator import add
# A synthesizable FIR filter.
class FIR(Module):
-from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen import *
class Mem(Module):
+from migen.fhdl.structure import *
+from migen.fhdl.module import *
+from migen.fhdl.specials import *
+from migen.fhdl.bitcontainer import *
+from migen.fhdl.decorators import *
+
+from migen.sim import *
+
+from migen.genlib.record import *
+from migen.genlib.fsm import *
-from migen.fhdl.std import Instance, Module
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
from migen.genlib.io import DifferentialInput, DifferentialOutput
import os
import sys
-from migen.fhdl.std import Signal
+from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from migen.genlib.io import CRG
from migen.fhdl import verilog, edif
from migen.util.misc import autotype
-
from migen.build import tools
-from migen.fhdl.std import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
from migen.genlib.io import *
-
from migen.genlib.resetsync import AsyncResetSynchronizer
return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
lattice_special_overrides = {
- AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
- DDROutput: LatticeDDROutput
+ AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
+ DDROutput: LatticeDDROutput
}
import os
import subprocess
-from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
-
from migen.build import tools
from migen.build.generic_platform import *
-from migen.build.sim import common
def _build_tb(platform, vns, serial, template):
-
- def io_name(ressource, subsignal=None):
- res = platform.lookup_request(ressource)
+ def io_name(resource, subsignal=None):
+ res = platform.lookup_request(resource)
if subsignal is not None:
res = getattr(res, subsignal)
return vns.get_name(res)
import sys
from distutils.version import StrictVersion
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.fhdl.module import Module
from migen.fhdl.specials import SynthesisDirective
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
import subprocess
import sys
-from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
from migen.build.generic_platform import *
from migen.build import tools
import subprocess
import sys
-from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
-
from migen.build.generic_platform import *
from migen.build import tools
from migen.build.xilinx import common
from migen.fhdl import structure as f
+__all__ = ["log2_int", "bits_for", "flen", "fiter", "fslice", "freversed"]
+
+
def log2_int(n, need_pow2=True):
l = 1
r = 0
from migen.fhdl.tools import insert_reset, rename_clock_domain
+__all__ = ["DecorateModule",
+ "InsertCE", "InsertReset", "RenameClockDomains",
+ "CEInserter", "ResetInserter", "ClockDomainsRenamer",
+ "ModuleTransformer"]
+
+
class ModuleTransformer:
# overload this in derived classes
def transform_instance(self, i):
-from collections import OrderedDict
-from collections import namedtuple
+from collections import OrderedDict, namedtuple
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
from migen.fhdl.namer import build_namespace
from migen.fhdl.tools import list_special_ios
from migen.fhdl.structure import _Fragment
from migen.fhdl.tools import rename_clock_domain
+__all__ = ["Module", "FinalizeError"]
+
+
class FinalizeError(Exception):
pass
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
from migen.fhdl.specials import _MemoryPort
from migen.fhdl.decorators import ModuleTransformer
from migen.util.misc import gcd_multiple
from migen.fhdl.verilog import _printexpr as verilog_printexpr
+__all__ = ["TSTriple", "Instance", "Memory",
+ "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
+
+
class Special(HUID):
def iter_expressions(self):
for x in []:
r += ");\n\n"
return r
+
(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
memory_filename = add_data_file(gn(memory) + ".init", content)
r += "initial begin\n"
- r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
+ r += "\t$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
r += "end\n\n"
+++ /dev/null
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module, FinalizeError
-from migen.fhdl.specials import TSTriple, Instance, Memory
-from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed
-from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains
-from migen.fhdl.decorators import (CEInserter, ResetInserter,
- ClockDomainsRenamer, ModuleTransformer)
-from migen.fhdl.std import *
-from migen.fhdl.bitcontainer import value_bits_sign
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
+from migen.fhdl.bitcontainer import value_bits_sign
class NoRetiming(Special):
-from migen.fhdl.std import *
-
"""
Encoders and decoders between binary and one-hot representation
"""
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+
class Encoder(Module):
"""Encode one-hot to binary
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
class Divider(Module):
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Memory
from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
from migen.genlib.record import layout_len, Record
from collections import OrderedDict
-from migen.fhdl.std import *
-from migen.fhdl.module import FinalizeError
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module, FinalizeError
from migen.fhdl.visit import NodeTransformer
from migen.fhdl.bitcontainer import value_bits_sign
+__all__ = ["AnonymousState", "NextState", "NextValue", "FSM"]
+
+
class AnonymousState:
pass
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
class DifferentialInput(Special):
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
def split(v, *counts):
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
from migen.fhdl.tracer import get_obj_var_name
from functools import reduce
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
class AsyncResetSynchronizer(Special):
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+
(SP_WITHDRAW, SP_CE) = range(2)
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
class BitonicSort(Module):
import operator
from collections import defaultdict
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Assign, _Fragment
from migen.fhdl.tools import list_inputs
+__all__ = ["Simulator"]
+
+
class ClockState:
def __init__(self, period, times_before_tick):
self.period = period
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
from migen.fhdl import verilog
import unittest
-from migen.fhdl.std import *
+from migen import *
from migen.genlib.coding import *
from migen.test.support import SimCase, SimBench
import unittest
-from migen.fhdl.std import *
+from migen import *
from migen.genlib.fifo import SyncFIFO
from migen.test.support import SimCase, SimBench
import unittest
-from migen.fhdl.std import *
+from migen import *
from migen.test.support import SimCase
import unittest
-from migen.fhdl.std import *
+from migen import *
def _same_slices(a, b):
import unittest
from random import randrange
-from migen.fhdl.std import *
+from migen import *
from migen.genlib.sort import *
from migen.test.support import SimCase
import subprocess
import os
-from migen.fhdl.std import *
+from migen import *
from migen.fhdl.verilog import convert
projects / litex.git / commitdiff