dev: seperate legacy io offsets from PCI offset

The PC platform has a single IO range that is used both legacy IO and PCI IO
while other platforms may use seperate regions. Provide another mechanism to
configure the legacy IO base address range and set it to the PCI IO address
range for x86.

diff --git a/src/dev/Pci.py b/src/dev/Pci.py
index 79ea1f68ae59c2717c15baff1efff295a9fccc74..ef71371860a505c36e004e0038dd3f6e1ce133ab 100644 (file)
--- a/src/dev/Pci.py
+++ b/src/dev/Pci.py
@@ -98,6 +98,7 @@ class PciDevice(DmaDevice):
     BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
     BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
     BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
+    LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
 
     CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
     SubsystemID = Param.UInt16(0x00, "Subsystem ID")

diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index a24fa8da8f69d0c6504b96d2bbddbc24140e6f7f..adc12bb55aa24fa879bb6d2c23273c1f3bea9633 100644 (file)
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -213,7 +213,7 @@ PciDevice::PciDevice(const Params *p)
 
     for (int i = 0; i < 6; ++i) {
         if (legacyIO[i]) {
-            BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
+            BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
             config.baseAddr[i] = 0;
         } else {
             BARAddrs[i] = 0;

diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 45c49ce3a7365a5c367d6075e7d8d0cfb286c866..911853dd50cb4b57f455daf73c05e810d6b3a554 100644 (file)
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -84,6 +84,7 @@ class SouthBridge(SimObject):
     ide.ProgIF = 0x80
     ide.InterruptLine = 14
     ide.InterruptPin = 1
+    ide.LegacyIOBase = x86IOAddress(0)
 
     def attachIO(self, bus, dma_ports):
         # Route interupt signals