tests: Removed 60.bzip2 tests
authorBobby R. Bruce <bbruce@ucdavis.edu>
Tue, 14 Jan 2020 20:13:24 +0000 (12:13 -0800)
committerBobby R. Bruce <bbruce@ucdavis.edu>
Fri, 24 Jan 2020 05:48:26 +0000 (05:48 +0000)
In an effort to cleanup the old tests, and migrate useful tests to be
executed via `test/main.py`, it has been decided that the
`test/quick/60.bzip2` tests should be removed.

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: I8469814a2f4715655960b9049182e426e10380ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24385
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
25 files changed:
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout [deleted file]
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout [deleted file]
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt [deleted file]
tests/long/se/60.bzip2/test.py [deleted file]

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
deleted file mode 100644 (file)
index 7df53f2..0000000
+++ /dev/null
@@ -1,997 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr
deleted file mode 100755 (executable)
index caeab83..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
deleted file mode 100755 (executable)
index b95f9cd..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:01
-gem5 executing on e108600-lin, pid 17341
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 1150225722500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
deleted file mode 100644 (file)
index 24c0fbb..0000000
+++ /dev/null
@@ -1,953 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.150356                       # Number of seconds simulated
-sim_ticks                                1150356296500                       # Number of ticks simulated
-final_tick                               1150356296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 374766                       # Simulator instruction rate (inst/s)
-host_op_rate                                   403753                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              279117141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273688                       # Number of bytes of host memory used
-host_seconds                                  4121.41                       # Real time elapsed on the host
-sim_insts                                  1544563088                       # Number of instructions simulated
-sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             50240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         132097728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132147968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67851072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67851072                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                785                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2064027                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2064812                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1060173                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1060173                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                43673                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            114832012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               114875685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           43673                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              43673                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          58982658                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               58982658                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          58982658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               43673                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           114832012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              173858343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2064812                       # Number of read requests accepted
-system.physmem.writeReqs                      1060173                       # Number of write requests accepted
-system.physmem.readBursts                     2064812                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1060173                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                132064448                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83520                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67849344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132147968                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67851072                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1305                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              128530                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125798                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122667                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124564                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              123583                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              123689                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              124368                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124965                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              132503                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              134776                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             133237                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             134508                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             134521                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             134606                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             130538                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130654                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               66782                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64941                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               63176                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               63581                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               63564                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63647                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               65050                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66062                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67977                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               68434                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              68153                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              68587                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              68034                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              68534                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              67158                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              66466                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1150356195500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2064812                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1060173                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1919552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    143941                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    57354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    62496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    62733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    62687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    62667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    62593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    62549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    62604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    62637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    63099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    62454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    62359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1927714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.704114                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.833686                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.867792                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1497696     77.69%     77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       310699     16.12%     93.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52184      2.71%     96.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20631      1.07%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13074      0.68%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7807      0.40%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5185      0.27%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5186      0.27%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        15252      0.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1927714                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         62200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.128826                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       23.842942                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      148.982645                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          62161     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            7      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            5      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           62200                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         62200                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.044148                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.013066                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.029999                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              29988     48.21%     48.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1141      1.83%     50.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              29436     47.32%     97.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1609      2.59%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 24      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           62200                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    60011294750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               98702051000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10317535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29082.19                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47832.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         114.80                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          58.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      114.88                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       58.98                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.36                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.46                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.14                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     775182                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    420747                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.57                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                       368115.75                       # Average gap between requests
-system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6705024060                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3563778240                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7126890960                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               2697711660                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           71598184320.000015                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47589199680                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             2602904160                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy      242927855970                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy       71960703840                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy        82354339920                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             539151608970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              468.682274                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1039160467250                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE     3513710000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     30352766000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   319025802500                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 187397997250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     77329050000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 532736970750                       # Time in different power states
-system.physmem_1.actEnergy                 7058925300                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3751896390                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7606549020                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               2836250460                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           71153184960.000015                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            47703954360                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             2452947360                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy      248582355720                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy       68636874240                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy        80784488595                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             540590019675                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              469.932679                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1039304472000                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE     3115835000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     30156708000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   315425606000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 178743425250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     77779220750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 545135501500                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               240030332                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186613747                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14536765                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            132238924                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122337864                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.512749                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15662658                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             538                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                232                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              306                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          162                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.numSyscalls                    46                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2300712593                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1544563088                       # Number of instructions committed
-system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41389188                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.489556                       # CPI: cycles per instruction
-system.cpu.ipc                               0.671341                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
-system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                       0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatMult                    0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc                    0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc                3      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     61.95% # Class of committed instruction
-system.cpu.op_class_0::MemRead              458306322     27.54%     89.49% # Class of committed instruction
-system.cpu.op_class_0::MemWrite             174847022     10.51%    100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead                12      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite               24      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
-system.cpu.tickCycles                      1845105384                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       455607209                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9220185                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.806447                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624504262                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9224281                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.702216                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        9872962500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.806447                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997511                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997511                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1190                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1277413521                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1277413521                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    454174952                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       454174952                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170329187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170329187                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624504139                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624504139                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624504140                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624504140                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7333496                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7333496                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2256860                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2256860                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9590356                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9590356                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9590358                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9590358                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 208281810000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 119887020500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 328168830500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 328168830500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 328168830500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 328168830500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461508448                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461508448                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total            3                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    634094495                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    634094495                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    634094498                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    634094498                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015890                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015890                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013077                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013077                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015124                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015124                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015124                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015124                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34218.628641                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34218.621505                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      3670078                       # number of writebacks
-system.cpu.dcache.writebacks::total           3670078                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       366027                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       366027                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       366076                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       366076                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       366076                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       366076                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333447                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7333447                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890833                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890833                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9224280                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9224280                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9224281                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9224281                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  92449770000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  92449770000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        81000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        81000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 293393691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 293393772500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015890                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015890                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014547                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014547                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        81000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        81000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                33                       # number of replacements
-system.cpu.icache.tags.tagsinuse           660.481453                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           466324528                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               822                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567304.778589                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   660.481453                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322501                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322501                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          789                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          751                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.385254                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         932651522                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        932651522                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    466324528                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       466324528                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     466324528                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        466324528                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    466324528                       # number of overall hits
-system.cpu.icache.overall_hits::total       466324528                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          822                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           822                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          822                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            822                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          822                       # number of overall misses
-system.cpu.icache.overall_misses::total           822                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     75338000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     75338000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     75338000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     75338000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     75338000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     75338000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    466325350                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    466325350                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    466325350                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    466325350                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    466325350                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    466325350                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 91652.068127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 91652.068127                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks           33                       # number of writebacks
-system.cpu.icache.writebacks::total                33                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          822                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          822                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          822                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          822                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          822                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          822                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74516000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     74516000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     74516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     74516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     74516000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     74516000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          2032379                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31895.934748                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           16378358                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2065147                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.930844                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      54709395000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    10.372068                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.532774                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000317                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000779                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.972291                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.973387                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          831                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2946                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7191                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21752                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149614963                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149614963                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3670078                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3670078                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks           33                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total           33                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1078495                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1078495                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           37                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           37                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6081752                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6081752                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           37                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7160247                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7160284                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           37                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7160247                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7160284                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       812338                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       812338                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          785                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          785                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1251696                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1251696                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          785                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2064034                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2064819                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          785                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2064034                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2064819                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  78265681500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  78265681500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     72863000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     72863000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 126082122000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 126082122000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     72863000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 204347803500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 204420666500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     72863000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 204347803500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 204420666500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3670078                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3670078                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks           33                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total           33                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890833                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1890833                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          822                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          822                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333448                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7333448                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          822                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9224281                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9225103                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          822                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9224281                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9225103                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.429619                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.429619                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.954988                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.954988                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.170683                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.170683                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.954988                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223761                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.223826                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954988                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223761                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.223826                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96346.202566                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96346.202566                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92819.108280                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92819.108280                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100729.028454                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100729.028454                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92819.108280                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99004.087869                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 99001.736472                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92819.108280                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99004.087869                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 99001.736472                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1060173                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1060173                       # number of writebacks
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            7                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            7                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            7                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            7                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            7                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          215                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          215                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       812338                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       812338                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1251689                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1251689                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          785                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2064027                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2064812                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          785                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2064027                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2064812                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  70142301500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  70142301500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65013000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65013000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65013000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65013000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.429619                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.429619                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.954988                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.170682                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.170682                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223760                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.223825                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223760                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.223825                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     18445321                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9220230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1444                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1438                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       7334270                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4730251                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean           33                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6522313                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890833                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890833                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          822                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333448                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1677                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27668747                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27670424                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825238976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          825293696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2032379                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              67851072                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     11257482                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000271                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.016506                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11254432     99.97%     99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3044      0.03%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11257482                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12892771500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1233000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13836424993                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       4095962                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2031307                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp            1252474                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1060173                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           970977                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            812338                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           812338                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1252474                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6160774                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6160774                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199999040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               199999040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2064812                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2064812    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2064812                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8805297000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11285202500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
deleted file mode 100644 (file)
index 5da6802..0000000
+++ /dev/null
@@ -1,962 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
deleted file mode 100755 (executable)
index 5467490..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
deleted file mode 100755 (executable)
index 19305f0..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 17:55:48
-gem5 started Apr  3 2017 17:56:14
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54235
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 787835965500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
deleted file mode 100644 (file)
index 6256fdd..0000000
+++ /dev/null
@@ -1,1282 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.787836                      
-sim_ticks                                787835965500                      
-final_tick                               787835965500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 147468                      
-host_op_rate                                   158874                      
-host_tick_rate                               75218875                      
-host_mem_usage                                 340272                      
-host_seconds                                 10473.91                      
-sim_insts                                  1544563024                      
-sim_ops                                    1664032416                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.physmem.bytes_read::cpu.inst             65344                      
-system.physmem.bytes_read::cpu.data         236015808                      
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63804544                      
-system.physmem.bytes_read::total            299885696                      
-system.physmem.bytes_inst_read::cpu.inst        65344                      
-system.physmem.bytes_inst_read::total           65344                      
-system.physmem.bytes_written::writebacks    104593152                      
-system.physmem.bytes_written::total         104593152                      
-system.physmem.num_reads::cpu.inst               1021                      
-system.physmem.num_reads::cpu.data            3687747                      
-system.physmem.num_reads::cpu.l2cache.prefetcher       996946                      
-system.physmem.num_reads::total               4685714                      
-system.physmem.num_writes::writebacks         1634268                      
-system.physmem.num_writes::total              1634268                      
-system.physmem.bw_read::cpu.inst                82941                      
-system.physmem.bw_read::cpu.data            299574808                      
-system.physmem.bw_read::cpu.l2cache.prefetcher     80987092                      
-system.physmem.bw_read::total               380644841                      
-system.physmem.bw_inst_read::cpu.inst           82941                      
-system.physmem.bw_inst_read::total              82941                      
-system.physmem.bw_write::writebacks         132760062                      
-system.physmem.bw_write::total              132760062                      
-system.physmem.bw_total::writebacks         132760062                      
-system.physmem.bw_total::cpu.inst               82941                      
-system.physmem.bw_total::cpu.data           299574808                      
-system.physmem.bw_total::cpu.l2cache.prefetcher     80987092                      
-system.physmem.bw_total::total              513404904                      
-system.physmem.readReqs                       4685714                      
-system.physmem.writeReqs                      1634268                      
-system.physmem.readBursts                     4685714                      
-system.physmem.writeBursts                    1634268                      
-system.physmem.bytesReadDRAM                299374336                      
-system.physmem.bytesReadWrQ                    511360                      
-system.physmem.bytesWritten                 104589440                      
-system.physmem.bytesReadSys                 299885696                      
-system.physmem.bytesWrittenSys              104593152                      
-system.physmem.servicedByWrQ                     7990                      
-system.physmem.mergedWrBursts                      28                      
-system.physmem.neitherReadNorWriteReqs              0                      
-system.physmem.perBankRdBursts::0              301500                      
-system.physmem.perBankRdBursts::1              301960                      
-system.physmem.perBankRdBursts::2              285447                      
-system.physmem.perBankRdBursts::3              288137                      
-system.physmem.perBankRdBursts::4              288946                      
-system.physmem.perBankRdBursts::5              285921                      
-system.physmem.perBankRdBursts::6              281288                      
-system.physmem.perBankRdBursts::7              278400                      
-system.physmem.perBankRdBursts::8              294011                      
-system.physmem.perBankRdBursts::9              300115                      
-system.physmem.perBankRdBursts::10             292046                      
-system.physmem.perBankRdBursts::11             297684                      
-system.physmem.perBankRdBursts::12             299531                      
-system.physmem.perBankRdBursts::13             298464                      
-system.physmem.perBankRdBursts::14             294115                      
-system.physmem.perBankRdBursts::15             290159                      
-system.physmem.perBankWrBursts::0              103775                      
-system.physmem.perBankWrBursts::1              101738                      
-system.physmem.perBankWrBursts::2               99347                      
-system.physmem.perBankWrBursts::3               99748                      
-system.physmem.perBankWrBursts::4               99113                      
-system.physmem.perBankWrBursts::5               98946                      
-system.physmem.perBankWrBursts::6              102275                      
-system.physmem.perBankWrBursts::7              103989                      
-system.physmem.perBankWrBursts::8              105110                      
-system.physmem.perBankWrBursts::9              104316                      
-system.physmem.perBankWrBursts::10             101973                      
-system.physmem.perBankWrBursts::11             102390                      
-system.physmem.perBankWrBursts::12             102662                      
-system.physmem.perBankWrBursts::13             102242                      
-system.physmem.perBankWrBursts::14             104082                      
-system.physmem.perBankWrBursts::15             102504                      
-system.physmem.numRdRetry                           0                      
-system.physmem.numWrRetry                           0                      
-system.physmem.totGap                    787835924500                      
-system.physmem.readPktSize::0                       0                      
-system.physmem.readPktSize::1                       0                      
-system.physmem.readPktSize::2                       0                      
-system.physmem.readPktSize::3                       0                      
-system.physmem.readPktSize::4                       0                      
-system.physmem.readPktSize::5                       0                      
-system.physmem.readPktSize::6                 4685714                      
-system.physmem.writePktSize::0                      0                      
-system.physmem.writePktSize::1                      0                      
-system.physmem.writePktSize::2                      0                      
-system.physmem.writePktSize::3                      0                      
-system.physmem.writePktSize::4                      0                      
-system.physmem.writePktSize::5                      0                      
-system.physmem.writePktSize::6                1634268                      
-system.physmem.rdQLenPdf::0                   2727826                      
-system.physmem.rdQLenPdf::1                   1050681                      
-system.physmem.rdQLenPdf::2                    326941                      
-system.physmem.rdQLenPdf::3                    233426                      
-system.physmem.rdQLenPdf::4                    158423                      
-system.physmem.rdQLenPdf::5                     90275                      
-system.physmem.rdQLenPdf::6                     39813                      
-system.physmem.rdQLenPdf::7                     24457                      
-system.physmem.rdQLenPdf::8                     17994                      
-system.physmem.rdQLenPdf::9                      4464                      
-system.physmem.rdQLenPdf::10                     1780                      
-system.physmem.rdQLenPdf::11                      895                      
-system.physmem.rdQLenPdf::12                      477                      
-system.physmem.rdQLenPdf::13                      261                      
-system.physmem.rdQLenPdf::14                       11                      
-system.physmem.rdQLenPdf::15                        0                      
-system.physmem.rdQLenPdf::16                        0                      
-system.physmem.rdQLenPdf::17                        0                      
-system.physmem.rdQLenPdf::18                        0                      
-system.physmem.rdQLenPdf::19                        0                      
-system.physmem.rdQLenPdf::20                        0                      
-system.physmem.rdQLenPdf::21                        0                      
-system.physmem.rdQLenPdf::22                        0                      
-system.physmem.rdQLenPdf::23                        0                      
-system.physmem.rdQLenPdf::24                        0                      
-system.physmem.rdQLenPdf::25                        0                      
-system.physmem.rdQLenPdf::26                        0                      
-system.physmem.rdQLenPdf::27                        0                      
-system.physmem.rdQLenPdf::28                        0                      
-system.physmem.rdQLenPdf::29                        0                      
-system.physmem.rdQLenPdf::30                        0                      
-system.physmem.rdQLenPdf::31                        0                      
-system.physmem.wrQLenPdf::0                         1                      
-system.physmem.wrQLenPdf::1                         1                      
-system.physmem.wrQLenPdf::2                         1                      
-system.physmem.wrQLenPdf::3                         1                      
-system.physmem.wrQLenPdf::4                         1                      
-system.physmem.wrQLenPdf::5                         1                      
-system.physmem.wrQLenPdf::6                         1                      
-system.physmem.wrQLenPdf::7                         1                      
-system.physmem.wrQLenPdf::8                         1                      
-system.physmem.wrQLenPdf::9                         1                      
-system.physmem.wrQLenPdf::10                        1                      
-system.physmem.wrQLenPdf::11                        1                      
-system.physmem.wrQLenPdf::12                        1                      
-system.physmem.wrQLenPdf::13                        1                      
-system.physmem.wrQLenPdf::14                        1                      
-system.physmem.wrQLenPdf::15                    24253                      
-system.physmem.wrQLenPdf::16                    26721                      
-system.physmem.wrQLenPdf::17                    55721                      
-system.physmem.wrQLenPdf::18                    72860                      
-system.physmem.wrQLenPdf::19                    84494                      
-system.physmem.wrQLenPdf::20                    93247                      
-system.physmem.wrQLenPdf::21                    99524                      
-system.physmem.wrQLenPdf::22                   103226                      
-system.physmem.wrQLenPdf::23                   104977                      
-system.physmem.wrQLenPdf::24                   106102                      
-system.physmem.wrQLenPdf::25                   106319                      
-system.physmem.wrQLenPdf::26                   107599                      
-system.physmem.wrQLenPdf::27                   108399                      
-system.physmem.wrQLenPdf::28                   109635                      
-system.physmem.wrQLenPdf::29                   109963                      
-system.physmem.wrQLenPdf::30                   109142                      
-system.physmem.wrQLenPdf::31                   102277                      
-system.physmem.wrQLenPdf::32                   101239                      
-system.physmem.wrQLenPdf::33                     4710                      
-system.physmem.wrQLenPdf::34                     1941                      
-system.physmem.wrQLenPdf::35                      910                      
-system.physmem.wrQLenPdf::36                      451                      
-system.physmem.wrQLenPdf::37                      238                      
-system.physmem.wrQLenPdf::38                      127                      
-system.physmem.wrQLenPdf::39                       69                      
-system.physmem.wrQLenPdf::40                       40                      
-system.physmem.wrQLenPdf::41                       17                      
-system.physmem.wrQLenPdf::42                       11                      
-system.physmem.wrQLenPdf::43                        7                      
-system.physmem.wrQLenPdf::44                        3                      
-system.physmem.wrQLenPdf::45                        2                      
-system.physmem.wrQLenPdf::46                        1                      
-system.physmem.wrQLenPdf::47                        0                      
-system.physmem.wrQLenPdf::48                        0                      
-system.physmem.wrQLenPdf::49                        0                      
-system.physmem.wrQLenPdf::50                        0                      
-system.physmem.wrQLenPdf::51                        0                      
-system.physmem.wrQLenPdf::52                        0                      
-system.physmem.wrQLenPdf::53                        0                      
-system.physmem.wrQLenPdf::54                        0                      
-system.physmem.wrQLenPdf::55                        0                      
-system.physmem.wrQLenPdf::56                        0                      
-system.physmem.wrQLenPdf::57                        0                      
-system.physmem.wrQLenPdf::58                        0                      
-system.physmem.wrQLenPdf::59                        0                      
-system.physmem.wrQLenPdf::60                        0                      
-system.physmem.wrQLenPdf::61                        0                      
-system.physmem.wrQLenPdf::62                        0                      
-system.physmem.wrQLenPdf::63                        0                      
-system.physmem.bytesPerActivate::samples      4259361                      
-system.physmem.bytesPerActivate::mean       94.841028                      
-system.physmem.bytesPerActivate::gmean      78.814946                      
-system.physmem.bytesPerActivate::stdev     102.698820                      
-system.physmem.bytesPerActivate::0-127        3400000     79.82%     79.82%
-system.physmem.bytesPerActivate::128-255       662329     15.55%     95.37%
-system.physmem.bytesPerActivate::256-383        94740      2.22%     97.60%
-system.physmem.bytesPerActivate::384-511        35136      0.82%     98.42%
-system.physmem.bytesPerActivate::512-639        22172      0.52%     98.94%
-system.physmem.bytesPerActivate::640-767        12513      0.29%     99.24%
-system.physmem.bytesPerActivate::768-895         7488      0.18%     99.41%
-system.physmem.bytesPerActivate::896-1023         5149      0.12%     99.53%
-system.physmem.bytesPerActivate::1024-1151        19834      0.47%    100.00%
-system.physmem.bytesPerActivate::total        4259361                      
-system.physmem.rdPerTurnAround::samples         98005                      
-system.physmem.rdPerTurnAround::mean        47.729004                      
-system.physmem.rdPerTurnAround::stdev       99.044358                      
-system.physmem.rdPerTurnAround::0-255           95588     97.53%     97.53%
-system.physmem.rdPerTurnAround::256-511          1180      1.20%     98.74%
-system.physmem.rdPerTurnAround::512-767           706      0.72%     99.46%
-system.physmem.rdPerTurnAround::768-1023          397      0.41%     99.86%
-system.physmem.rdPerTurnAround::1024-1279          101      0.10%     99.97%
-system.physmem.rdPerTurnAround::1280-1535           19      0.02%     99.99%
-system.physmem.rdPerTurnAround::1536-1791            5      0.01%     99.99%
-system.physmem.rdPerTurnAround::1792-2047            2      0.00%     99.99%
-system.physmem.rdPerTurnAround::2048-2303            3      0.00%    100.00%
-system.physmem.rdPerTurnAround::2560-2815            1      0.00%    100.00%
-system.physmem.rdPerTurnAround::2816-3071            1      0.00%    100.00%
-system.physmem.rdPerTurnAround::3072-3327            1      0.00%    100.00%
-system.physmem.rdPerTurnAround::4608-4863            1      0.00%    100.00%
-system.physmem.rdPerTurnAround::total           98005                      
-system.physmem.wrPerTurnAround::samples         98005                      
-system.physmem.wrPerTurnAround::mean        16.674761                      
-system.physmem.wrPerTurnAround::gmean       16.634865                      
-system.physmem.wrPerTurnAround::stdev        1.202481                      
-system.physmem.wrPerTurnAround::16              70360     71.79%     71.79%
-system.physmem.wrPerTurnAround::17               1982      2.02%     73.81%
-system.physmem.wrPerTurnAround::18              17660     18.02%     91.83%
-system.physmem.wrPerTurnAround::19               5209      5.32%     97.15%
-system.physmem.wrPerTurnAround::20               1729      1.76%     98.91%
-system.physmem.wrPerTurnAround::21                596      0.61%     99.52%
-system.physmem.wrPerTurnAround::22                225      0.23%     99.75%
-system.physmem.wrPerTurnAround::23                114      0.12%     99.87%
-system.physmem.wrPerTurnAround::24                 71      0.07%     99.94%
-system.physmem.wrPerTurnAround::25                 31      0.03%     99.97%
-system.physmem.wrPerTurnAround::26                 17      0.02%     99.99%
-system.physmem.wrPerTurnAround::27                  4      0.00%     99.99%
-system.physmem.wrPerTurnAround::28                  3      0.00%    100.00%
-system.physmem.wrPerTurnAround::29                  1      0.00%    100.00%
-system.physmem.wrPerTurnAround::31                  2      0.00%    100.00%
-system.physmem.wrPerTurnAround::33                  1      0.00%    100.00%
-system.physmem.wrPerTurnAround::total           98005                      
-system.physmem.totQLat                   162836208305                      
-system.physmem.totMemAccLat              250543533305                      
-system.physmem.totBusLat                  23388620000                      
-system.physmem.avgQLat                       34810.99                      
-system.physmem.avgBusLat                      5000.00                      
-system.physmem.avgMemAccLat                  53560.99                      
-system.physmem.avgRdBW                         380.00                      
-system.physmem.avgWrBW                         132.76                      
-system.physmem.avgRdBWSys                      380.64                      
-system.physmem.avgWrBWSys                      132.76                      
-system.physmem.peakBW                        12800.00                      
-system.physmem.busUtil                           4.01                      
-system.physmem.busUtilRead                       2.97                      
-system.physmem.busUtilWrite                      1.04                      
-system.physmem.avgRdQLen                         1.44                      
-system.physmem.avgWrQLen                        24.94                      
-system.physmem.readRowHits                    1712017                      
-system.physmem.writeRowHits                    340548                      
-system.physmem.readRowHitRate                   36.60                      
-system.physmem.writeRowHitRate                  20.84                      
-system.physmem.avgGap                       124657.94                      
-system.physmem.pageHitRate                      32.52                      
-system.physmem_0.actEnergy                15118935720                      
-system.physmem_0.preEnergy                 8035889730                      
-system.physmem_0.readEnergy               16504816860                      
-system.physmem_0.writeEnergy               4222619820                      
-system.physmem_0.refreshEnergy           59457815040.000015                      
-system.physmem_0.actBackEnergy            64415436660                      
-system.physmem_0.preBackEnergy             1624122240                      
-system.physmem_0.actPowerDownEnergy      222796740750                      
-system.physmem_0.prePowerDownEnergy       36224267040                      
-system.physmem_0.selfRefreshEnergy        16152645360                      
-system.physmem_0.totalEnergy             444563646270                      
-system.physmem_0.averagePower              564.284526                      
-system.physmem_0.totalIdleTime           642315388170                      
-system.physmem_0.memoryStateTime::IDLE     1436139102                      
-system.physmem_0.memoryStateTime::REF     25173062000                      
-system.physmem_0.memoryStateTime::SREF    59398115500                      
-system.physmem_0.memoryStateTime::PRE_PDN  94331998561                      
-system.physmem_0.memoryStateTime::ACT    118911366978                      
-system.physmem_0.memoryStateTime::ACT_PDN 488585283359                      
-system.physmem_1.actEnergy                15292958940                      
-system.physmem_1.preEnergy                 8128385265                      
-system.physmem_1.readEnergy               16894132500                      
-system.physmem_1.writeEnergy               4307956380                      
-system.physmem_1.refreshEnergy           58918161120.000015                      
-system.physmem_1.actBackEnergy            64834688190                      
-system.physmem_1.preBackEnergy             1616111040                      
-system.physmem_1.actPowerDownEnergy      219342669570                      
-system.physmem_1.prePowerDownEnergy       35641510560                      
-system.physmem_1.selfRefreshEnergy        18222503400                      
-system.physmem_1.totalEnergy             443208649005                      
-system.physmem_1.averagePower              562.564626                      
-system.physmem_1.totalIdleTime           641423107931                      
-system.physmem_1.memoryStateTime::IDLE     1455389769                      
-system.physmem_1.memoryStateTime::REF     24945910000                      
-system.physmem_1.memoryStateTime::SREF    67593570250                      
-system.physmem_1.memoryStateTime::PRE_PDN  92814429154                      
-system.physmem_1.memoryStateTime::ACT    120009883050                      
-system.physmem_1.memoryStateTime::ACT_PDN 481016783277                      
-system.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.branchPred.lookups               286288991                      
-system.cpu.branchPred.condPredicted         223379889                      
-system.cpu.branchPred.condIncorrect          14638803                      
-system.cpu.branchPred.BTBLookups            157014468                      
-system.cpu.branchPred.BTBHits               150316303                      
-system.cpu.branchPred.BTBCorrect                    0                      
-system.cpu.branchPred.BTBHitPct             95.734046                      
-system.cpu.branchPred.usedRAS                16636731                      
-system.cpu.branchPred.RASInCorrect                 64                      
-system.cpu.branchPred.indirectLookups            3547                      
-system.cpu.branchPred.indirectHits               2042                      
-system.cpu.branchPred.indirectMisses             1505                      
-system.cpu.branchPredindirectMispredicted          136                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.hits              0                      
-system.cpu.istage2_mmu.stage2_tlb.misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.itb.walker.walks                         0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.itb.walker.walkRequestOrigin::total            0                      
-system.cpu.itb.inst_hits                            0                      
-system.cpu.itb.inst_misses                          0                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.flush_tlb                            0                      
-system.cpu.itb.flush_tlb_mva                        0                      
-system.cpu.itb.flush_tlb_mva_asid                   0                      
-system.cpu.itb.flush_tlb_asid                       0                      
-system.cpu.itb.flush_entries                        0                      
-system.cpu.itb.align_faults                         0                      
-system.cpu.itb.prefetch_faults                      0                      
-system.cpu.itb.domain_faults                        0                      
-system.cpu.itb.perms_faults                         0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.inst_accesses                        0                      
-system.cpu.itb.hits                                 0                      
-system.cpu.itb.misses                               0                      
-system.cpu.itb.accesses                             0                      
-system.cpu.workload.numSyscalls                    46                      
-system.cpu.pwrStateResidencyTicks::ON    787835965500                      
-system.cpu.numCycles                       1575671932                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.fetch.icacheStallCycles           13942337                      
-system.cpu.fetch.Insts                     2067450540                      
-system.cpu.fetch.Branches                   286288991                      
-system.cpu.fetch.predictedBranches          166955076                      
-system.cpu.fetch.Cycles                    1546978368                      
-system.cpu.fetch.SquashCycles                29302454                      
-system.cpu.fetch.MiscStallCycles                  311                      
-system.cpu.fetch.IcacheWaitRetryStallCycles         1029                      
-system.cpu.fetch.CacheLines                 656906223                      
-system.cpu.fetch.IcacheSquashes                   925                      
-system.cpu.fetch.rateDist::samples         1575573272                      
-system.cpu.fetch.rateDist::mean              1.405744                      
-system.cpu.fetch.rateDist::stdev             1.233501                      
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00%
-system.cpu.fetch.rateDist::0                493163312     31.30%     31.30%
-system.cpu.fetch.rateDist::1                465492881     29.54%     60.84%
-system.cpu.fetch.rateDist::2                101391668      6.44%     67.28%
-system.cpu.fetch.rateDist::3                515525411     32.72%    100.00%
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00%
-system.cpu.fetch.rateDist::min_value                0                      
-system.cpu.fetch.rateDist::max_value                3                      
-system.cpu.fetch.rateDist::total           1575573272                      
-system.cpu.fetch.branchRate                  0.181693                      
-system.cpu.fetch.rate                        1.312107                      
-system.cpu.decode.IdleCycles                 74679257                      
-system.cpu.decode.BlockedCycles             578142352                      
-system.cpu.decode.RunCycles                 849952798                      
-system.cpu.decode.UnblockCycles              58148325                      
-system.cpu.decode.SquashCycles               14650540                      
-system.cpu.decode.BranchResolved            135611620                      
-system.cpu.decode.BranchMispred                   746                      
-system.cpu.decode.DecodedInsts             2037153887                      
-system.cpu.decode.SquashedInsts              52516232                      
-system.cpu.rename.SquashCycles               14650540                      
-system.cpu.rename.IdleCycles                139761664                      
-system.cpu.rename.BlockCycles               493000122                      
-system.cpu.rename.serializeStallCycles          16309                      
-system.cpu.rename.RunCycles                 837842196                      
-system.cpu.rename.UnblockCycles              90302441                      
-system.cpu.rename.RenamedInsts             1976324662                      
-system.cpu.rename.SquashedInsts              26749907                      
-system.cpu.rename.ROBFullEvents              45308958                      
-system.cpu.rename.IQFullEvents                 126668                      
-system.cpu.rename.LQFullEvents                1624936                      
-system.cpu.rename.SQFullEvents               29276583                      
-system.cpu.rename.RenamedOperands          1985726338                      
-system.cpu.rename.RenameLookups            9127758695                      
-system.cpu.rename.int_rename_lookups       2432766069                      
-system.cpu.rename.fp_rename_lookups               161                      
-system.cpu.rename.CommittedMaps            1674898945                      
-system.cpu.rename.UndoneMaps                310827393                      
-system.cpu.rename.serializingInsts                177                      
-system.cpu.rename.tempSerializingInsts            174                      
-system.cpu.rename.skidInsts                 111376144                      
-system.cpu.memDep0.insertedLoads            542477238                      
-system.cpu.memDep0.insertedStores           199268014                      
-system.cpu.memDep0.conflictingLoads          26870545                      
-system.cpu.memDep0.conflictingStores         28963209                      
-system.cpu.iq.iqInstsAdded                 1947887828                      
-system.cpu.iq.iqNonSpecInstsAdded                 229                      
-system.cpu.iq.iqInstsIssued                1857408251                      
-system.cpu.iq.iqSquashedInstsIssued          13517769                      
-system.cpu.iq.iqSquashedInstsExamined       283855640                      
-system.cpu.iq.iqSquashedOperandsExamined    647022412                      
-system.cpu.iq.iqSquashedNonSpecRemoved             59                      
-system.cpu.iq.issued_per_cycle::samples    1575573272                      
-system.cpu.iq.issued_per_cycle::mean         1.178878                      
-system.cpu.iq.issued_per_cycle::stdev        1.151815                      
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00%
-system.cpu.iq.issued_per_cycle::0           622703787     39.52%     39.52%
-system.cpu.iq.issued_per_cycle::1           326030740     20.69%     60.22%
-system.cpu.iq.issued_per_cycle::2           378156304     24.00%     84.22%
-system.cpu.iq.issued_per_cycle::3           219671219     13.94%     98.16%
-system.cpu.iq.issued_per_cycle::4            29004864      1.84%    100.00%
-system.cpu.iq.issued_per_cycle::5                6358      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::min_value            0                      
-system.cpu.iq.issued_per_cycle::max_value            5                      
-system.cpu.iq.issued_per_cycle::total      1575573272                      
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00%
-system.cpu.iq.fu_full::IntAlu               166096777     40.98%     40.98%
-system.cpu.iq.fu_full::IntMult                   2401      0.00%     40.99%
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatMisc                    0      0.00%     40.99%
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99%
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99%
-system.cpu.iq.fu_full::MemRead              191354081     47.22%     88.20%
-system.cpu.iq.fu_full::MemWrite              47812478     11.80%    100.00%
-system.cpu.iq.fu_full::FloatMemRead                19      0.00%    100.00%
-system.cpu.iq.fu_full::FloatMemWrite               28      0.00%    100.00%
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00%
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00%
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00%
-system.cpu.iq.FU_type_0::IntAlu            1138249696     61.28%     61.28%
-system.cpu.iq.FU_type_0::IntMult               803001      0.04%     61.32%
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     61.32%
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatCvt              34      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32%
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32%
-system.cpu.iq.FU_type_0::MemRead            532063614     28.65%     89.97%
-system.cpu.iq.FU_type_0::MemWrite           186291823     10.03%    100.00%
-system.cpu.iq.FU_type_0::FloatMemRead              37      0.00%    100.00%
-system.cpu.iq.FU_type_0::FloatMemWrite             24      0.00%    100.00%
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00%
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00%
-system.cpu.iq.FU_type_0::total             1857408251                      
-system.cpu.iq.rate                           1.178804                      
-system.cpu.iq.fu_busy_cnt                   405265784                      
-system.cpu.iq.fu_busy_rate                   0.218189                      
-system.cpu.iq.int_inst_queue_reads         5709173052                      
-system.cpu.iq.int_inst_queue_writes        2231756416                      
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805664221                      
-system.cpu.iq.fp_inst_queue_reads                 275                      
-system.cpu.iq.fp_inst_queue_writes                288                      
-system.cpu.iq.fp_inst_queue_wakeup_accesses           75                      
-system.cpu.iq.int_alu_accesses             2262673874                      
-system.cpu.iq.fp_alu_accesses                     161                      
-system.cpu.iew.lsq.thread0.forwLoads         17815816                      
-system.cpu.iew.lsq.thread0.invAddrLoads             0                      
-system.cpu.iew.lsq.thread0.squashedLoads     84170904                      
-system.cpu.iew.lsq.thread0.ignoredResponses        66799                      
-system.cpu.iew.lsq.thread0.memOrderViolation        13274                      
-system.cpu.iew.lsq.thread0.squashedStores     24420969                      
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                      
-system.cpu.iew.lsq.thread0.blockedLoads             0                      
-system.cpu.iew.lsq.thread0.rescheduledLoads      4535474                      
-system.cpu.iew.lsq.thread0.cacheBlocked       4852528                      
-system.cpu.iew.iewIdleCycles                        0                      
-system.cpu.iew.iewSquashCycles               14650540                      
-system.cpu.iew.iewBlockCycles                25426885                      
-system.cpu.iew.iewUnblockCycles               1470128                      
-system.cpu.iew.iewDispatchedInsts          1947888203                      
-system.cpu.iew.iewDispSquashedInsts                 0                      
-system.cpu.iew.iewDispLoadInsts             542477238                      
-system.cpu.iew.iewDispStoreInsts            199268014                      
-system.cpu.iew.iewDispNonSpecInsts                167                      
-system.cpu.iew.iewIQFullEvents                 159099                      
-system.cpu.iew.iewLSQFullEvents               1309527                      
-system.cpu.iew.memOrderViolationEvents          13274                      
-system.cpu.iew.predictedTakenIncorrect        7696809                      
-system.cpu.iew.predictedNotTakenIncorrect      8718333                      
-system.cpu.iew.branchMispredicts             16415142                      
-system.cpu.iew.iewExecutedInsts            1827780120                      
-system.cpu.iew.iewExecLoadInsts             516898840                      
-system.cpu.iew.iewExecSquashedInsts          29628131                      
-system.cpu.iew.exec_swp                             0                      
-system.cpu.iew.exec_nop                           146                      
-system.cpu.iew.exec_refs                    698650840                      
-system.cpu.iew.exec_branches                229565077                      
-system.cpu.iew.exec_stores                  181752000                      
-system.cpu.iew.exec_rate                     1.160000                      
-system.cpu.iew.wb_sent                     1808693799                      
-system.cpu.iew.wb_count                    1805664296                      
-system.cpu.iew.wb_producers                1169145221                      
-system.cpu.iew.wb_consumers                1689395973                      
-system.cpu.iew.wb_rate                       1.145965                      
-system.cpu.iew.wb_fanout                     0.692049                      
-system.cpu.commit.commitSquashedInsts       257953466                      
-system.cpu.commit.commitNonSpecStalls             170                      
-system.cpu.commit.branchMispredicts          14638116                      
-system.cpu.commit.committed_per_cycle::samples   1536081048                      
-system.cpu.commit.committed_per_cycle::mean     1.083297                      
-system.cpu.commit.committed_per_cycle::stdev     2.009309                      
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00%
-system.cpu.commit.committed_per_cycle::0    955788021     62.22%     62.22%
-system.cpu.commit.committed_per_cycle::1    250630730     16.32%     78.54%
-system.cpu.commit.committed_per_cycle::2    110093475      7.17%     85.71%
-system.cpu.commit.committed_per_cycle::3     55285008      3.60%     89.31%
-system.cpu.commit.committed_per_cycle::4     29278263      1.91%     91.21%
-system.cpu.commit.committed_per_cycle::5     34064309      2.22%     93.43%
-system.cpu.commit.committed_per_cycle::6     24750177      1.61%     95.04%
-system.cpu.commit.committed_per_cycle::7     18104449      1.18%     96.22%
-system.cpu.commit.committed_per_cycle::8     58086616      3.78%    100.00%
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00%
-system.cpu.commit.committed_per_cycle::min_value            0                      
-system.cpu.commit.committed_per_cycle::max_value            8                      
-system.cpu.commit.committed_per_cycle::total   1536081048                      
-system.cpu.commit.committedInsts           1544563042                      
-system.cpu.commit.committedOps             1664032434                      
-system.cpu.commit.swp_count                         0                      
-system.cpu.commit.refs                      633153379                      
-system.cpu.commit.loads                     458306334                      
-system.cpu.commit.membars                          62                      
-system.cpu.commit.branches                  213462427                      
-system.cpu.commit.fp_insts                         36                      
-system.cpu.commit.int_insts                1477900421                      
-system.cpu.commit.function_calls             13665177                      
-system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00%
-system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91%
-system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95%
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatMisc             0      0.00%     61.95%
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95%
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95%
-system.cpu.commit.op_class_0::MemRead       458306322     27.54%     89.49%
-system.cpu.commit.op_class_0::MemWrite      174847021     10.51%    100.00%
-system.cpu.commit.op_class_0::FloatMemRead           12      0.00%    100.00%
-system.cpu.commit.op_class_0::FloatMemWrite           24      0.00%    100.00%
-system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00%
-system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00%
-system.cpu.commit.op_class_0::total        1664032434                      
-system.cpu.commit.bw_lim_events              58086616                      
-system.cpu.rob.rob_reads                   3399979733                      
-system.cpu.rob.rob_writes                  3883469026                      
-system.cpu.timesIdled                             836                      
-system.cpu.idleCycles                           98660                      
-system.cpu.committedInsts                  1544563024                      
-system.cpu.committedOps                    1664032416                      
-system.cpu.cpi                               1.020141                      
-system.cpu.cpi_total                         1.020141                      
-system.cpu.ipc                               0.980257                      
-system.cpu.ipc_total                         0.980257                      
-system.cpu.int_regfile_reads               2175723378                      
-system.cpu.int_regfile_writes              1261531313                      
-system.cpu.fp_regfile_reads                        42                      
-system.cpu.fp_regfile_writes                       57                      
-system.cpu.cc_regfile_reads                6965468307                      
-system.cpu.cc_regfile_writes                551796531                      
-system.cpu.misc_regfile_reads               675796862                      
-system.cpu.misc_regfile_writes                    124                      
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.dcache.tags.replacements          17001793                      
-system.cpu.dcache.tags.tagsinuse           511.963908                      
-system.cpu.dcache.tags.total_refs           638014747                      
-system.cpu.dcache.tags.sampled_refs          17002305                      
-system.cpu.dcache.tags.avg_refs             37.525191                      
-system.cpu.dcache.tags.warmup_cycle          81846500                      
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.963908                      
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999930                      
-system.cpu.dcache.tags.occ_percent::total     0.999930                      
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          367                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          145                      
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                      
-system.cpu.dcache.tags.tag_accesses        1335598455                      
-system.cpu.dcache.tags.data_accesses       1335598455                      
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.dcache.ReadReq_hits::cpu.data    469297691                      
-system.cpu.dcache.ReadReq_hits::total       469297691                      
-system.cpu.dcache.WriteReq_hits::cpu.data    168716899                      
-system.cpu.dcache.WriteReq_hits::total      168716899                      
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                      
-system.cpu.dcache.LoadLockedReq_hits::total           57                      
-system.cpu.dcache.StoreCondReq_hits::cpu.data           61                      
-system.cpu.dcache.StoreCondReq_hits::total           61                      
-system.cpu.dcache.demand_hits::cpu.data     638014590                      
-system.cpu.dcache.demand_hits::total        638014590                      
-system.cpu.dcache.overall_hits::cpu.data    638014590                      
-system.cpu.dcache.overall_hits::total       638014590                      
-system.cpu.dcache.ReadReq_misses::cpu.data     17414213                      
-system.cpu.dcache.ReadReq_misses::total      17414213                      
-system.cpu.dcache.WriteReq_misses::cpu.data      3869148                      
-system.cpu.dcache.WriteReq_misses::total      3869148                      
-system.cpu.dcache.SoftPFReq_misses::cpu.data            2                      
-system.cpu.dcache.SoftPFReq_misses::total            2                      
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                      
-system.cpu.dcache.LoadLockedReq_misses::total            4                      
-system.cpu.dcache.demand_misses::cpu.data     21283361                      
-system.cpu.dcache.demand_misses::total       21283361                      
-system.cpu.dcache.overall_misses::cpu.data     21283363                      
-system.cpu.dcache.overall_misses::total      21283363                      
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000                      
-system.cpu.dcache.ReadReq_miss_latency::total 440649629000                      
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348                      
-system.cpu.dcache.WriteReq_miss_latency::total 157410000348                      
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       389500                      
-system.cpu.dcache.LoadLockedReq_miss_latency::total       389500                      
-system.cpu.dcache.demand_miss_latency::cpu.data 598059629348                      
-system.cpu.dcache.demand_miss_latency::total 598059629348                      
-system.cpu.dcache.overall_miss_latency::cpu.data 598059629348                      
-system.cpu.dcache.overall_miss_latency::total 598059629348                      
-system.cpu.dcache.ReadReq_accesses::cpu.data    486711904                      
-system.cpu.dcache.ReadReq_accesses::total    486711904                      
-system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                      
-system.cpu.dcache.WriteReq_accesses::total    172586047                      
-system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                      
-system.cpu.dcache.SoftPFReq_accesses::total            2                      
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                      
-system.cpu.dcache.LoadLockedReq_accesses::total           61                      
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                      
-system.cpu.dcache.StoreCondReq_accesses::total           61                      
-system.cpu.dcache.demand_accesses::cpu.data    659297951                      
-system.cpu.dcache.demand_accesses::total    659297951                      
-system.cpu.dcache.overall_accesses::cpu.data    659297953                      
-system.cpu.dcache.overall_accesses::total    659297953                      
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035779                      
-system.cpu.dcache.ReadReq_miss_rate::total     0.035779                      
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022419                      
-system.cpu.dcache.WriteReq_miss_rate::total     0.022419                      
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_miss_rate::total            1                      
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                      
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                      
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032282                      
-system.cpu.dcache.demand_miss_rate::total     0.032282                      
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032282                      
-system.cpu.dcache.overall_miss_rate::total     0.032282                      
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008                      
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008                      
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345                      
-system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345                      
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        97375                      
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        97375                      
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749                      
-system.cpu.dcache.demand_avg_miss_latency::total 28099.867749                      
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108                      
-system.cpu.dcache.overall_avg_miss_latency::total 28099.865108                      
-system.cpu.dcache.blocked_cycles::no_mshrs     21246265                      
-system.cpu.dcache.blocked_cycles::no_targets      3823077                      
-system.cpu.dcache.blocked::no_mshrs            940794                      
-system.cpu.dcache.blocked::no_targets           67416                      
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.583334                      
-system.cpu.dcache.avg_blocked_cycles::no_targets    56.708749                      
-system.cpu.dcache.writebacks::writebacks     17001793                      
-system.cpu.dcache.writebacks::total          17001793                      
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3149457                      
-system.cpu.dcache.ReadReq_mshr_hits::total      3149457                      
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1131591                      
-system.cpu.dcache.WriteReq_mshr_hits::total      1131591                      
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                      
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                      
-system.cpu.dcache.demand_mshr_hits::cpu.data      4281048                      
-system.cpu.dcache.demand_mshr_hits::total      4281048                      
-system.cpu.dcache.overall_mshr_hits::cpu.data      4281048                      
-system.cpu.dcache.overall_mshr_hits::total      4281048                      
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14264756                      
-system.cpu.dcache.ReadReq_mshr_misses::total     14264756                      
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737557                      
-system.cpu.dcache.WriteReq_mshr_misses::total      2737557                      
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                      
-system.cpu.dcache.demand_mshr_misses::cpu.data     17002313                      
-system.cpu.dcache.demand_mshr_misses::total     17002313                      
-system.cpu.dcache.overall_mshr_misses::cpu.data     17002314                      
-system.cpu.dcache.overall_mshr_misses::total     17002314                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143                      
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        75000                      
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        75000                      
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643                      
-system.cpu.dcache.demand_mshr_miss_latency::total 475454689643                      
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643                      
-system.cpu.dcache.overall_mshr_miss_latency::total 475454764643                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                      
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                      
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                      
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025789                      
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025789                      
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025789                      
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025789                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739                      
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        75000                      
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        75000                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922                      
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.icache.tags.replacements               591                      
-system.cpu.icache.tags.tagsinuse           443.744305                      
-system.cpu.icache.tags.total_refs           656904625                      
-system.cpu.icache.tags.sampled_refs              1075                      
-system.cpu.icache.tags.avg_refs          611074.069767                      
-system.cpu.icache.tags.warmup_cycle                 0                      
-system.cpu.icache.tags.occ_blocks::cpu.inst   443.744305                      
-system.cpu.icache.tags.occ_percent::cpu.inst     0.866688                      
-system.cpu.icache.tags.occ_percent::total     0.866688                      
-system.cpu.icache.tags.occ_task_id_blocks::1024          484                      
-system.cpu.icache.tags.age_task_id_blocks_1024::0           32                      
-system.cpu.icache.tags.age_task_id_blocks_1024::1           14                      
-system.cpu.icache.tags.age_task_id_blocks_1024::4          438                      
-system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                      
-system.cpu.icache.tags.tag_accesses        1313813517                      
-system.cpu.icache.tags.data_accesses       1313813517                      
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.icache.ReadReq_hits::cpu.inst    656904625                      
-system.cpu.icache.ReadReq_hits::total       656904625                      
-system.cpu.icache.demand_hits::cpu.inst     656904625                      
-system.cpu.icache.demand_hits::total        656904625                      
-system.cpu.icache.overall_hits::cpu.inst    656904625                      
-system.cpu.icache.overall_hits::total       656904625                      
-system.cpu.icache.ReadReq_misses::cpu.inst         1596                      
-system.cpu.icache.ReadReq_misses::total          1596                      
-system.cpu.icache.demand_misses::cpu.inst         1596                      
-system.cpu.icache.demand_misses::total           1596                      
-system.cpu.icache.overall_misses::cpu.inst         1596                      
-system.cpu.icache.overall_misses::total          1596                      
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    121940986                      
-system.cpu.icache.ReadReq_miss_latency::total    121940986                      
-system.cpu.icache.demand_miss_latency::cpu.inst    121940986                      
-system.cpu.icache.demand_miss_latency::total    121940986                      
-system.cpu.icache.overall_miss_latency::cpu.inst    121940986                      
-system.cpu.icache.overall_miss_latency::total    121940986                      
-system.cpu.icache.ReadReq_accesses::cpu.inst    656906221                      
-system.cpu.icache.ReadReq_accesses::total    656906221                      
-system.cpu.icache.demand_accesses::cpu.inst    656906221                      
-system.cpu.icache.demand_accesses::total    656906221                      
-system.cpu.icache.overall_accesses::cpu.inst    656906221                      
-system.cpu.icache.overall_accesses::total    656906221                      
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.ReadReq_miss_rate::total     0.000002                      
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.demand_miss_rate::total     0.000002                      
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.overall_miss_rate::total     0.000002                      
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566                      
-system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566                      
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566                      
-system.cpu.icache.demand_avg_miss_latency::total 76404.126566                      
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566                      
-system.cpu.icache.overall_avg_miss_latency::total 76404.126566                      
-system.cpu.icache.blocked_cycles::no_mshrs        19802                      
-system.cpu.icache.blocked_cycles::no_targets          336                      
-system.cpu.icache.blocked::no_mshrs               187                      
-system.cpu.icache.blocked::no_targets              10                      
-system.cpu.icache.avg_blocked_cycles::no_mshrs   105.893048                      
-system.cpu.icache.avg_blocked_cycles::no_targets    33.600000                      
-system.cpu.icache.writebacks::writebacks          591                      
-system.cpu.icache.writebacks::total               591                      
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          520                      
-system.cpu.icache.ReadReq_mshr_hits::total          520                      
-system.cpu.icache.demand_mshr_hits::cpu.inst          520                      
-system.cpu.icache.demand_mshr_hits::total          520                      
-system.cpu.icache.overall_mshr_hits::cpu.inst          520                      
-system.cpu.icache.overall_mshr_hits::total          520                      
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                      
-system.cpu.icache.ReadReq_mshr_misses::total         1076                      
-system.cpu.icache.demand_mshr_misses::cpu.inst         1076                      
-system.cpu.icache.demand_mshr_misses::total         1076                      
-system.cpu.icache.overall_mshr_misses::cpu.inst         1076                      
-system.cpu.icache.overall_mshr_misses::total         1076                      
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     89957490                      
-system.cpu.icache.ReadReq_mshr_miss_latency::total     89957490                      
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     89957490                      
-system.cpu.icache.demand_mshr_miss_latency::total     89957490                      
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     89957490                      
-system.cpu.icache.overall_mshr_miss_latency::total     89957490                      
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                      
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.demand_mshr_miss_rate::total     0.000002                      
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                      
-system.cpu.icache.overall_mshr_miss_rate::total     0.000002                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242                      
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242                      
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242                      
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242                      
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242                      
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.l2cache.prefetcher.num_hwpf_issued     11616550                      
-system.cpu.l2cache.prefetcher.pfIdentified     11644306                      
-system.cpu.l2cache.prefetcher.pfBufferHit        18561                      
-system.cpu.l2cache.prefetcher.pfInCache             0                      
-system.cpu.l2cache.prefetcher.pfRemovedFull            1                      
-system.cpu.l2cache.prefetcher.pfSpanPage      4655502                      
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.l2cache.tags.replacements          4647569                      
-system.cpu.l2cache.tags.tagsinuse        15870.791949                      
-system.cpu.l2cache.tags.total_refs           13265757                      
-system.cpu.l2cache.tags.sampled_refs          4663475                      
-system.cpu.l2cache.tags.avg_refs             2.844608                      
-system.cpu.l2cache.tags.warmup_cycle                0                      
-system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265                      
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   218.779684                      
-system.cpu.l2cache.tags.occ_percent::writebacks     0.955323                      
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013353                      
-system.cpu.l2cache.tags.occ_percent::total     0.968676                      
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          135                      
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15771                      
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            3                      
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          109                      
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           23                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          415                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         4017                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         7150                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2693                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1496                      
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.008240                      
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962585                      
-system.cpu.l2cache.tags.tag_accesses        561731761                      
-system.cpu.l2cache.tags.data_accesses       561731761                      
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.l2cache.WritebackDirty_hits::writebacks      4837264                      
-system.cpu.l2cache.WritebackDirty_hits::total      4837264                      
-system.cpu.l2cache.WritebackClean_hits::writebacks     12143869                      
-system.cpu.l2cache.WritebackClean_hits::total     12143869                      
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1756642                      
-system.cpu.l2cache.ReadExReq_hits::total      1756642                      
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           54                      
-system.cpu.l2cache.ReadCleanReq_hits::total           54                      
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11509702                      
-system.cpu.l2cache.ReadSharedReq_hits::total     11509702                      
-system.cpu.l2cache.demand_hits::cpu.inst           54                      
-system.cpu.l2cache.demand_hits::cpu.data     13266344                      
-system.cpu.l2cache.demand_hits::total        13266398                      
-system.cpu.l2cache.overall_hits::cpu.inst           54                      
-system.cpu.l2cache.overall_hits::cpu.data     13266344                      
-system.cpu.l2cache.overall_hits::total       13266398                      
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            9                      
-system.cpu.l2cache.UpgradeReq_misses::total            9                      
-system.cpu.l2cache.ReadExReq_misses::cpu.data       980963                      
-system.cpu.l2cache.ReadExReq_misses::total       980963                      
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1022                      
-system.cpu.l2cache.ReadCleanReq_misses::total         1022                      
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2754998                      
-system.cpu.l2cache.ReadSharedReq_misses::total      2754998                      
-system.cpu.l2cache.demand_misses::cpu.inst         1022                      
-system.cpu.l2cache.demand_misses::cpu.data      3735961                      
-system.cpu.l2cache.demand_misses::total       3736983                      
-system.cpu.l2cache.overall_misses::cpu.inst         1022                      
-system.cpu.l2cache.overall_misses::cpu.data      3735961                      
-system.cpu.l2cache.overall_misses::total      3736983                      
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       191500                      
-system.cpu.l2cache.UpgradeReq_miss_latency::total       191500                      
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104504427500                      
-system.cpu.l2cache.ReadExReq_miss_latency::total 104504427500                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     88486500                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     88486500                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000                      
-system.cpu.l2cache.demand_miss_latency::cpu.inst     88486500                      
-system.cpu.l2cache.demand_miss_latency::cpu.data 361229876500                      
-system.cpu.l2cache.demand_miss_latency::total 361318363000                      
-system.cpu.l2cache.overall_miss_latency::cpu.inst     88486500                      
-system.cpu.l2cache.overall_miss_latency::cpu.data 361229876500                      
-system.cpu.l2cache.overall_miss_latency::total 361318363000                      
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      4837264                      
-system.cpu.l2cache.WritebackDirty_accesses::total      4837264                      
-system.cpu.l2cache.WritebackClean_accesses::writebacks     12143869                      
-system.cpu.l2cache.WritebackClean_accesses::total     12143869                      
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            9                      
-system.cpu.l2cache.UpgradeReq_accesses::total            9                      
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737605                      
-system.cpu.l2cache.ReadExReq_accesses::total      2737605                      
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1076                      
-system.cpu.l2cache.ReadCleanReq_accesses::total         1076                      
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14264700                      
-system.cpu.l2cache.ReadSharedReq_accesses::total     14264700                      
-system.cpu.l2cache.demand_accesses::cpu.inst         1076                      
-system.cpu.l2cache.demand_accesses::cpu.data     17002305                      
-system.cpu.l2cache.demand_accesses::total     17003381                      
-system.cpu.l2cache.overall_accesses::cpu.inst         1076                      
-system.cpu.l2cache.overall_accesses::cpu.data     17002305                      
-system.cpu.l2cache.overall_accesses::total     17003381                      
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                      
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                      
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358329                      
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.358329                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.949814                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.949814                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.193134                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.193134                      
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.949814                      
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.219733                      
-system.cpu.l2cache.demand_miss_rate::total     0.219779                      
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.949814                      
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.219733                      
-system.cpu.l2cache.overall_miss_rate::total     0.219779                      
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778                      
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106532.486444                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106532.486444                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86581.702544                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93185.348592                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93185.348592                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86581.702544                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96689.948450                      
-system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450                      
-system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020                      
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                      
-system.cpu.l2cache.blocked_cycles::no_targets            0                      
-system.cpu.l2cache.blocked::no_mshrs                0                      
-system.cpu.l2cache.blocked::no_targets              0                      
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.l2cache.unused_prefetches            58080                      
-system.cpu.l2cache.writebacks::writebacks      1634268                      
-system.cpu.l2cache.writebacks::total          1634268                      
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3942                      
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3942                      
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                      
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                      
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45595                      
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45595                      
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                      
-system.cpu.l2cache.demand_mshr_hits::cpu.data        49537                      
-system.cpu.l2cache.demand_mshr_hits::total        49538                      
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                      
-system.cpu.l2cache.overall_mshr_hits::cpu.data        49537                      
-system.cpu.l2cache.overall_mshr_hits::total        49538                      
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1199044                      
-system.cpu.l2cache.HardPFReq_mshr_misses::total      1199044                      
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            9                      
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            9                      
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       977021                      
-system.cpu.l2cache.ReadExReq_mshr_misses::total       977021                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1021                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1021                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2709403                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2709403                      
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1021                      
-system.cpu.l2cache.demand_mshr_misses::cpu.data      3686424                      
-system.cpu.l2cache.demand_mshr_misses::total      3687445                      
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1021                      
-system.cpu.l2cache.overall_mshr_misses::cpu.data      3686424                      
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1199044                      
-system.cpu.l2cache.overall_mshr_misses::total      4886489                      
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  84363300436                      
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  84363300436                      
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       137500                      
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       137500                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  98257390500                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  98257390500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     82266500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     82266500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     82266500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000                      
-system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     82266500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  84363300436                      
-system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936                      
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                      
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                      
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                      
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356889                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356889                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.948885                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.948885                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189938                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189938                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.948885                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216819                      
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216865                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.948885                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216819                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                      
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.287383                      
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876                      
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876                      
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778                      
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956                      
-system.cpu.toL2Bus.snoop_filter.tot_requests     34005774                      
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     17002402                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21251                      
-system.cpu.toL2Bus.snoop_filter.tot_snoops       202098                      
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       202097                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                      
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.cpu.toL2Bus.trans_dist::ReadResp      14265775                      
-system.cpu.toL2Bus.trans_dist::WritebackDirty      6471532                      
-system.cpu.toL2Bus.trans_dist::WritebackClean     12165120                      
-system.cpu.toL2Bus.trans_dist::CleanEvict      3013301                      
-system.cpu.toL2Bus.trans_dist::HardPFReq      1495847                      
-system.cpu.toL2Bus.trans_dist::HardPFResp           14                      
-system.cpu.toL2Bus.trans_dist::UpgradeReq            9                      
-system.cpu.toL2Bus.trans_dist::UpgradeResp            9                      
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737605                      
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737605                      
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                      
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14264700                      
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2742                      
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51006435                      
-system.cpu.toL2Bus.pkt_count::total          51009177                      
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106624                      
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176263168                      
-system.cpu.toL2Bus.pkt_size::total         2176369792                      
-system.cpu.toL2Bus.snoops                     6143430                      
-system.cpu.toL2Bus.snoopTraffic             104594048                      
-system.cpu.toL2Bus.snoop_fanout::samples     23146806                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.009650                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.097758                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0           22923448     99.04%     99.04%
-system.cpu.toL2Bus.snoop_fanout::1             223357      0.96%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            2                      
-system.cpu.toL2Bus.snoop_fanout::total       23146806                      
-system.cpu.toL2Bus.reqLayer0.occupancy    34005271029                      
-system.cpu.toL2Bus.reqLayer0.utilization          4.3                      
-system.cpu.toL2Bus.snoopLayer0.occupancy        21045                      
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                      
-system.cpu.toL2Bus.respLayer0.occupancy       1613498                      
-system.cpu.toL2Bus.respLayer0.utilization          0.0                      
-system.cpu.toL2Bus.respLayer1.occupancy   25503465992                      
-system.cpu.toL2Bus.respLayer1.utilization          3.2                      
-system.membus.snoop_filter.tot_requests       9333292                      
-system.membus.snoop_filter.hit_single_requests      4668829                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500                      
-system.membus.trans_dist::ReadResp            3708542                      
-system.membus.trans_dist::WritebackDirty      1634268                      
-system.membus.trans_dist::CleanEvict          3013301                      
-system.membus.trans_dist::UpgradeReq                9                      
-system.membus.trans_dist::ReadExReq            977171                      
-system.membus.trans_dist::ReadExResp           977171                      
-system.membus.trans_dist::ReadSharedReq       3708543                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14019005                      
-system.membus.pkt_count::total               14019005                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    404478784                      
-system.membus.pkt_size::total               404478784                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples           4685723                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                 4685723    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total             4685723                      
-system.membus.reqLayer0.occupancy         17639856241                      
-system.membus.reqLayer0.utilization               2.2                      
-system.membus.respLayer1.occupancy        25447920698                      
-system.membus.respLayer1.utilization              3.2                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
deleted file mode 100644 (file)
index 36301b9..0000000
+++ /dev/null
@@ -1,330 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
deleted file mode 100755 (executable)
index 43d7005..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
deleted file mode 100755 (executable)
index 61d9889..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 17:55:48
-gem5 started Apr  3 2017 18:15:54
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57397
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 832017490500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
deleted file mode 100644 (file)
index 5e4ef20..0000000
+++ /dev/null
@@ -1,262 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.832017                      
-sim_ticks                                832017490500                      
-final_tick                               832017490500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 917891                      
-host_op_rate                                   988888                      
-host_tick_rate                              494444669                      
-host_mem_usage                                 271524                      
-host_seconds                                  1682.73                      
-sim_insts                                  1544563042                      
-sim_ops                                    1664032434                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.physmem.bytes_read::cpu.inst        6178262360                      
-system.physmem.bytes_read::cpu.data        1581387671                      
-system.physmem.bytes_read::total           7759650031                      
-system.physmem.bytes_inst_read::cpu.inst   6178262360                      
-system.physmem.bytes_inst_read::total      6178262360                      
-system.physmem.bytes_written::cpu.data      624158392                      
-system.physmem.bytes_written::total         624158392                      
-system.physmem.num_reads::cpu.inst         1544565590                      
-system.physmem.num_reads::cpu.data          454909197                      
-system.physmem.num_reads::total            1999474787                      
-system.physmem.num_writes::cpu.data         172586108                      
-system.physmem.num_writes::total            172586108                      
-system.physmem.bw_read::cpu.inst           7425640002                      
-system.physmem.bw_read::cpu.data           1900666379                      
-system.physmem.bw_read::total              9326306381                      
-system.physmem.bw_inst_read::cpu.inst      7425640002                      
-system.physmem.bw_inst_read::total         7425640002                      
-system.physmem.bw_write::cpu.data           750174605                      
-system.physmem.bw_write::total              750174605                      
-system.physmem.bw_total::cpu.inst          7425640002                      
-system.physmem.bw_total::cpu.data          2650840984                      
-system.physmem.bw_total::total            10076480986                      
-system.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.hits              0                      
-system.cpu.istage2_mmu.stage2_tlb.misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.cpu.itb.walker.walks                         0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.itb.walker.walkRequestOrigin::total            0                      
-system.cpu.itb.inst_hits                            0                      
-system.cpu.itb.inst_misses                          0                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.flush_tlb                            0                      
-system.cpu.itb.flush_tlb_mva                        0                      
-system.cpu.itb.flush_tlb_mva_asid                   0                      
-system.cpu.itb.flush_tlb_asid                       0                      
-system.cpu.itb.flush_entries                        0                      
-system.cpu.itb.align_faults                         0                      
-system.cpu.itb.prefetch_faults                      0                      
-system.cpu.itb.domain_faults                        0                      
-system.cpu.itb.perms_faults                         0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.inst_accesses                        0                      
-system.cpu.itb.hits                                 0                      
-system.cpu.itb.misses                               0                      
-system.cpu.itb.accesses                             0                      
-system.cpu.workload.numSyscalls                    46                      
-system.cpu.pwrStateResidencyTicks::ON    832017490500                      
-system.cpu.numCycles                       1664034982                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                  1544563042                      
-system.cpu.committedOps                    1664032434                      
-system.cpu.num_int_alu_accesses            1477900422                      
-system.cpu.num_fp_alu_accesses                     36                      
-system.cpu.num_func_calls                    27330256                      
-system.cpu.num_conditional_control_insts    167612489                      
-system.cpu.num_int_insts                   1477900422                      
-system.cpu.num_fp_insts                            36                      
-system.cpu.num_int_register_reads          2605402867                      
-system.cpu.num_int_register_writes         1125475224                      
-system.cpu.num_fp_register_reads                   24                      
-system.cpu.num_fp_register_writes                  16                      
-system.cpu.num_cc_register_reads           4992096239                      
-system.cpu.num_cc_register_writes           518236214                      
-system.cpu.num_mem_refs                     633153380                      
-system.cpu.num_load_insts                   458306334                      
-system.cpu.num_store_insts                  174847046                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                 1664034982                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         213462427                      
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
-system.cpu.op_class::IntAlu                1030178776     61.91%     61.91%
-system.cpu.op_class::IntMult                   700322      0.04%     61.95%
-system.cpu.op_class::IntDiv                         0      0.00%     61.95%
-system.cpu.op_class::FloatAdd                       0      0.00%     61.95%
-system.cpu.op_class::FloatCmp                       0      0.00%     61.95%
-system.cpu.op_class::FloatCvt                       0      0.00%     61.95%
-system.cpu.op_class::FloatMult                      0      0.00%     61.95%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     61.95%
-system.cpu.op_class::FloatDiv                       0      0.00%     61.95%
-system.cpu.op_class::FloatMisc                      0      0.00%     61.95%
-system.cpu.op_class::FloatSqrt                      0      0.00%     61.95%
-system.cpu.op_class::SimdAdd                        0      0.00%     61.95%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     61.95%
-system.cpu.op_class::SimdAlu                        0      0.00%     61.95%
-system.cpu.op_class::SimdCmp                        0      0.00%     61.95%
-system.cpu.op_class::SimdCvt                        0      0.00%     61.95%
-system.cpu.op_class::SimdMisc                       0      0.00%     61.95%
-system.cpu.op_class::SimdMult                       0      0.00%     61.95%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     61.95%
-system.cpu.op_class::SimdShift                      0      0.00%     61.95%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.95%
-system.cpu.op_class::SimdSqrt                       0      0.00%     61.95%
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.95%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     61.95%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.95%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.95%
-system.cpu.op_class::MemRead                458306322     27.54%     89.49%
-system.cpu.op_class::MemWrite               174847022     10.51%    100.00%
-system.cpu.op_class::FloatMemRead                  12      0.00%    100.00%
-system.cpu.op_class::FloatMemWrite                 24      0.00%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                 1664032481                      
-system.membus.snoop_filter.tot_requests             0                      
-system.membus.snoop_filter.hit_single_requests            0                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500                      
-system.membus.trans_dist::ReadReq          1999474725                      
-system.membus.trans_dist::ReadResp         1999474786                      
-system.membus.trans_dist::WriteReq          172586047                      
-system.membus.trans_dist::WriteResp         172586047                      
-system.membus.trans_dist::SoftPFReq                 1                      
-system.membus.trans_dist::SoftPFResp                1                      
-system.membus.trans_dist::LoadLockedReq            61                      
-system.membus.trans_dist::StoreCondReq             61                      
-system.membus.trans_dist::StoreCondResp            61                      
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   3089131180                      
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port   1254990610                      
-system.membus.pkt_count::total             4344121790                      
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   6178262360                      
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   2205546063                      
-system.membus.pkt_size::total              8383808423                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples        2172060895                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0              2172060895    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total          2172060895                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
deleted file mode 100644 (file)
index c5f8c8e..0000000
+++ /dev/null
@@ -1,499 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
deleted file mode 100755 (executable)
index 43d7005..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
deleted file mode 100755 (executable)
index 3fe7451..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 17:55:48
-gem5 started Apr  3 2017 17:57:50
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54313
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 2379921906500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
deleted file mode 100644 (file)
index fd3a813..0000000
+++ /dev/null
@@ -1,682 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.379922                      
-sim_ticks                                2379921906500                      
-final_tick                               2379921906500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 663470                      
-host_op_rate                                   714982                      
-host_tick_rate                             1026156085                      
-host_mem_usage                                 282544                      
-host_seconds                                  2319.26                      
-sim_insts                                  1538759602                      
-sim_ops                                    1658228915                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.physmem.bytes_read::cpu.inst             39424                      
-system.physmem.bytes_read::cpu.data         126077056                      
-system.physmem.bytes_read::total            126116480                      
-system.physmem.bytes_inst_read::cpu.inst        39424                      
-system.physmem.bytes_inst_read::total           39424                      
-system.physmem.bytes_written::writebacks     66029376                      
-system.physmem.bytes_written::total          66029376                      
-system.physmem.num_reads::cpu.inst                616                      
-system.physmem.num_reads::cpu.data            1969954                      
-system.physmem.num_reads::total               1970570                      
-system.physmem.num_writes::writebacks         1031709                      
-system.physmem.num_writes::total              1031709                      
-system.physmem.bw_read::cpu.inst                16565                      
-system.physmem.bw_read::cpu.data             52975291                      
-system.physmem.bw_read::total                52991856                      
-system.physmem.bw_inst_read::cpu.inst           16565                      
-system.physmem.bw_inst_read::total              16565                      
-system.physmem.bw_write::writebacks          27744346                      
-system.physmem.bw_write::total               27744346                      
-system.physmem.bw_total::writebacks          27744346                      
-system.physmem.bw_total::cpu.inst               16565                      
-system.physmem.bw_total::cpu.data            52975291                      
-system.physmem.bw_total::total               80736202                      
-system.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.hits              0                      
-system.cpu.istage2_mmu.stage2_tlb.misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.itb.walker.walks                         0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.itb.walker.walkRequestOrigin::total            0                      
-system.cpu.itb.inst_hits                            0                      
-system.cpu.itb.inst_misses                          0                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.flush_tlb                            0                      
-system.cpu.itb.flush_tlb_mva                        0                      
-system.cpu.itb.flush_tlb_mva_asid                   0                      
-system.cpu.itb.flush_tlb_asid                       0                      
-system.cpu.itb.flush_entries                        0                      
-system.cpu.itb.align_faults                         0                      
-system.cpu.itb.prefetch_faults                      0                      
-system.cpu.itb.domain_faults                        0                      
-system.cpu.itb.perms_faults                         0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.inst_accesses                        0                      
-system.cpu.itb.hits                                 0                      
-system.cpu.itb.misses                               0                      
-system.cpu.itb.accesses                             0                      
-system.cpu.workload.numSyscalls                    46                      
-system.cpu.pwrStateResidencyTicks::ON    2379921906500                      
-system.cpu.numCycles                       4759843813                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                  1538759602                      
-system.cpu.committedOps                    1658228915                      
-system.cpu.num_int_alu_accesses            1477900422                      
-system.cpu.num_fp_alu_accesses                     36                      
-system.cpu.num_func_calls                    27330256                      
-system.cpu.num_conditional_control_insts    167612489                      
-system.cpu.num_int_insts                   1477900422                      
-system.cpu.num_fp_insts                            36                      
-system.cpu.num_int_register_reads          2601860297                      
-system.cpu.num_int_register_writes         1125475224                      
-system.cpu.num_fp_register_reads                   24                      
-system.cpu.num_fp_register_writes                  16                      
-system.cpu.num_cc_register_reads           6356387678                      
-system.cpu.num_cc_register_writes           518236214                      
-system.cpu.num_mem_refs                     633153380                      
-system.cpu.num_load_insts                   458306334                      
-system.cpu.num_store_insts                  174847046                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                 4759843813                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         213462427                      
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
-system.cpu.op_class::IntAlu                1030178776     61.91%     61.91%
-system.cpu.op_class::IntMult                   700322      0.04%     61.95%
-system.cpu.op_class::IntDiv                         0      0.00%     61.95%
-system.cpu.op_class::FloatAdd                       0      0.00%     61.95%
-system.cpu.op_class::FloatCmp                       0      0.00%     61.95%
-system.cpu.op_class::FloatCvt                       0      0.00%     61.95%
-system.cpu.op_class::FloatMult                      0      0.00%     61.95%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     61.95%
-system.cpu.op_class::FloatDiv                       0      0.00%     61.95%
-system.cpu.op_class::FloatMisc                      0      0.00%     61.95%
-system.cpu.op_class::FloatSqrt                      0      0.00%     61.95%
-system.cpu.op_class::SimdAdd                        0      0.00%     61.95%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     61.95%
-system.cpu.op_class::SimdAlu                        0      0.00%     61.95%
-system.cpu.op_class::SimdCmp                        0      0.00%     61.95%
-system.cpu.op_class::SimdCvt                        0      0.00%     61.95%
-system.cpu.op_class::SimdMisc                       0      0.00%     61.95%
-system.cpu.op_class::SimdMult                       0      0.00%     61.95%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     61.95%
-system.cpu.op_class::SimdShift                      0      0.00%     61.95%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.95%
-system.cpu.op_class::SimdSqrt                       0      0.00%     61.95%
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.95%
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.95%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     61.95%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.95%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.95%
-system.cpu.op_class::MemRead                458306322     27.54%     89.49%
-system.cpu.op_class::MemWrite               174847022     10.51%    100.00%
-system.cpu.op_class::FloatMemRead                  12      0.00%    100.00%
-system.cpu.op_class::FloatMemWrite                 24      0.00%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                 1664032481                      
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.dcache.tags.replacements           9111140                      
-system.cpu.dcache.tags.tagsinuse          4083.747199                      
-system.cpu.dcache.tags.total_refs           618380069                      
-system.cpu.dcache.tags.sampled_refs           9115236                      
-system.cpu.dcache.tags.avg_refs             67.840270                      
-system.cpu.dcache.tags.warmup_cycle       25232837500                      
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.747199                      
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997009                      
-system.cpu.dcache.tags.occ_percent::total     0.997009                      
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          151                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1149                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2648                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          147                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                      
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                      
-system.cpu.dcache.tags.tag_accesses        1264105846                      
-system.cpu.dcache.tags.data_accesses       1264105846                      
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.dcache.ReadReq_hits::cpu.data    447683049                      
-system.cpu.dcache.ReadReq_hits::total       447683049                      
-system.cpu.dcache.WriteReq_hits::cpu.data    170696898                      
-system.cpu.dcache.WriteReq_hits::total      170696898                      
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                      
-system.cpu.dcache.LoadLockedReq_hits::total           61                      
-system.cpu.dcache.StoreCondReq_hits::cpu.data           61                      
-system.cpu.dcache.StoreCondReq_hits::total           61                      
-system.cpu.dcache.demand_hits::cpu.data     618379947                      
-system.cpu.dcache.demand_hits::total        618379947                      
-system.cpu.dcache.overall_hits::cpu.data    618379947                      
-system.cpu.dcache.overall_hits::total       618379947                      
-system.cpu.dcache.ReadReq_misses::cpu.data      7226086                      
-system.cpu.dcache.ReadReq_misses::total       7226086                      
-system.cpu.dcache.WriteReq_misses::cpu.data      1889149                      
-system.cpu.dcache.WriteReq_misses::total      1889149                      
-system.cpu.dcache.SoftPFReq_misses::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_misses::total            1                      
-system.cpu.dcache.demand_misses::cpu.data      9115235                      
-system.cpu.dcache.demand_misses::total        9115235                      
-system.cpu.dcache.overall_misses::cpu.data      9115236                      
-system.cpu.dcache.overall_misses::total       9115236                      
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500                      
-system.cpu.dcache.ReadReq_miss_latency::total 152766688500                      
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  64243803000                      
-system.cpu.dcache.WriteReq_miss_latency::total  64243803000                      
-system.cpu.dcache.demand_miss_latency::cpu.data 217010491500                      
-system.cpu.dcache.demand_miss_latency::total 217010491500                      
-system.cpu.dcache.overall_miss_latency::cpu.data 217010491500                      
-system.cpu.dcache.overall_miss_latency::total 217010491500                      
-system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                      
-system.cpu.dcache.ReadReq_accesses::total    454909135                      
-system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                      
-system.cpu.dcache.WriteReq_accesses::total    172586047                      
-system.cpu.dcache.SoftPFReq_accesses::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_accesses::total            1                      
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                      
-system.cpu.dcache.LoadLockedReq_accesses::total           61                      
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                      
-system.cpu.dcache.StoreCondReq_accesses::total           61                      
-system.cpu.dcache.demand_accesses::cpu.data    627495182                      
-system.cpu.dcache.demand_accesses::total    627495182                      
-system.cpu.dcache.overall_accesses::cpu.data    627495183                      
-system.cpu.dcache.overall_accesses::total    627495183                      
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015885                      
-system.cpu.dcache.ReadReq_miss_rate::total     0.015885                      
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                      
-system.cpu.dcache.WriteReq_miss_rate::total     0.010946                      
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_miss_rate::total            1                      
-system.cpu.dcache.demand_miss_rate::cpu.data     0.014526                      
-system.cpu.dcache.demand_miss_rate::total     0.014526                      
-system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                      
-system.cpu.dcache.overall_miss_rate::total     0.014526                      
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605                      
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605                      
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189                      
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189                      
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903                      
-system.cpu.dcache.demand_avg_miss_latency::total 23807.448903                      
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291                      
-system.cpu.dcache.overall_avg_miss_latency::total 23807.446291                      
-system.cpu.dcache.blocked_cycles::no_mshrs            0                      
-system.cpu.dcache.blocked_cycles::no_targets            0                      
-system.cpu.dcache.blocked::no_mshrs                 0                      
-system.cpu.dcache.blocked::no_targets               0                      
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.dcache.writebacks::writebacks      3667054                      
-system.cpu.dcache.writebacks::total           3667054                      
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                      
-system.cpu.dcache.ReadReq_mshr_misses::total      7226086                      
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                      
-system.cpu.dcache.WriteReq_mshr_misses::total      1889149                      
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                      
-system.cpu.dcache.demand_mshr_misses::cpu.data      9115235                      
-system.cpu.dcache.demand_mshr_misses::total      9115235                      
-system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                      
-system.cpu.dcache.overall_mshr_misses::total      9115236                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  62354654000                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  62354654000                      
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        62000                      
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        62000                      
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500                      
-system.cpu.dcache.demand_mshr_miss_latency::total 207895256500                      
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500                      
-system.cpu.dcache.overall_mshr_miss_latency::total 207895318500                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010946                      
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data            1                      
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total            1                      
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526                      
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                      
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                      
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189                      
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        62000                      
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        62000                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203                      
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.icache.tags.replacements                 7                      
-system.cpu.icache.tags.tagsinuse           515.169434                      
-system.cpu.icache.tags.total_refs          1544564953                      
-system.cpu.icache.tags.sampled_refs               638                      
-system.cpu.icache.tags.avg_refs          2420948.202194                      
-system.cpu.icache.tags.warmup_cycle                 0                      
-system.cpu.icache.tags.occ_blocks::cpu.inst   515.169434                      
-system.cpu.icache.tags.occ_percent::cpu.inst     0.251548                      
-system.cpu.icache.tags.occ_percent::total     0.251548                      
-system.cpu.icache.tags.occ_task_id_blocks::1024          631                      
-system.cpu.icache.tags.age_task_id_blocks_1024::0           24                      
-system.cpu.icache.tags.age_task_id_blocks_1024::2            1                      
-system.cpu.icache.tags.age_task_id_blocks_1024::4          606                      
-system.cpu.icache.tags.occ_task_id_percent::1024     0.308105                      
-system.cpu.icache.tags.tag_accesses        3089131820                      
-system.cpu.icache.tags.data_accesses       3089131820                      
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.icache.ReadReq_hits::cpu.inst   1544564953                      
-system.cpu.icache.ReadReq_hits::total      1544564953                      
-system.cpu.icache.demand_hits::cpu.inst    1544564953                      
-system.cpu.icache.demand_hits::total       1544564953                      
-system.cpu.icache.overall_hits::cpu.inst   1544564953                      
-system.cpu.icache.overall_hits::total      1544564953                      
-system.cpu.icache.ReadReq_misses::cpu.inst          638                      
-system.cpu.icache.ReadReq_misses::total           638                      
-system.cpu.icache.demand_misses::cpu.inst          638                      
-system.cpu.icache.demand_misses::total            638                      
-system.cpu.icache.overall_misses::cpu.inst          638                      
-system.cpu.icache.overall_misses::total           638                      
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     39132000                      
-system.cpu.icache.ReadReq_miss_latency::total     39132000                      
-system.cpu.icache.demand_miss_latency::cpu.inst     39132000                      
-system.cpu.icache.demand_miss_latency::total     39132000                      
-system.cpu.icache.overall_miss_latency::cpu.inst     39132000                      
-system.cpu.icache.overall_miss_latency::total     39132000                      
-system.cpu.icache.ReadReq_accesses::cpu.inst   1544565591                      
-system.cpu.icache.ReadReq_accesses::total   1544565591                      
-system.cpu.icache.demand_accesses::cpu.inst   1544565591                      
-system.cpu.icache.demand_accesses::total   1544565591                      
-system.cpu.icache.overall_accesses::cpu.inst   1544565591                      
-system.cpu.icache.overall_accesses::total   1544565591                      
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.ReadReq_miss_rate::total     0.000000                      
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.demand_miss_rate::total     0.000000                      
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.overall_miss_rate::total     0.000000                      
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197                      
-system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197                      
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197                      
-system.cpu.icache.demand_avg_miss_latency::total 61335.423197                      
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197                      
-system.cpu.icache.overall_avg_miss_latency::total 61335.423197                      
-system.cpu.icache.blocked_cycles::no_mshrs            0                      
-system.cpu.icache.blocked_cycles::no_targets            0                      
-system.cpu.icache.blocked::no_mshrs                 0                      
-system.cpu.icache.blocked::no_targets               0                      
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.icache.writebacks::writebacks            7                      
-system.cpu.icache.writebacks::total                 7                      
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                      
-system.cpu.icache.ReadReq_mshr_misses::total          638                      
-system.cpu.icache.demand_mshr_misses::cpu.inst          638                      
-system.cpu.icache.demand_mshr_misses::total          638                      
-system.cpu.icache.overall_mshr_misses::cpu.inst          638                      
-system.cpu.icache.overall_mshr_misses::total          638                      
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38494000                      
-system.cpu.icache.ReadReq_mshr_miss_latency::total     38494000                      
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38494000                      
-system.cpu.icache.demand_mshr_miss_latency::total     38494000                      
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38494000                      
-system.cpu.icache.overall_mshr_miss_latency::total     38494000                      
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.demand_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.overall_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197                      
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197                      
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197                      
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197                      
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197                      
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.l2cache.tags.replacements          1938113                      
-system.cpu.l2cache.tags.tagsinuse        31679.342131                      
-system.cpu.l2cache.tags.total_refs           16254769                      
-system.cpu.l2cache.tags.sampled_refs          1970881                      
-system.cpu.l2cache.tags.avg_refs             8.247463                      
-system.cpu.l2cache.tags.warmup_cycle     138952277000                      
-system.cpu.l2cache.tags.occ_blocks::writebacks    10.111234                      
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.251326                      
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571                      
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000309                      
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000710                      
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.965759                      
-system.cpu.l2cache.tags.occ_percent::total     0.966777                      
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          744                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2874                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1739                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27370                      
-system.cpu.l2cache.tags.occ_task_id_percent::1024            1                      
-system.cpu.l2cache.tags.tag_accesses        147777841                      
-system.cpu.l2cache.tags.data_accesses       147777841                      
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3667054                      
-system.cpu.l2cache.WritebackDirty_hits::total      3667054                      
-system.cpu.l2cache.WritebackClean_hits::writebacks            7                      
-system.cpu.l2cache.WritebackClean_hits::total            7                      
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1095453                      
-system.cpu.l2cache.ReadExReq_hits::total      1095453                      
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           22                      
-system.cpu.l2cache.ReadCleanReq_hits::total           22                      
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6049829                      
-system.cpu.l2cache.ReadSharedReq_hits::total      6049829                      
-system.cpu.l2cache.demand_hits::cpu.inst           22                      
-system.cpu.l2cache.demand_hits::cpu.data      7145282                      
-system.cpu.l2cache.demand_hits::total         7145304                      
-system.cpu.l2cache.overall_hits::cpu.inst           22                      
-system.cpu.l2cache.overall_hits::cpu.data      7145282                      
-system.cpu.l2cache.overall_hits::total        7145304                      
-system.cpu.l2cache.ReadExReq_misses::cpu.data       793696                      
-system.cpu.l2cache.ReadExReq_misses::total       793696                      
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          616                      
-system.cpu.l2cache.ReadCleanReq_misses::total          616                      
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1176258                      
-system.cpu.l2cache.ReadSharedReq_misses::total      1176258                      
-system.cpu.l2cache.demand_misses::cpu.inst          616                      
-system.cpu.l2cache.demand_misses::cpu.data      1969954                      
-system.cpu.l2cache.demand_misses::total       1970570                      
-system.cpu.l2cache.overall_misses::cpu.inst          616                      
-system.cpu.l2cache.overall_misses::cpu.data      1969954                      
-system.cpu.l2cache.overall_misses::total      1970570                      
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  48018674000                      
-system.cpu.l2cache.ReadExReq_miss_latency::total  48018674000                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     37281000                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     37281000                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  71177285500                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  71177285500                      
-system.cpu.l2cache.demand_miss_latency::cpu.inst     37281000                      
-system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500                      
-system.cpu.l2cache.demand_miss_latency::total 119233240500                      
-system.cpu.l2cache.overall_miss_latency::cpu.inst     37281000                      
-system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500                      
-system.cpu.l2cache.overall_miss_latency::total 119233240500                      
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3667054                      
-system.cpu.l2cache.WritebackDirty_accesses::total      3667054                      
-system.cpu.l2cache.WritebackClean_accesses::writebacks            7                      
-system.cpu.l2cache.WritebackClean_accesses::total            7                      
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889149                      
-system.cpu.l2cache.ReadExReq_accesses::total      1889149                      
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          638                      
-system.cpu.l2cache.ReadCleanReq_accesses::total          638                      
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7226087                      
-system.cpu.l2cache.ReadSharedReq_accesses::total      7226087                      
-system.cpu.l2cache.demand_accesses::cpu.inst          638                      
-system.cpu.l2cache.demand_accesses::cpu.data      9115236                      
-system.cpu.l2cache.demand_accesses::total      9115874                      
-system.cpu.l2cache.overall_accesses::cpu.inst          638                      
-system.cpu.l2cache.overall_accesses::cpu.data      9115236                      
-system.cpu.l2cache.overall_accesses::total      9115874                      
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.420134                      
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.420134                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.965517                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162779                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162779                      
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.216117                      
-system.cpu.l2cache.demand_miss_rate::total     0.216169                      
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.216117                      
-system.cpu.l2cache.overall_miss_rate::total     0.216169                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051                      
-system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051                      
-system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468                      
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                      
-system.cpu.l2cache.blocked_cycles::no_targets            0                      
-system.cpu.l2cache.blocked::no_mshrs                0                      
-system.cpu.l2cache.blocked::no_targets              0                      
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.l2cache.writebacks::writebacks      1031709                      
-system.cpu.l2cache.writebacks::total          1031709                      
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          220                      
-system.cpu.l2cache.CleanEvict_mshr_misses::total          220                      
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       793696                      
-system.cpu.l2cache.ReadExReq_mshr_misses::total       793696                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          616                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          616                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1176258                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1176258                      
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                      
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1969954                      
-system.cpu.l2cache.demand_mshr_misses::total      1970570                      
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                      
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1969954                      
-system.cpu.l2cache.overall_mshr_misses::total      1970570                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  40081714000                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  40081714000                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     31121000                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     31121000                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  59414705500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  59414705500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31121000                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  99496419500                      
-system.cpu.l2cache.demand_mshr_miss_latency::total  99527540500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31121000                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  99496419500                      
-system.cpu.l2cache.overall_mshr_miss_latency::total  99527540500                      
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                      
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.420134                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.420134                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965517                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162779                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162779                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216117                      
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216169                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216117                      
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.216169                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468                      
-system.cpu.toL2Bus.snoop_filter.tot_requests     18227021                      
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9111154                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1151                      
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1220                      
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1220                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                      
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.cpu.toL2Bus.trans_dist::ReadResp       7226725                      
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4698763                      
-system.cpu.toL2Bus.trans_dist::WritebackClean            7                      
-system.cpu.toL2Bus.trans_dist::CleanEvict      6350490                      
-system.cpu.toL2Bus.trans_dist::ReadExReq      1889149                      
-system.cpu.toL2Bus.trans_dist::ReadExResp      1889149                      
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          638                      
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7226087                      
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1283                      
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27341612                      
-system.cpu.toL2Bus.pkt_count::total          27342895                      
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        41280                      
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818066560                      
-system.cpu.toL2Bus.pkt_size::total          818107840                      
-system.cpu.toL2Bus.snoops                     1938113                      
-system.cpu.toL2Bus.snoopTraffic              66029376                      
-system.cpu.toL2Bus.snoop_fanout::samples     11053987                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.000215                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.014666                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0           11051609     99.98%     99.98%
-system.cpu.toL2Bus.snoop_fanout::1               2378      0.02%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            1                      
-system.cpu.toL2Bus.snoop_fanout::total       11053987                      
-system.cpu.toL2Bus.reqLayer0.occupancy    12780571500                      
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                      
-system.cpu.toL2Bus.respLayer0.occupancy        957000                      
-system.cpu.toL2Bus.respLayer0.utilization          0.0                      
-system.cpu.toL2Bus.respLayer1.occupancy   13672854000                      
-system.cpu.toL2Bus.respLayer1.utilization          0.6                      
-system.membus.snoop_filter.tot_requests       3907683                      
-system.membus.snoop_filter.hit_single_requests      1937205                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500                      
-system.membus.trans_dist::ReadResp            1176874                      
-system.membus.trans_dist::WritebackDirty      1031709                      
-system.membus.trans_dist::CleanEvict           905404                      
-system.membus.trans_dist::ReadExReq            793696                      
-system.membus.trans_dist::ReadExResp           793696                      
-system.membus.trans_dist::ReadSharedReq       1176874                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5878253                      
-system.membus.pkt_count::total                5878253                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192145856                      
-system.membus.pkt_size::total               192145856                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples           1970570                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                 1970570    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total             1970570                      
-system.membus.reqLayer0.occupancy          8048170000                      
-system.membus.reqLayer0.utilization               0.3                      
-system.membus.respLayer1.occupancy         9852850000                      
-system.membus.respLayer1.utilization              0.4                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
deleted file mode 100644 (file)
index 2dc4933..0000000
+++ /dev/null
@@ -1,263 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[5]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=bzip2 input.source 1
-cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
deleted file mode 100755 (executable)
index 43d7005..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
deleted file mode 100755 (executable)
index c93c64d..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 19:05:53
-gem5 started Apr  3 2017 19:06:24
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 2846007227500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
deleted file mode 100644 (file)
index 3d3e070..0000000
+++ /dev/null
@@ -1,145 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.846007                      
-sim_ticks                                2846007227500                      
-final_tick                               2846007227500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 877028                      
-host_op_rate                                  1366490                      
-host_tick_rate                              829774485                      
-host_mem_usage                                 274188                      
-host_seconds                                  3429.86                      
-sim_insts                                  3008081022                      
-sim_ops                                    4686862596                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.physmem.bytes_read::cpu.inst       32105863056                      
-system.physmem.bytes_read::cpu.data        5023868345                      
-system.physmem.bytes_read::total          37129731401                      
-system.physmem.bytes_inst_read::cpu.inst  32105863056                      
-system.physmem.bytes_inst_read::total     32105863056                      
-system.physmem.bytes_written::cpu.data     1544656792                      
-system.physmem.bytes_written::total        1544656792                      
-system.physmem.num_reads::cpu.inst         4013232882                      
-system.physmem.num_reads::cpu.data         1239184746                      
-system.physmem.num_reads::total            5252417628                      
-system.physmem.num_writes::cpu.data         438528338                      
-system.physmem.num_writes::total            438528338                      
-system.physmem.bw_read::cpu.inst          11281019509                      
-system.physmem.bw_read::cpu.data           1765233867                      
-system.physmem.bw_read::total             13046253376                      
-system.physmem.bw_inst_read::cpu.inst     11281019509                      
-system.physmem.bw_inst_read::total        11281019509                      
-system.physmem.bw_write::cpu.data           542745211                      
-system.physmem.bw_write::total              542745211                      
-system.physmem.bw_total::cpu.inst         11281019509                      
-system.physmem.bw_total::cpu.data          2307979078                      
-system.physmem.bw_total::total            13588998587                      
-system.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.cpu.apic_clk_domain.clock                 8000                      
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.cpu.workload.numSyscalls                    46                      
-system.cpu.pwrStateResidencyTicks::ON    2846007227500                      
-system.cpu.numCycles                       5692014456                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                  3008081022                      
-system.cpu.committedOps                    4686862596                      
-system.cpu.num_int_alu_accesses            4684368009                      
-system.cpu.num_fp_alu_accesses                      0                      
-system.cpu.num_func_calls                    33534539                      
-system.cpu.num_conditional_control_insts    182173300                      
-system.cpu.num_int_insts                   4684368009                      
-system.cpu.num_fp_insts                             0                      
-system.cpu.num_int_register_reads         10688755601                      
-system.cpu.num_int_register_writes         3999841477                      
-system.cpu.num_fp_register_reads                    0                      
-system.cpu.num_fp_register_writes                   0                      
-system.cpu.num_cc_register_reads           1226718827                      
-system.cpu.num_cc_register_writes          1355930461                      
-system.cpu.num_mem_refs                    1677713084                      
-system.cpu.num_load_insts                  1239184746                      
-system.cpu.num_store_insts                  438528338                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                 5692014456                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         248500691                      
-system.cpu.op_class::No_OpClass               2494522      0.05%      0.05%
-system.cpu.op_class::IntAlu                3006647871     64.15%     64.20%
-system.cpu.op_class::IntMult                     6215      0.00%     64.20%
-system.cpu.op_class::IntDiv                       904      0.00%     64.20%
-system.cpu.op_class::FloatAdd                       0      0.00%     64.20%
-system.cpu.op_class::FloatCmp                       0      0.00%     64.20%
-system.cpu.op_class::FloatCvt                       0      0.00%     64.20%
-system.cpu.op_class::FloatMult                      0      0.00%     64.20%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     64.20%
-system.cpu.op_class::FloatDiv                       0      0.00%     64.20%
-system.cpu.op_class::FloatMisc                      0      0.00%     64.20%
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.20%
-system.cpu.op_class::SimdAdd                        0      0.00%     64.20%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.20%
-system.cpu.op_class::SimdAlu                        0      0.00%     64.20%
-system.cpu.op_class::SimdCmp                        0      0.00%     64.20%
-system.cpu.op_class::SimdCvt                        0      0.00%     64.20%
-system.cpu.op_class::SimdMisc                       0      0.00%     64.20%
-system.cpu.op_class::SimdMult                       0      0.00%     64.20%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.20%
-system.cpu.op_class::SimdShift                      0      0.00%     64.20%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.20%
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.20%
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.20%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.20%
-system.cpu.op_class::MemRead               1239184746     26.44%     90.64%
-system.cpu.op_class::MemWrite               438528338      9.36%    100.00%
-system.cpu.op_class::FloatMemRead                   0      0.00%    100.00%
-system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                 4686862596                      
-system.membus.snoop_filter.tot_requests             0                      
-system.membus.snoop_filter.hit_single_requests            0                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500                      
-system.membus.trans_dist::ReadReq          5252417628                      
-system.membus.trans_dist::ReadResp         5252417628                      
-system.membus.trans_dist::WriteReq          438528338                      
-system.membus.trans_dist::WriteResp         438528338                      
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   8026465764                      
-system.membus.pkt_count_system.cpu.icache_port::total   8026465764                      
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port   3355426168                      
-system.membus.pkt_count_system.cpu.dcache_port::total   3355426168                      
-system.membus.pkt_count::total            11381891932                      
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port  32105863056                      
-system.membus.pkt_size_system.cpu.icache_port::total  32105863056                      
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   6568525137                      
-system.membus.pkt_size_system.cpu.dcache_port::total   6568525137                      
-system.membus.pkt_size::total             38674388193                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples        5690945966                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0              5690945966    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total          5690945966                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
deleted file mode 100644 (file)
index 136c439..0000000
+++ /dev/null
@@ -1,432 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=bzip2 input.source 1
-cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
deleted file mode 100755 (executable)
index 43d7005..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
deleted file mode 100755 (executable)
index f2fd8c9..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 19:05:53
-gem5 started Apr  3 2017 19:06:21
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 5898831348500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
deleted file mode 100644 (file)
index 01185a8..0000000
+++ /dev/null
@@ -1,541 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  5.898831                      
-sim_ticks                                5898831348500                      
-final_tick                               5898831348500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 712175                      
-host_op_rate                                  1109633                      
-host_tick_rate                             1396571526                      
-host_mem_usage                                 285208                      
-host_seconds                                  4223.79                      
-sim_insts                                  3008081022                      
-sim_ops                                    4686862596                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.physmem.bytes_read::cpu.inst             43200                      
-system.physmem.bytes_read::cpu.data         126068992                      
-system.physmem.bytes_read::total            126112192                      
-system.physmem.bytes_inst_read::cpu.inst        43200                      
-system.physmem.bytes_inst_read::total           43200                      
-system.physmem.bytes_written::writebacks     66108032                      
-system.physmem.bytes_written::total          66108032                      
-system.physmem.num_reads::cpu.inst                675                      
-system.physmem.num_reads::cpu.data            1969828                      
-system.physmem.num_reads::total               1970503                      
-system.physmem.num_writes::writebacks         1032938                      
-system.physmem.num_writes::total              1032938                      
-system.physmem.bw_read::cpu.inst                 7323                      
-system.physmem.bw_read::cpu.data             21371859                      
-system.physmem.bw_read::total                21379183                      
-system.physmem.bw_inst_read::cpu.inst            7323                      
-system.physmem.bw_inst_read::total               7323                      
-system.physmem.bw_write::writebacks          11206971                      
-system.physmem.bw_write::total               11206971                      
-system.physmem.bw_total::writebacks          11206971                      
-system.physmem.bw_total::cpu.inst                7323                      
-system.physmem.bw_total::cpu.data            21371859                      
-system.physmem.bw_total::total               32586154                      
-system.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.apic_clk_domain.clock                 8000                      
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.workload.numSyscalls                    46                      
-system.cpu.pwrStateResidencyTicks::ON    5898831348500                      
-system.cpu.numCycles                      11797662697                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                  3008081022                      
-system.cpu.committedOps                    4686862596                      
-system.cpu.num_int_alu_accesses            4684368009                      
-system.cpu.num_fp_alu_accesses                      0                      
-system.cpu.num_func_calls                    33534539                      
-system.cpu.num_conditional_control_insts    182173300                      
-system.cpu.num_int_insts                   4684368009                      
-system.cpu.num_fp_insts                             0                      
-system.cpu.num_int_register_reads         10688755601                      
-system.cpu.num_int_register_writes         3999841477                      
-system.cpu.num_fp_register_reads                    0                      
-system.cpu.num_fp_register_writes                   0                      
-system.cpu.num_cc_register_reads           1226718827                      
-system.cpu.num_cc_register_writes          1355930461                      
-system.cpu.num_mem_refs                    1677713084                      
-system.cpu.num_load_insts                  1239184746                      
-system.cpu.num_store_insts                  438528338                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                11797662697                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         248500691                      
-system.cpu.op_class::No_OpClass               2494522      0.05%      0.05%
-system.cpu.op_class::IntAlu                3006647871     64.15%     64.20%
-system.cpu.op_class::IntMult                     6215      0.00%     64.20%
-system.cpu.op_class::IntDiv                       904      0.00%     64.20%
-system.cpu.op_class::FloatAdd                       0      0.00%     64.20%
-system.cpu.op_class::FloatCmp                       0      0.00%     64.20%
-system.cpu.op_class::FloatCvt                       0      0.00%     64.20%
-system.cpu.op_class::FloatMult                      0      0.00%     64.20%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     64.20%
-system.cpu.op_class::FloatDiv                       0      0.00%     64.20%
-system.cpu.op_class::FloatMisc                      0      0.00%     64.20%
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.20%
-system.cpu.op_class::SimdAdd                        0      0.00%     64.20%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.20%
-system.cpu.op_class::SimdAlu                        0      0.00%     64.20%
-system.cpu.op_class::SimdCmp                        0      0.00%     64.20%
-system.cpu.op_class::SimdCvt                        0      0.00%     64.20%
-system.cpu.op_class::SimdMisc                       0      0.00%     64.20%
-system.cpu.op_class::SimdMult                       0      0.00%     64.20%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.20%
-system.cpu.op_class::SimdShift                      0      0.00%     64.20%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.20%
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.20%
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.20%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.20%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.20%
-system.cpu.op_class::MemRead               1239184746     26.44%     90.64%
-system.cpu.op_class::MemWrite               438528338      9.36%    100.00%
-system.cpu.op_class::FloatMemRead                   0      0.00%    100.00%
-system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                 4686862596                      
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.dcache.tags.replacements           9108581                      
-system.cpu.dcache.tags.tagsinuse          4084.589706                      
-system.cpu.dcache.tags.total_refs          1668600407                      
-system.cpu.dcache.tags.sampled_refs           9112677                      
-system.cpu.dcache.tags.avg_refs            183.107599                      
-system.cpu.dcache.tags.warmup_cycle       58922805500                      
-system.cpu.dcache.tags.occ_blocks::cpu.data  4084.589706                      
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                      
-system.cpu.dcache.tags.occ_percent::total     0.997214                      
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          898                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2768                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          329                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                      
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                      
-system.cpu.dcache.tags.tag_accesses        3364538845                      
-system.cpu.dcache.tags.data_accesses       3364538845                      
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                      
-system.cpu.dcache.ReadReq_hits::total      1231961896                      
-system.cpu.dcache.WriteReq_hits::cpu.data    436638511                      
-system.cpu.dcache.WriteReq_hits::total      436638511                      
-system.cpu.dcache.demand_hits::cpu.data    1668600407                      
-system.cpu.dcache.demand_hits::total       1668600407                      
-system.cpu.dcache.overall_hits::cpu.data   1668600407                      
-system.cpu.dcache.overall_hits::total      1668600407                      
-system.cpu.dcache.ReadReq_misses::cpu.data      7222850                      
-system.cpu.dcache.ReadReq_misses::total       7222850                      
-system.cpu.dcache.WriteReq_misses::cpu.data      1889827                      
-system.cpu.dcache.WriteReq_misses::total      1889827                      
-system.cpu.dcache.demand_misses::cpu.data      9112677                      
-system.cpu.dcache.demand_misses::total        9112677                      
-system.cpu.dcache.overall_misses::cpu.data      9112677                      
-system.cpu.dcache.overall_misses::total       9112677                      
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000                      
-system.cpu.dcache.ReadReq_miss_latency::total 152690255000                      
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  64265951000                      
-system.cpu.dcache.WriteReq_miss_latency::total  64265951000                      
-system.cpu.dcache.demand_miss_latency::cpu.data 216956206000                      
-system.cpu.dcache.demand_miss_latency::total 216956206000                      
-system.cpu.dcache.overall_miss_latency::cpu.data 216956206000                      
-system.cpu.dcache.overall_miss_latency::total 216956206000                      
-system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                      
-system.cpu.dcache.ReadReq_accesses::total   1239184746                      
-system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                      
-system.cpu.dcache.WriteReq_accesses::total    438528338                      
-system.cpu.dcache.demand_accesses::cpu.data   1677713084                      
-system.cpu.dcache.demand_accesses::total   1677713084                      
-system.cpu.dcache.overall_accesses::cpu.data   1677713084                      
-system.cpu.dcache.overall_accesses::total   1677713084                      
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                      
-system.cpu.dcache.ReadReq_miss_rate::total     0.005829                      
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                      
-system.cpu.dcache.WriteReq_miss_rate::total     0.004309                      
-system.cpu.dcache.demand_miss_rate::cpu.data     0.005432                      
-system.cpu.dcache.demand_miss_rate::total     0.005432                      
-system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                      
-system.cpu.dcache.overall_miss_rate::total     0.005432                      
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071                      
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071                      
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420                      
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420                      
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700                      
-system.cpu.dcache.demand_avg_miss_latency::total 23808.174700                      
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700                      
-system.cpu.dcache.overall_avg_miss_latency::total 23808.174700                      
-system.cpu.dcache.blocked_cycles::no_mshrs            0                      
-system.cpu.dcache.blocked_cycles::no_targets            0                      
-system.cpu.dcache.blocked::no_mshrs                 0                      
-system.cpu.dcache.blocked::no_targets               0                      
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.dcache.writebacks::writebacks      3669049                      
-system.cpu.dcache.writebacks::total           3669049                      
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                      
-system.cpu.dcache.ReadReq_mshr_misses::total      7222850                      
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                      
-system.cpu.dcache.WriteReq_mshr_misses::total      1889827                      
-system.cpu.dcache.demand_mshr_misses::cpu.data      9112677                      
-system.cpu.dcache.demand_mshr_misses::total      9112677                      
-system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                      
-system.cpu.dcache.overall_mshr_misses::total      9112677                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  62376124000                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  62376124000                      
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000                      
-system.cpu.dcache.demand_mshr_miss_latency::total 207843529000                      
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000                      
-system.cpu.dcache.overall_mshr_miss_latency::total 207843529000                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.004309                      
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432                      
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                      
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                      
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700                      
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.icache.tags.replacements                10                      
-system.cpu.icache.tags.tagsinuse           555.760511                      
-system.cpu.icache.tags.total_refs          4013232208                      
-system.cpu.icache.tags.sampled_refs               675                      
-system.cpu.icache.tags.avg_refs          5945529.197037                      
-system.cpu.icache.tags.warmup_cycle                 0                      
-system.cpu.icache.tags.occ_blocks::cpu.inst   555.760511                      
-system.cpu.icache.tags.occ_percent::cpu.inst     0.271367                      
-system.cpu.icache.tags.occ_percent::total     0.271367                      
-system.cpu.icache.tags.occ_task_id_blocks::1024          665                      
-system.cpu.icache.tags.age_task_id_blocks_1024::0           33                      
-system.cpu.icache.tags.age_task_id_blocks_1024::4          632                      
-system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                      
-system.cpu.icache.tags.tag_accesses        8026466441                      
-system.cpu.icache.tags.data_accesses       8026466441                      
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                      
-system.cpu.icache.ReadReq_hits::total      4013232208                      
-system.cpu.icache.demand_hits::cpu.inst    4013232208                      
-system.cpu.icache.demand_hits::total       4013232208                      
-system.cpu.icache.overall_hits::cpu.inst   4013232208                      
-system.cpu.icache.overall_hits::total      4013232208                      
-system.cpu.icache.ReadReq_misses::cpu.inst          675                      
-system.cpu.icache.ReadReq_misses::total           675                      
-system.cpu.icache.demand_misses::cpu.inst          675                      
-system.cpu.icache.demand_misses::total            675                      
-system.cpu.icache.overall_misses::cpu.inst          675                      
-system.cpu.icache.overall_misses::total           675                      
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     42528500                      
-system.cpu.icache.ReadReq_miss_latency::total     42528500                      
-system.cpu.icache.demand_miss_latency::cpu.inst     42528500                      
-system.cpu.icache.demand_miss_latency::total     42528500                      
-system.cpu.icache.overall_miss_latency::cpu.inst     42528500                      
-system.cpu.icache.overall_miss_latency::total     42528500                      
-system.cpu.icache.ReadReq_accesses::cpu.inst   4013232883                      
-system.cpu.icache.ReadReq_accesses::total   4013232883                      
-system.cpu.icache.demand_accesses::cpu.inst   4013232883                      
-system.cpu.icache.demand_accesses::total   4013232883                      
-system.cpu.icache.overall_accesses::cpu.inst   4013232883                      
-system.cpu.icache.overall_accesses::total   4013232883                      
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.ReadReq_miss_rate::total     0.000000                      
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.demand_miss_rate::total     0.000000                      
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.overall_miss_rate::total     0.000000                      
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185                      
-system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185                      
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185                      
-system.cpu.icache.demand_avg_miss_latency::total 63005.185185                      
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185                      
-system.cpu.icache.overall_avg_miss_latency::total 63005.185185                      
-system.cpu.icache.blocked_cycles::no_mshrs            0                      
-system.cpu.icache.blocked_cycles::no_targets            0                      
-system.cpu.icache.blocked::no_mshrs                 0                      
-system.cpu.icache.blocked::no_targets               0                      
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.icache.writebacks::writebacks           10                      
-system.cpu.icache.writebacks::total                10                      
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                      
-system.cpu.icache.ReadReq_mshr_misses::total          675                      
-system.cpu.icache.demand_mshr_misses::cpu.inst          675                      
-system.cpu.icache.demand_mshr_misses::total          675                      
-system.cpu.icache.overall_mshr_misses::cpu.inst          675                      
-system.cpu.icache.overall_mshr_misses::total          675                      
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41853500                      
-system.cpu.icache.ReadReq_mshr_miss_latency::total     41853500                      
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41853500                      
-system.cpu.icache.demand_mshr_miss_latency::total     41853500                      
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41853500                      
-system.cpu.icache.overall_mshr_miss_latency::total     41853500                      
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.demand_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                      
-system.cpu.icache.overall_mshr_miss_rate::total     0.000000                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185                      
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185                      
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185                      
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185                      
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185                      
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.l2cache.tags.replacements          1938075                      
-system.cpu.l2cache.tags.tagsinuse        31745.660470                      
-system.cpu.l2cache.tags.total_refs           16250887                      
-system.cpu.l2cache.tags.sampled_refs          1970843                      
-system.cpu.l2cache.tags.avg_refs             8.245653                      
-system.cpu.l2cache.tags.warmup_cycle     320350195000                      
-system.cpu.l2cache.tags.occ_blocks::writebacks    11.856683                      
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.308015                      
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772                      
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000362                      
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000772                      
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.967666                      
-system.cpu.l2cache.tags.occ_percent::total     0.968801                      
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          435                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3097                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          786                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        28399                      
-system.cpu.l2cache.tags.occ_task_id_percent::1024            1                      
-system.cpu.l2cache.tags.tag_accesses        147746387                      
-system.cpu.l2cache.tags.data_accesses       147746387                      
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3669049                      
-system.cpu.l2cache.WritebackDirty_hits::total      3669049                      
-system.cpu.l2cache.WritebackClean_hits::writebacks           10                      
-system.cpu.l2cache.WritebackClean_hits::total           10                      
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1095863                      
-system.cpu.l2cache.ReadExReq_hits::total      1095863                      
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6046986                      
-system.cpu.l2cache.ReadSharedReq_hits::total      6046986                      
-system.cpu.l2cache.demand_hits::cpu.data      7142849                      
-system.cpu.l2cache.demand_hits::total         7142849                      
-system.cpu.l2cache.overall_hits::cpu.data      7142849                      
-system.cpu.l2cache.overall_hits::total        7142849                      
-system.cpu.l2cache.ReadExReq_misses::cpu.data       793964                      
-system.cpu.l2cache.ReadExReq_misses::total       793964                      
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          675                      
-system.cpu.l2cache.ReadCleanReq_misses::total          675                      
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1175864                      
-system.cpu.l2cache.ReadSharedReq_misses::total      1175864                      
-system.cpu.l2cache.demand_misses::cpu.inst          675                      
-system.cpu.l2cache.demand_misses::cpu.data      1969828                      
-system.cpu.l2cache.demand_misses::total       1970503                      
-system.cpu.l2cache.overall_misses::cpu.inst          675                      
-system.cpu.l2cache.overall_misses::cpu.data      1969828                      
-system.cpu.l2cache.overall_misses::total      1970503                      
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  48034822000                      
-system.cpu.l2cache.ReadExReq_miss_latency::total  48034822000                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     40839500                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     40839500                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  71139776000                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  71139776000                      
-system.cpu.l2cache.demand_miss_latency::cpu.inst     40839500                      
-system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000                      
-system.cpu.l2cache.demand_miss_latency::total 119215437500                      
-system.cpu.l2cache.overall_miss_latency::cpu.inst     40839500                      
-system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000                      
-system.cpu.l2cache.overall_miss_latency::total 119215437500                      
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3669049                      
-system.cpu.l2cache.WritebackDirty_accesses::total      3669049                      
-system.cpu.l2cache.WritebackClean_accesses::writebacks           10                      
-system.cpu.l2cache.WritebackClean_accesses::total           10                      
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                      
-system.cpu.l2cache.ReadExReq_accesses::total      1889827                      
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          675                      
-system.cpu.l2cache.ReadCleanReq_accesses::total          675                      
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7222850                      
-system.cpu.l2cache.ReadSharedReq_accesses::total      7222850                      
-system.cpu.l2cache.demand_accesses::cpu.inst          675                      
-system.cpu.l2cache.demand_accesses::cpu.data      9112677                      
-system.cpu.l2cache.demand_accesses::total      9113352                      
-system.cpu.l2cache.overall_accesses::cpu.inst          675                      
-system.cpu.l2cache.overall_accesses::cpu.data      9112677                      
-system.cpu.l2cache.overall_accesses::total      9113352                      
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.420125                      
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.420125                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162798                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162798                      
-system.cpu.l2cache.demand_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.216163                      
-system.cpu.l2cache.demand_miss_rate::total     0.216222                      
-system.cpu.l2cache.overall_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.216163                      
-system.cpu.l2cache.overall_miss_rate::total     0.216222                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031                      
-system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031                      
-system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045                      
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                      
-system.cpu.l2cache.blocked_cycles::no_targets            0                      
-system.cpu.l2cache.blocked::no_mshrs                0                      
-system.cpu.l2cache.blocked::no_targets              0                      
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.l2cache.writebacks::writebacks      1032938                      
-system.cpu.l2cache.writebacks::total          1032938                      
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          213                      
-system.cpu.l2cache.CleanEvict_mshr_misses::total          213                      
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       793964                      
-system.cpu.l2cache.ReadExReq_mshr_misses::total       793964                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          675                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          675                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1175864                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1175864                      
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                      
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1969828                      
-system.cpu.l2cache.demand_mshr_misses::total      1970503                      
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                      
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1969828                      
-system.cpu.l2cache.overall_mshr_misses::total      1970503                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  40095182000                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  40095182000                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     34089500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     34089500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  59381136000                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  59381136000                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34089500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  99476318000                      
-system.cpu.l2cache.demand_mshr_miss_latency::total  99510407500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34089500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  99476318000                      
-system.cpu.l2cache.overall_mshr_miss_latency::total  99510407500                      
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                      
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.420125                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.420125                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162798                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162798                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216163                      
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216222                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216163                      
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.216222                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045                      
-system.cpu.toL2Bus.snoop_filter.tot_requests     18221943                      
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9108591                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                      
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1186                      
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1186                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                      
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.cpu.toL2Bus.trans_dist::ReadResp       7223525                      
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4701987                      
-system.cpu.toL2Bus.trans_dist::WritebackClean           10                      
-system.cpu.toL2Bus.trans_dist::CleanEvict      6344669                      
-system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                      
-system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                      
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          675                      
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222850                      
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1360                      
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27333935                      
-system.cpu.toL2Bus.pkt_count::total          27335295                      
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43840                      
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818030464                      
-system.cpu.toL2Bus.pkt_size::total          818074304                      
-system.cpu.toL2Bus.snoops                     1938075                      
-system.cpu.toL2Bus.snoopTraffic              66108032                      
-system.cpu.toL2Bus.snoop_fanout::samples     11051427                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.000107                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.010359                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0           11050241     99.99%     99.99%
-system.cpu.toL2Bus.snoop_fanout::1               1186      0.01%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            1                      
-system.cpu.toL2Bus.snoop_fanout::total       11051427                      
-system.cpu.toL2Bus.reqLayer0.occupancy    12780030500                      
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                      
-system.cpu.toL2Bus.respLayer0.occupancy       1012500                      
-system.cpu.toL2Bus.respLayer0.utilization          0.0                      
-system.cpu.toL2Bus.respLayer1.occupancy   13669015500                      
-system.cpu.toL2Bus.respLayer1.utilization          0.2                      
-system.membus.snoop_filter.tot_requests       3907605                      
-system.membus.snoop_filter.hit_single_requests      1937102                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500                      
-system.membus.trans_dist::ReadResp            1176539                      
-system.membus.trans_dist::WritebackDirty      1032938                      
-system.membus.trans_dist::CleanEvict           904164                      
-system.membus.trans_dist::ReadExReq            793964                      
-system.membus.trans_dist::ReadExResp           793964                      
-system.membus.trans_dist::ReadSharedReq       1176539                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5878108                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5878108                      
-system.membus.pkt_count::total                5878108                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192220224                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    192220224                      
-system.membus.pkt_size::total               192220224                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples           1970503                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                 1970503    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total             1970503                      
-system.membus.reqLayer0.occupancy          8039359500                      
-system.membus.reqLayer0.utilization               0.1                      
-system.membus.respLayer1.occupancy         9852515000                      
-system.membus.respLayer1.utilization              0.2                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/test.py b/tests/long/se/60.bzip2/test.py
deleted file mode 100644 (file)
index b7e2688..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import bzip2_source
-
-workload = bzip2_source(isa, opsys, 'lgred')
-root.system.cpu[0].workload = workload.makeProcess()