fix extsb pseudo-code

some of the bit positions had been wrong

diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index 6611f89f8c261324b55778c2c0b0d52f0e8dc48f..b8ea786c269e7a3083e5c0a82f18b599f906c75c 100644 (file)
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -284,14 +284,19 @@ is a loss of functionality and opportunity:
                 extsw: 32-bit -> 64-bit sign extension
 ```
 
-The RTL for `extsb` becomes:
+The pseudo-code for `extsb` becomes:
 
 ```
-    in <- (RA)[XLEN-8:XLEN-1]
-    if XLEN = 8  then RT <- in[0]]  * 8               # 1->8
-    if XLEN = 16 then RT <- in[13]] * 15 || in[15]    # 2->16
-    if XLEN = 32 then RT <- in[28]] * 29 || in[29:31] # 4->32
-    if XLEN = 64 then RT <- in[55]] * 56 || in[57:63] # 8->64
+RT[0:XLEN-1] <- EXTS((RA)[XLEN*7/8:XLEN-1])
+```
+
+or, if expanded out:
+
+```
+    if XLEN = 8  then RT <- (RA)[ 7] * 7  || (RA)[ 7: 7] # 1 -> 8
+    if XLEN = 16 then RT <- (RA)[14] * 14 || (RA)[14:15] # 2 -> 16
+    if XLEN = 32 then RT <- (RA)[28] * 28 || (RA)[28:31] # 4 -> 32
+    if XLEN = 64 then RT <- (RA)[56] * 56 || (RA)[56:63] # 8 -> 64
 ```
 
 And `extsh` and `extsw` follow similar logic. Interestingly there is