arch-power: Add support for timebase updates
authorkajoljain379 <kajoljain797@gmail.com>
Wed, 20 Feb 2019 05:58:03 +0000 (11:28 +0530)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 Jan 2021 03:59:19 +0000 (03:59 +0000)
* Added support to update INTREG_TB on checkInterrupt
* Initialize TB register
* Add support for decrementer interrupt to check for ee bit to
  handle nested interrupt.

Change-Id: I2e1f37871879bb9370eba17ddb5d23562665b138
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
src/arch/power/interrupts.hh
src/arch/power/system.cc

index ead82dd7006f7e8b45688006ed8c82f52c5d9daa..7770a6c9dd240275eb87641a924628c0ed150dc1 100644 (file)
@@ -79,11 +79,15 @@ class Interrupts : public BaseInterrupts
     checkInterrupts(ThreadContext *tc)
     {
         //panic("Interrupts::checkInterrupts not implemented.\n");
-        if ( tc->readIntReg(INTREG_DEC) == 0) {
+      Msr msr = tc->readIntReg(INTREG_MSR);
+      tc->setIntReg(INTREG_TB , tc->readIntReg(INTREG_TB)+1);
+      if ( tc->readIntReg(INTREG_DEC) == 0 && msr.ee) {
            si = true;
            return true;
         }
-        else {
+      else if (tc->readIntReg(INTREG_DEC) == 0 && !msr.ee) {
+       return false;
+      } else {
            tc->setIntReg(INTREG_DEC , tc->readIntReg(INTREG_DEC)-1);
            return false;
         }
index 389bc625bdf177037d091d98615bbb9c16483694..1df07a5060d153593d1999cec9d20007fdf72e65 100644 (file)
@@ -73,11 +73,11 @@ PowerSystem::initState()
     Msr msr = 0x9000000000000001;
     tc->setIntReg(INTREG_DEC , 0xffffffffffffffff);
     // This PVR is specific to power9
+    // Setting TB register to 0
+    tc->setIntReg(INTREG_TB , 0x0);
     tc->setIntReg(INTREG_PVR , 0x004e1100);
     tc->setIntReg(INTREG_MSR , msr);
     //ArgumentReg0 is initialized with 0xc00000 because in linux/system.cc
     //dtb is loaded at 0xc00000
     tc->setIntReg(ArgumentReg0, 0x1800000);
-    /* Perform a system reset */
-    tc->pcState(0x100);
 }