Convert a few more tests to be able to use cxxsim

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 9c8115ce69da2c035f0d674ac3768fceb415020d..dd03932d466ab6a465a4fc858b453310decb90c8 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -14,7 +14,10 @@ from nmigen.hdl.rec import Record, Layout
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.sim import run_simulation
-from nmigen.back.pysim import Simulator, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator
 
 from soc.decoder.power_enums import MicrOp, Function, CryIn
 

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 45701eb66fe82e04dbfb0814eeb4b1a412bf8ea2..9b0c73308f6552ba8740acd78b49bd27befa95a8 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -14,19 +14,10 @@ import unittest
 from nmigen.cli import rtlil
 from nmutil.formaltest import FHDLTestCase
 from nmigen import Module, Signal
-from nmigen.back.pysim import Delay, Settle
-# NOTE: to use this (set to True), at present it is necessary to check
-# out the cxxsim nmigen branch
-cxxsim = False
-if cxxsim:
-    try:
-        from nmigen.sim.cxxsim import Simulator
-    except ImportError:
-        print("nope, sorry, have to use nmigen cxxsim branch for now")
-        cxxsim = False
-        from nmigen.back.pysim import Simulator
-else:
-    from nmigen.back.pysim import Simulator
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 def get_cu_inputs(dec2, sim):

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 915989358f42ddb589240a754657b6f8f5dc51a1..03e76435a21b84efa208fa2a797725a05d19f2f0 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal, ResetSignal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index d9c8a718721569d80890d91b28b387bd43d2d052..3b57b52933b79298cf16719c5e932e945c0deb4b 100644 (file)
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -2,7 +2,11 @@ import random
 import unittest
 import power_instruction_analyzer as pia
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.power_enums import XER_bits, Function

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 794e9fcdaaa53b10690d389f0775e715df520274..f5f319fab3c54aec34defd55bc5b0c5674771d46 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index 1c2ad912e3e7904a5bb9f42591a2cf1607915e6a..934138a56ed40d94955ea547d239991d318cd4df 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.sim.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 4c5fb39cd4c43a03d22cc553ed499bc9c6a2f641..e939a699ff5f929c0a47b07c835156220d03f2de 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index aa45b6c757133362f8994069bb28a73cd6d315c0..1cc4c4238b53bd5ebe2e2e3c90b32ba7268ddab4 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index edcfb4f7be5111aba47757fb604aa0ef94594f37..08361c99392aaa139a34fb8b5b37deeb0cec76f7 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -5,7 +5,11 @@ related bugs:
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
 from nmigen import Module, Signal, Cat
-from nmutil.sim_tmp_alternative import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest