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Adding missing vexriscv CPU.
authorTim 'mithro' Ansell <me@mith.ro>
Sun, 23 Feb 2020 22:54:07 +0000 (14:54 -0800)
committerTim 'mithro' Ansell <me@mith.ro>
Sun, 12 Apr 2020 01:37:06 +0000 (18:37 -0700)
litex_setup.py patch | blob | history

diff --git a/litex_setup.py b/litex_setup.py
index ffd8fd76f696bb181afd084020d71a153adce845..ff2777bfa39fb4ffeb4d22acae64adf2ab852126 100755 (executable)
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -43,6 +43,7 @@ repos = [
     ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)