[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Mon, 25 May 2020 02:21:01 +0000 (02:21 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Mon, 25 May 2020 02:21:03 +0000 (03:21 +0100)
cb/ee7c790e4254aec7dc0fd64cd384f971af8d60 [new file with mode: 0644]

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+Date: Mon, 25 May 2020 02:21:01 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-yRr75Jk8ft@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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