block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:25
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 23:18:50
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 107825000
-Exiting @ tick 1901719660500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 110215000
+Exiting @ tick 1900727015500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.897808 # Number of seconds simulated
-sim_ticks 1897807508000 # Number of ticks simulated
-final_tick 1897807508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.900727 # Number of seconds simulated
+sim_ticks 1900727015500 # Number of ticks simulated
+final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94343 # Simulator instruction rate (inst/s)
-host_op_rate 94343 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3156287920 # Simulator tick rate (ticks/s)
-host_mem_usage 338708 # Number of bytes of host memory used
-host_seconds 601.28 # Real time elapsed on the host
-sim_insts 56726638 # Number of instructions simulated
-sim_ops 56726638 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 852800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24659584 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 123904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 537024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28824960 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 852800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 123904 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 976704 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7794816 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7794816 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13325 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 385306 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1936 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8391 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450390 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 121794 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 121794 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 449361 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12993722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1397217 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 65288 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 282971 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15188558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 449361 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 65288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 514649 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4107274 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4107274 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4107274 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 449361 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12993722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1397217 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 65288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 282971 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19295833 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450390 # Total number of read requests seen
-system.physmem.writeReqs 121794 # Total number of write requests seen
-system.physmem.cpureqs 577229 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28824960 # Total number of bytes read from memory
-system.physmem.bytesWritten 7794816 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28824960 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7794816 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 5032 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28516 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28325 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28182 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28018 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28421 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28301 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 28181 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28103 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27880 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27811 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28047 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27949 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7958 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7700 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7581 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7841 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7698 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7706 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7677 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7797 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7592 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7617 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7289 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7480 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7323 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7475 # Track writes on a per bank basis
+host_inst_rate 47037 # Simulator instruction rate (inst/s)
+host_op_rate 47037 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1570523818 # Simulator tick rate (ticks/s)
+host_mem_usage 354648 # Number of bytes of host memory used
+host_seconds 1210.25 # Real time elapsed on the host
+sim_insts 56926994 # Number of instructions simulated
+sim_ops 56926994 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 449493 # Total number of read requests seen
+system.physmem.writeReqs 120791 # Total number of write requests seen
+system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28767552 # Total number of bytes read from memory
+system.physmem.bytesWritten 7730624 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7707 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7701 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7578 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7608 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7520 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7649 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7589 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7579 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7352 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7235 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7444 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7276 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7350 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1897802972000 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1900722456000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 450390 # Categorize read packet sizes
+system.physmem.readPktSize::6 449493 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 121794 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 319842 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59620 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 33247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2675 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2631 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2569 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1505 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1451 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1403 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1342 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1503 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 120791 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7610 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2961 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2698 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2655 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::10 1511 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1362 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1348 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3815 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4430 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4913 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5274 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5280 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2130 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1481 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 383 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
-system.physmem.totQLat 7744912500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15549496250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2251660000 # Total cycles spent in databus access
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-system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency
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-system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.928379 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 12324830 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 10383801 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 330699 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 7879276 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 5243296 # Number of BTB hits
+system.cpu0.branchPred.lookups 12043910 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 66.545403 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 784421 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 32635 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8754095 # DTB read hits
-system.cpu0.dtb.read_misses 29935 # DTB read misses
-system.cpu0.dtb.read_acv 546 # DTB read access violations
-system.cpu0.dtb.read_accesses 624217 # DTB read accesses
-system.cpu0.dtb.write_hits 5744304 # DTB write hits
-system.cpu0.dtb.write_misses 8066 # DTB write misses
-system.cpu0.dtb.write_acv 350 # DTB write access violations
-system.cpu0.dtb.write_accesses 207709 # DTB write accesses
-system.cpu0.dtb.data_hits 14498399 # DTB hits
-system.cpu0.dtb.data_misses 38001 # DTB misses
-system.cpu0.dtb.data_acv 896 # DTB access violations
-system.cpu0.dtb.data_accesses 831926 # DTB accesses
-system.cpu0.itb.fetch_hits 984231 # ITB hits
-system.cpu0.itb.fetch_misses 30400 # ITB misses
-system.cpu0.itb.fetch_acv 951 # ITB acv
-system.cpu0.itb.fetch_accesses 1014631 # ITB accesses
+system.cpu0.dtb.read_hits 8552844 # DTB read hits
+system.cpu0.dtb.read_misses 30306 # DTB read misses
+system.cpu0.dtb.read_acv 545 # DTB read access violations
+system.cpu0.dtb.read_accesses 625084 # DTB read accesses
+system.cpu0.dtb.write_hits 5600708 # DTB write hits
+system.cpu0.dtb.write_misses 7703 # DTB write misses
+system.cpu0.dtb.write_acv 337 # DTB write access violations
+system.cpu0.dtb.write_accesses 207517 # DTB write accesses
+system.cpu0.dtb.data_hits 14153552 # DTB hits
+system.cpu0.dtb.data_misses 38009 # DTB misses
+system.cpu0.dtb.data_acv 882 # DTB access violations
+system.cpu0.dtb.data_accesses 832601 # DTB accesses
+system.cpu0.itb.fetch_hits 972187 # ITB hits
+system.cpu0.itb.fetch_misses 27447 # ITB misses
+system.cpu0.itb.fetch_acv 929 # ITB acv
+system.cpu0.itb.fetch_accesses 999634 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 101829868 # number of cpu cycles simulated
+system.cpu0.numCycles 100158206 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 24831231 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 63164825 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 12324830 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 6027717 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 11886034 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1687418 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 36616651 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 32610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 197530 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 292271 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 247 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7635312 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 223745 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 74945500 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.842810 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.180311 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 63059466 84.14% 84.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 761662 1.02% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1556791 2.08% 87.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 699013 0.93% 88.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2562383 3.42% 91.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 515928 0.69% 92.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 568129 0.76% 93.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 822428 1.10% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4399700 5.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 74945500 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.121034 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.620298 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26048767 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 36112585 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 10811010 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 918999 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1054138 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 507624 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 35116 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 62016567 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 105227 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1054138 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27056479 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14636567 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 17989986 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 10129953 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 4078375 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 58716570 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6669 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 641571 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1425002 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 39326634 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 71486416 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 71104766 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 381650 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 34557314 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4769312 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1434958 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 208601 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 11111126 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9162338 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6008284 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1124943 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 741369 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 52108127 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1785217 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 50965376 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 88359 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5842472 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2979590 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1208696 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 74945500 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.680033 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.329236 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 52296103 69.78% 69.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10307056 13.75% 83.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4639666 6.19% 89.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3056082 4.08% 93.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2432821 3.25% 97.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1212271 1.62% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 643524 0.86% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 306857 0.41% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 51120 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 74945500 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 83315 12.44% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 310574 46.36% 58.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 276009 41.20% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 35160159 68.99% 69.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 56163 0.11% 69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9109271 17.87% 87.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5812211 11.40% 98.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 806271 1.58% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 50965376 # Type of FU issued
-system.cpu0.iq.rate 0.500495 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 669898 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 177086282 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 59482873 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 49950097 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 548226 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 265331 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 258806 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 51344519 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 286981 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 543841 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued
+system.cpu0.iq.rate 0.498985 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1097645 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3519 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12633 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 446832 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18414 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 123451 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1054138 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10442164 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 794127 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 57094083 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 608812 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9162338 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6008284 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1572405 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 581948 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5528 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12633 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 164589 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 346313 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 510902 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 50577895 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8807105 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 387480 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3200739 # number of nop insts executed
-system.cpu0.iew.exec_refs 14572965 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 8058105 # Number of branches executed
-system.cpu0.iew.exec_stores 5765860 # Number of stores executed
-system.cpu0.iew.exec_rate 0.496690 # Inst execution rate
-system.cpu0.iew.wb_sent 50296670 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 50208903 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 25061095 # num instructions producing a value
-system.cpu0.iew.wb_consumers 33769433 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3133489 # number of nop insts executed
+system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7905275 # Number of branches executed
+system.cpu0.iew.exec_stores 5621640 # Number of stores executed
+system.cpu0.iew.exec_rate 0.495223 # Inst execution rate
+system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24627791 # num instructions producing a value
+system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.493067 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.742124 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6306622 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 576521 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 477545 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 73891362 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.686006 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.603918 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 54863146 74.25% 74.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7931478 10.73% 84.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4331360 5.86% 90.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2351860 3.18% 94.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1314304 1.78% 95.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 548181 0.74% 96.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 466916 0.63% 97.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 432440 0.59% 97.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1651677 2.24% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 73891362 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 50689891 # Number of instructions committed
-system.cpu0.commit.committedOps 50689891 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 49720528 # Number of instructions committed
+system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13626145 # Number of memory references committed
-system.cpu0.commit.loads 8064693 # Number of loads committed
-system.cpu0.commit.membars 196335 # Number of memory barriers committed
-system.cpu0.commit.branches 7657959 # Number of branches committed
-system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 46940801 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 646411 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1651677 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13302179 # Number of memory references committed
+system.cpu0.commit.loads 7888682 # Number of loads committed
+system.cpu0.commit.membars 189617 # Number of memory barriers committed
+system.cpu0.commit.branches 7516247 # Number of branches committed
+system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 629253 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.quiesceCycles 3693778600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 47771172 # Number of Instructions Simulated
-system.cpu0.committedOps 47771172 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 47771172 # Number of Instructions Simulated
-system.cpu0.cpi 2.131618 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.131618 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.469127 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.469127 # IPC: Total IPC of All Threads
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+system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads
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system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
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-system.cpu0.icache.sampled_refs 863332 # Sample count of references to valid blocks.
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-system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 14090.066015 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 14090.066015 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 2647984 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2186587 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 77884 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1531761 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 883024 # Number of BTB hits
+system.cpu1.branchPred.lookups 2951549 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 57.647636 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 183996 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 8305 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1962214 # DTB read hits
-system.cpu1.dtb.read_misses 10693 # DTB read misses
+system.cpu1.dtb.read_hits 2175312 # DTB read hits
+system.cpu1.dtb.read_misses 10933 # DTB read misses
system.cpu1.dtb.read_acv 25 # DTB read access violations
-system.cpu1.dtb.read_accesses 324562 # DTB read accesses
-system.cpu1.dtb.write_hits 1265832 # DTB write hits
-system.cpu1.dtb.write_misses 2093 # DTB write misses
-system.cpu1.dtb.write_acv 66 # DTB write access violations
-system.cpu1.dtb.write_accesses 133005 # DTB write accesses
-system.cpu1.dtb.data_hits 3228046 # DTB hits
-system.cpu1.dtb.data_misses 12786 # DTB misses
-system.cpu1.dtb.data_acv 91 # DTB access violations
-system.cpu1.dtb.data_accesses 457567 # DTB accesses
-system.cpu1.itb.fetch_hits 437198 # ITB hits
-system.cpu1.itb.fetch_misses 6975 # ITB misses
-system.cpu1.itb.fetch_acv 228 # ITB acv
-system.cpu1.itb.fetch_accesses 444173 # ITB accesses
+system.cpu1.dtb.read_accesses 324345 # DTB read accesses
+system.cpu1.dtb.write_hits 1433020 # DTB write hits
+system.cpu1.dtb.write_misses 2283 # DTB write misses
+system.cpu1.dtb.write_acv 64 # DTB write access violations
+system.cpu1.dtb.write_accesses 133154 # DTB write accesses
+system.cpu1.dtb.data_hits 3608332 # DTB hits
+system.cpu1.dtb.data_misses 13216 # DTB misses
+system.cpu1.dtb.data_acv 89 # DTB access violations
+system.cpu1.dtb.data_accesses 457499 # DTB accesses
+system.cpu1.itb.fetch_hits 457840 # ITB hits
+system.cpu1.itb.fetch_misses 7553 # ITB misses
+system.cpu1.itb.fetch_acv 250 # ITB acv
+system.cpu1.itb.fetch_accesses 465393 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 16140506 # number of cpu cycles simulated
+system.cpu1.numCycles 18134862 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 6118318 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 12482084 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 2647984 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1067020 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 2239129 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 408271 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 6344159 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 26393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 65784 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 57491 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1512128 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 52849 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 15112669 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.825935 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.199937 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 12873540 85.18% 85.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 143819 0.95% 86.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 241770 1.60% 87.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 180451 1.19% 88.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 309857 2.05% 90.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 119919 0.79% 91.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 135082 0.89% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 201991 1.34% 94.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 906240 6.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 15112669 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.164058 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.773339 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 6050197 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 6601549 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 2093593 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 113312 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 254017 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 116024 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 7481 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 12238533 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 22436 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 254017 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 6259861 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 497059 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 5456265 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 1994881 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 650584 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 11345893 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 56627 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 159750 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 7468114 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 13547421 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 13404114 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 143307 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 6384399 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1083715 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 455985 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 44016 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2004753 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 2075172 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1340696 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 190596 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 106471 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 9962736 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 502412 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 9694977 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 29943 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1444595 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 720781 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 360981 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 15112669 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.641513 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.316207 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 10849099 71.79% 71.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 1954888 12.94% 84.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 839816 5.56% 90.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 558366 3.69% 93.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 473326 3.13% 97.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 218082 1.44% 98.55% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 140204 0.93% 99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 70683 0.47% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 8205 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 15112669 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 3691 1.86% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 106885 53.95% 55.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 87531 44.18% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 6046898 62.37% 62.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 16423 0.17% 62.58% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2053041 21.18% 83.88% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1289229 13.30% 97.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 273248 2.82% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 9694977 # Type of FU issued
-system.cpu1.iq.rate 0.600661 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 198107 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.020434 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 34523477 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 11810363 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 9424990 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 207196 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 101110 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 98065 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 9781516 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 108042 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 94596 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued
+system.cpu1.iq.rate 0.597126 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 286791 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 870 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1822 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 126158 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 10101 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 254017 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 327186 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 41525 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 10980256 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 148232 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 2075172 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1340696 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 454941 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 34335 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2140 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1822 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 35734 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 100242 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 135976 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 9604840 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 1980291 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 90137 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 515108 # number of nop insts executed
-system.cpu1.iew.exec_refs 3254225 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1434575 # Number of branches executed
-system.cpu1.iew.exec_stores 1273934 # Number of stores executed
-system.cpu1.iew.exec_rate 0.595077 # Inst execution rate
-system.cpu1.iew.wb_sent 9552134 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 9523055 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 4457844 # num instructions producing a value
-system.cpu1.iew.wb_consumers 6254214 # num instructions consuming a value
+system.cpu1.iew.exec_nop 600729 # number of nop insts executed
+system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1609931 # Number of branches executed
+system.cpu1.iew.exec_stores 1442207 # Number of stores executed
+system.cpu1.iew.exec_rate 0.591458 # Inst execution rate
+system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4954529 # num instructions producing a value
+system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.590010 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.712774 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1499365 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 141431 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 128632 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 14858652 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.633306 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.577285 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 11337498 76.30% 76.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1644581 11.07% 87.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 614314 4.13% 91.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 371520 2.50% 94.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 264064 1.78% 95.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 106187 0.71% 96.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 110282 0.74% 97.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 108223 0.73% 97.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 301983 2.03% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 14858652 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 9410077 # Number of instructions committed
-system.cpu1.commit.committedOps 9410077 # Number of ops (including micro ops) committed
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-system.cpu1.committedInsts_total 8955466 # Number of Instructions Simulated
-system.cpu1.cpi 1.802308 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.802308 # CPI: Total CPI of All Threads
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-system.cpu1.icache.demand_avg_miss_latency::total 13858.876452 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency
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-system.cpu1.icache.demand_mshr_misses::cpu1.inst 227261 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 227261 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 227261 # number of overall MSHR misses
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-system.cpu1.icache.demand_mshr_miss_latency::total 2711595499 # number of demand (read+write) MSHR miss cycles
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 72044 # number of writebacks
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+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675233500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675233500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706208000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706208000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045465 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045465 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034356 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034356 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128546 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128546 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092914 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092914 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.041055 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.041055 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12191.161306 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12191.161306 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6549 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 181634 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 64148 40.44% 40.44% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.08% 40.52% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1924 1.21% 41.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 92227 58.14% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 158624 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 63158 49.20% 49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1924 1.50% 50.80% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 62964 49.05% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 128371 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1862438042500 98.14% 98.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 62559000 0.00% 98.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 567042000 0.03% 98.17% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 94587500 0.00% 98.17% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 34644439500 1.83% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1897806670500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.984567 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.682707 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.809279 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 202 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 151888 91.03% 93.33% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6165 3.69% 97.02% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed
-system.cpu0.kern.callpal::rti 4486 2.69% 99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 166848 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed
+system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
+system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed
+system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 161075 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1258
system.cpu0.kern.mode_good::user 1259
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.180023 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.305202 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1895901736500 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1904926000 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3470 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3343 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2462 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 58111 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 18212 36.94% 36.94% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1923 3.90% 40.85% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 28864 58.55% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 49296 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 17825 47.44% 47.44% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1923 5.12% 52.56% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 17528 46.65% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 37573 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1872585348000 98.69% 98.69% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 531683000 0.03% 98.71% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 134630500 0.01% 98.72% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 24248440000 1.28% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1897500101500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.978750 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.607262 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.762192 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 124 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed
-system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 43980 85.81% 88.44% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2592 5.06% 93.50% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed
-system.cpu1.kern.callpal::rti 3095 6.04% 99.56% # number of callpals executed
-system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed
-system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 255 0.44% 0.44% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1393 2.41% 2.86% # number of callpals executed
+system.cpu1.kern.callpal::tbi 6 0.01% 2.87% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 2.88% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 49964 86.52% 89.41% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2595 4.49% 93.90% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 93.90% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 93.91% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 93.91% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 93.91% # number of callpals executed
+system.cpu1.kern.callpal::rti 3286 5.69% 99.61% # number of callpals executed
+system.cpu1.kern.callpal::callsys 184 0.32% 99.92% # number of callpals executed
+system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 51254 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 489 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 710
-system.cpu1.kern.mode_good::user 489
-system.cpu1.kern.mode_good::idle 221
-system.cpu1.kern.mode_switch_good::kernel 0.498596 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 57746 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1619 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 771
+system.cpu1.kern.mode_good::user 488
+system.cpu1.kern.mode_good::idle 283
+system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.090722 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.326512 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 4824136000 0.25% 0.25% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 831285000 0.04% 0.30% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1891834463500 99.70% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1141 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1394 # number of times the context was actually changed
---------- End Simulation Statistics ----------
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/projects/pd/randd/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 13 2013 10:45:16
-gem5 started Feb 13 2013 13:46:08
-gem5 executing on u200540-lin
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 23:18:16
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1854310111000 because m5_exit instruction encountered
+Exiting @ tick 1854315933000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.854310 # Number of seconds simulated
-sim_ticks 1854310449000 # Number of ticks simulated
-final_tick 1854310449000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.854316 # Number of seconds simulated
+sim_ticks 1854315933000 # Number of ticks simulated
+final_tick 1854315933000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91767 # Simulator instruction rate (inst/s)
-host_op_rate 91767 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3212612251 # Simulator tick rate (ticks/s)
-host_mem_usage 333588 # Number of bytes of host memory used
-host_seconds 577.20 # Real time elapsed on the host
-sim_insts 52967561 # Number of instructions simulated
-sim_ops 52967561 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 964416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24875392 # Number of bytes read from this memory
+host_inst_rate 49330 # Simulator instruction rate (inst/s)
+host_op_rate 49330 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1727408560 # Simulator tick rate (ticks/s)
+host_mem_usage 351576 # Number of bytes of host memory used
+host_seconds 1073.47 # Real time elapsed on the host
+sim_insts 52953842 # Number of instructions simulated
+sim_ops 52953842 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 964736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28492160 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 964416 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 964416 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7502272 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7502272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15069 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388678 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28496192 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 964736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 964736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7502848 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7502848 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445190 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117223 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117223 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 520094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13414901 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1430371 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15365367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 520094 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 520094 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4045855 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4045855 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4045855 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 520094 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13414901 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1430371 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19411222 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445190 # Total number of read requests seen
-system.physmem.writeReqs 117223 # Total number of write requests seen
-system.physmem.cpureqs 562598 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28492160 # Total number of bytes read from memory
-system.physmem.bytesWritten 7502272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28492160 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7502272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28015 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27564 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27868 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27959 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27788 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28082 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27814 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27969 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27768 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27789 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27980 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27796 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7542 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7286 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7135 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7347 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7367 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7431 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7327 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7363 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7509 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7240 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7287 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7384 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7205 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis
+system.physmem.num_reads::total 445253 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117232 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117232 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 520265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13416864 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15367496 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 520265 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 520265 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4046154 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4046154 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4046154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 520265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13416864 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19413650 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445253 # Total number of read requests seen
+system.physmem.writeReqs 117232 # Total number of write requests seen
+system.physmem.cpureqs 562681 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28496192 # Total number of bytes read from memory
+system.physmem.bytesWritten 7502848 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28496192 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7502848 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 180 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27757 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27571 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27900 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27985 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27992 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28084 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27816 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27970 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27741 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27761 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27965 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27782 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27722 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7549 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7292 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6981 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7370 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7331 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7642 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7358 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7506 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7213 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7258 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7375 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7186 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7197 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1854305000000 # Total gap between requests
+system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1854310455000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 445190 # Categorize read packet sizes
+system.physmem.readPktSize::6 445253 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 117223 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 323496 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 64344 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 19569 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7556 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2695 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1522 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1467 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1417 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1613 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1504 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 920 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 117232 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 323581 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 64321 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 19541 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2943 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3705 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4227 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4723 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5070 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5081 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5083 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5084 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5097 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2154 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1392 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 938 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 374 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 27 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
-system.physmem.totQLat 7465727500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15177783750 # Sum of mem lat for all requests
-system.physmem.totBusLat 2225655000 # Total cycles spent in databus access
-system.physmem.totBankLat 5486401250 # Total cycles spent in bank access
-system.physmem.avgQLat 16771.98 # Average queueing delay per request
-system.physmem.avgBankLat 12325.36 # Average bank access latency per request
+system.physmem.wrQLenPdf::15 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1390 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 947 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 376 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
+system.physmem.totQLat 7494847250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 15211767250 # Sum of mem lat for all requests
+system.physmem.totBusLat 2225940000 # Total cycles spent in databus access
+system.physmem.totBankLat 5490980000 # Total cycles spent in bank access
+system.physmem.avgQLat 16835.24 # Average queueing delay per request
+system.physmem.avgBankLat 12334.07 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 34097.34 # Average memory access latency
+system.physmem.avgMemAccLat 34169.31 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 14.50 # Average write queue length over time
-system.physmem.readRowHits 417731 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91366 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes
-system.physmem.avgGap 3297052.17 # Average gap between requests
+system.physmem.avgWrQLen 12.10 # Average write queue length over time
+system.physmem.readRowHits 417708 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91270 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.85 # Row buffer hit rate for writes
+system.physmem.avgGap 3296639.83 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.265060 # Cycle average of tags in use
+system.iocache.tagsinuse 1.265086 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.265060 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1704475467000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.265086 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.079068 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.079068 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10634247416 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10634247416 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10655175414 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10655175414 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10655175414 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10655175414 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10643328423 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10643328423 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10664256421 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10664256421 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10664256421 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10664256421 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.247016 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 255926.247016 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255366.696561 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255366.696561 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 283342 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256144.792621 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256144.792621 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255584.336034 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255584.336034 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 284060 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27068 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27214 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.467785 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.438010 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472247190 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8472247190 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8484178439 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8484178439 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8484178439 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8484178439 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8481334185 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8481334185 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8493265434 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8493265434 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8493265434 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8493265434 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203895.051742 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203895.051742 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204113.741456 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204113.741456 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13849744 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11622401 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 399564 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9420297 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5813323 # Number of BTB hits
+system.cpu.branchPred.lookups 13854129 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11621858 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 400402 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9160821 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5815827 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.710613 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 901783 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 38632 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 63.485871 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 906747 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 38946 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9912266 # DTB read hits
-system.cpu.dtb.read_misses 41544 # DTB read misses
-system.cpu.dtb.read_acv 542 # DTB read access violations
-system.cpu.dtb.read_accesses 940163 # DTB read accesses
-system.cpu.dtb.write_hits 6601788 # DTB write hits
-system.cpu.dtb.write_misses 10570 # DTB write misses
-system.cpu.dtb.write_acv 410 # DTB write access violations
-system.cpu.dtb.write_accesses 337668 # DTB write accesses
-system.cpu.dtb.data_hits 16514054 # DTB hits
-system.cpu.dtb.data_misses 52114 # DTB misses
-system.cpu.dtb.data_acv 952 # DTB access violations
-system.cpu.dtb.data_accesses 1277831 # DTB accesses
-system.cpu.itb.fetch_hits 1306011 # ITB hits
-system.cpu.itb.fetch_misses 36868 # ITB misses
-system.cpu.itb.fetch_acv 1103 # ITB acv
-system.cpu.itb.fetch_accesses 1342879 # ITB accesses
+system.cpu.dtb.read_hits 9920210 # DTB read hits
+system.cpu.dtb.read_misses 41076 # DTB read misses
+system.cpu.dtb.read_acv 544 # DTB read access violations
+system.cpu.dtb.read_accesses 941527 # DTB read accesses
+system.cpu.dtb.write_hits 6593814 # DTB write hits
+system.cpu.dtb.write_misses 10775 # DTB write misses
+system.cpu.dtb.write_acv 404 # DTB write access violations
+system.cpu.dtb.write_accesses 338229 # DTB write accesses
+system.cpu.dtb.data_hits 16514024 # DTB hits
+system.cpu.dtb.data_misses 51851 # DTB misses
+system.cpu.dtb.data_acv 948 # DTB access violations
+system.cpu.dtb.data_accesses 1279756 # DTB accesses
+system.cpu.itb.fetch_hits 1305070 # ITB hits
+system.cpu.itb.fetch_misses 36981 # ITB misses
+system.cpu.itb.fetch_acv 1089 # ITB acv
+system.cpu.itb.fetch_accesses 1342051 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 108629038 # number of cpu cycles simulated
+system.cpu.numCycles 108723981 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28026689 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70680176 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13849744 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6715106 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13246427 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1984359 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37388108 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32353 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 254081 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 294447 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 699 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8549154 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 266665 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80527554 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.877714 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.221537 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28071835 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70691782 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13854129 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6722574 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13248795 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1991444 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 37396273 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 253900 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 295773 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 814 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8551942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 266251 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 80590196 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.877176 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.220882 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67281127 83.55% 83.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 855303 1.06% 84.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1700571 2.11% 86.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 822573 1.02% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2750497 3.42% 91.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 561265 0.70% 91.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 645561 0.80% 92.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1010923 1.26% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4899734 6.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67341401 83.56% 83.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 854251 1.06% 84.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1698632 2.11% 86.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 828031 1.03% 87.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2750245 3.41% 91.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 562298 0.70% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 643304 0.80% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1012392 1.26% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4899642 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80527554 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.127496 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.650656 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29153725 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37057832 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12110647 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 962931 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1242418 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 586230 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42729 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69379302 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129899 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1242418 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30276016 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13626490 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19778343 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11345486 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4258799 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65628358 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 6970 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 508418 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1479478 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43831634 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79654682 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79176161 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 478521 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38170118 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5661508 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682525 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12113982 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10427074 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6890989 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1312659 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 851378 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58169067 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2051551 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56810875 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 88738 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6892578 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3503311 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1390624 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80527554 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.705484 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.366898 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 80590196 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.127425 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.650195 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29205934 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37061149 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12112258 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 963051 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1247803 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 585584 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42566 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69386312 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 128816 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1247803 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30327018 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13624252 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19779589 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11347768 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4263764 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65637148 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6817 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 509709 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1485643 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43822331 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79670452 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79191261 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 479191 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38158982 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5663341 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1681975 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 239504 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12131366 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10436836 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6902083 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1326454 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 859310 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58185317 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2050283 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56802944 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 107134 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6922426 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3549333 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1389358 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 80590196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.704837 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.365985 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55885936 69.40% 69.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10804988 13.42% 82.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5163321 6.41% 89.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3374568 4.19% 93.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2652291 3.29% 96.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1461239 1.81% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 754842 0.94% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 331822 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 98547 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 55946315 69.42% 69.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10805415 13.41% 82.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5162410 6.41% 89.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3384715 4.20% 93.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2645600 3.28% 96.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1461420 1.81% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 757318 0.94% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 330868 0.41% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 96135 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80527554 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 80590196 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 91181 11.49% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 373750 47.11% 58.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 328508 41.40% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 91816 11.60% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 373288 47.16% 58.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 326368 41.24% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38738406 68.19% 68.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38732288 68.19% 68.20% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61693 0.11% 68.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10344574 18.21% 86.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6680654 11.76% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949005 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10350848 18.22% 86.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6672590 11.75% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 948996 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56810875 # Type of FU issued
-system.cpu.iq.rate 0.522981 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 793439 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013966 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194338715 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66791274 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55577661 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692765 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 335658 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327829 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57234972 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 362056 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 601138 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 56802944 # Type of FU issued
+system.cpu.iq.rate 0.522451 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 791472 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013934 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 194402098 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66835363 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55566146 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 692591 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327919 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57225685 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 601434 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1337046 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14068 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 514312 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1348949 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4999 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14153 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 526604 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17961 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 173725 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17963 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 174400 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1242418 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9954083 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 684701 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63749782 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 676077 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10427074 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6890989 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1807007 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18311 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14068 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 203273 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 412234 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 615507 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56340822 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 9981988 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 470052 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1247803 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9948703 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63760053 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 677795 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10436836 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6902083 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1805728 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512612 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14153 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 203761 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 412011 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 615772 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56335729 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 9989502 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 467214 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3529164 # number of nop insts executed
-system.cpu.iew.exec_refs 16609586 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8925674 # Number of branches executed
-system.cpu.iew.exec_stores 6627598 # Number of stores executed
-system.cpu.iew.exec_rate 0.518653 # Inst execution rate
-system.cpu.iew.wb_sent 56019458 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55905490 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27772636 # num instructions producing a value
-system.cpu.iew.wb_consumers 37602554 # num instructions consuming a value
+system.cpu.iew.exec_nop 3524453 # number of nop insts executed
+system.cpu.iew.exec_refs 16609334 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8926219 # Number of branches executed
+system.cpu.iew.exec_stores 6619832 # Number of stores executed
+system.cpu.iew.exec_rate 0.518154 # Inst execution rate
+system.cpu.iew.wb_sent 56008573 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55894065 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27763400 # num instructions producing a value
+system.cpu.iew.wb_consumers 37619407 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.514646 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738584 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.514091 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738007 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7474791 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660927 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 568232 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79285136 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.708301 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.637990 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7499464 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660925 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 569249 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 79342393 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.707610 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.636795 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58523209 73.81% 73.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8600768 10.85% 84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4599944 5.80% 90.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2533685 3.20% 93.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1517149 1.91% 95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 606925 0.77% 96.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 524667 0.66% 97.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 525488 0.66% 97.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1853301 2.34% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58576225 73.83% 73.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8604152 10.84% 84.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4604262 5.80% 90.47% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::6 525202 0.66% 97.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 528895 0.67% 97.67% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79285136 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56157758 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52008025 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740393 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1853301 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 140814788 # The number of ROB reads
-system.cpu.rob.rob_writes 128509305 # The number of ROB writes
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-system.cpu.idleCycles 28101484 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3599985419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52967561 # Number of Instructions Simulated
-system.cpu.committedOps 52967561 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52967561 # Number of Instructions Simulated
-system.cpu.cpi 2.050860 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.050860 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.487600 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.487600 # IPC: Total IPC of All Threads
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-system.cpu.misc_regfile_reads 1987247 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938923 # number of misc regfile writes
+system.cpu.rob.rob_reads 140888897 # The number of ROB reads
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+system.cpu.quiesceCycles 3599901445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52953842 # Number of Instructions Simulated
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+system.cpu.committedInsts_total 52953842 # Number of Instructions Simulated
+system.cpu.cpi 2.053184 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.053184 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.487048 # IPC: Instructions Per Cycle
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system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1008504 # number of replacements
-system.cpu.icache.tagsinuse 510.288693 # Cycle average of tags in use
-system.cpu.icache.total_refs 7484267 # Total number of references to valid blocks.
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-system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.288693 # Average occupied blocks per requestor
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-system.cpu.icache.ReadReq_miss_latency::total 14670837493 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 14670837493 # number of overall miss cycles
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-system.cpu.icache.demand_accesses::total 8549153 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 13776.921915 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13776.921915 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency
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+system.cpu.icache.ReadReq_accesses::cpu.inst 8551940 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency
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+system.cpu.icache.avg_blocked_cycles::no_targets 489 # average number of cycles each access was blocked
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-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55656 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 55656 # number of demand (read+write) MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 1009229 # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 12029446495 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12029446495 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12029446495 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11919.441965 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11919.441965 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11919.441965 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11919.441965 # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11933.206773 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 338273 # number of replacements
-system.cpu.l2cache.tagsinuse 65365.869534 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2544201 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 403437 # Sample count of references to valid blocks.
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+system.cpu.l2cache.replacements 338326 # number of replacements
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system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 53972.455267 # Average occupied blocks per requestor
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-system.cpu.l2cache.occ_blocks::cpu.data 6070.335995 # Average occupied blocks per requestor
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-system.cpu.l2cache.Writeback_hits::total 840363 # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248776 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136919 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.606557 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.606557 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383718 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.167711 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.167711 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.596151 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.904618 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.173689 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14257.621622 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333774000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1400618 # number of replacements
-system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use
-system.cpu.dcache.total_refs 11803573 # Total number of references to valid blocks.
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-system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor
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+system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
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system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 2192171 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 95789 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.885415 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26433.448653 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26433.448653 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2202746 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 95919 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.964647 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 840363 # number of writebacks
-system.cpu.dcache.writebacks::total 840363 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719064 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 719064 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642999 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1642999 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5119 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5119 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2362063 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2362063 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2362063 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2362063 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083592 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1083592 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300126 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300126 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17552 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17552 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1383718 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1383718 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1383718 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1383718 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21332679000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21332679000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9855100772 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9855100772 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200264000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200264000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 56000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187779772 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31187779772 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187779772 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31187779772 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423903500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423903500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997763498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997763498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421666998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421666998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048829 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048829 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083954 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083954 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091351 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091351 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19687.003042 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19687.003042 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32836.544558 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32836.544558 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11409.753874 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11409.753874 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 840029 # number of writebacks
+system.cpu.dcache.writebacks::total 840029 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717621 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 717621 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642056 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1642056 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5266 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5266 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2359677 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2359677 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2359677 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2359677 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083247 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1083247 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300208 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300208 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17477 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17477 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1383455 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1383455 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1383455 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1383455 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21329073000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21329073000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9889442761 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9889442761 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199091500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199091500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31218515761 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 31218515761 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31218515761 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31218515761 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423851000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423851000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997662998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997662998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421513998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421513998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120254 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120254 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048852 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048852 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083710 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083710 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091298 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091298 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19689.944214 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19689.944214 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32941.969438 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32941.969438 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11391.628998 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11391.628998 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16750 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16750 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211000 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182231 # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1818337876500 98.06% 98.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 63843000 0.00% 98.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 549015500 0.03% 98.09% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 35358867000 1.91% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1854309602000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1818345164500 98.06% 98.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 63914000 0.00% 98.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 557987500 0.03% 98.09% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 35348021500 1.91% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1854315087500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815438 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175116 91.23% 93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191960 # number of callpals executed
+system.cpu.kern.callpal::total 191959 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1911
-system.cpu.kern.mode_good::user 1741
+system.cpu.kern.mode_good::kernel 1910
+system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326723 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.394549 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29457658500 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2706866000 0.15% 1.73% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1822145069500 98.27% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 29469027500 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2713167500 0.15% 1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1822132884500 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/projects/pd/randd/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:38
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 23:27:13
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 2000000000. Starting simulation...
+info: Entering event queue @ 2000003000. Starting simulation...
switching cpus
-info: Entering event queue @ 2000001000. Starting simulation...
+info: Entering event queue @ 2000005500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000001000. Starting simulation...
-info: Entering event queue @ 3000043000. Starting simulation...
+info: Entering event queue @ 3000005500. Starting simulation...
switching cpus
-info: Entering event queue @ 3000047500. Starting simulation...
+info: Entering event queue @ 3000041000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 4000047500. Starting simulation...
+info: Entering event queue @ 4000041000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 5000047500. Starting simulation...
+info: Entering event queue @ 5000041000. Starting simulation...
+info: Entering event queue @ 5000053000. Starting simulation...
switching cpus
-info: Entering event queue @ 5000048000. Starting simulation...
+info: Entering event queue @ 5000056500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000048000. Starting simulation...
-info: Entering event queue @ 7452589500. Starting simulation...
-info: Entering event queue @ 7452657000. Starting simulation...
+info: Entering event queue @ 6000056500. Starting simulation...
+info: Entering event queue @ 7458944500. Starting simulation...
+info: Entering event queue @ 7459012000. Starting simulation...
switching cpus
-info: Entering event queue @ 7452661500. Starting simulation...
+info: Entering event queue @ 7459016500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 8452661500. Starting simulation...
+info: Entering event queue @ 8459016500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 9452661500. Starting simulation...
-info: Entering event queue @ 9452675500. Starting simulation...
+info: Entering event queue @ 9459016500. Starting simulation...
switching cpus
-info: Entering event queue @ 9452679000. Starting simulation...
+info: Entering event queue @ 9459024000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 10452679000. Starting simulation...
+info: Entering event queue @ 10459024000. Starting simulation...
switching cpus
-info: Entering event queue @ 10452682000. Starting simulation...
+info: Entering event queue @ 10459031500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 11452682000. Starting simulation...
+info: Entering event queue @ 11459031500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 12452682000. Starting simulation...
-info: Entering event queue @ 12452693500. Starting simulation...
+info: Entering event queue @ 12459031500. Starting simulation...
+info: Entering event queue @ 12459047000. Starting simulation...
switching cpus
-info: Entering event queue @ 12452696000. Starting simulation...
+info: Entering event queue @ 12459242750. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 13452696000. Starting simulation...
+info: Entering event queue @ 13459242750. Starting simulation...
+info: Entering event queue @ 13459250250. Starting simulation...
+info: Entering event queue @ 13459254000. Starting simulation...
switching cpus
-info: Entering event queue @ 13452709500. Starting simulation...
+info: Entering event queue @ 13459258500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 14452709500. Starting simulation...
+info: Entering event queue @ 14459258500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 15452709500. Starting simulation...
-info: Entering event queue @ 15452713500. Starting simulation...
+info: Entering event queue @ 15459258500. Starting simulation...
switching cpus
-info: Entering event queue @ 15452714500. Starting simulation...
+info: Entering event queue @ 15459266000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 16452714500. Starting simulation...
+info: Entering event queue @ 16459266000. Starting simulation...
switching cpus
-info: Entering event queue @ 16452717000. Starting simulation...
+info: Entering event queue @ 16459273500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 17452717000. Starting simulation...
+info: Entering event queue @ 17459273500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 18452717000. Starting simulation...
-info: Entering event queue @ 18452728500. Starting simulation...
+info: Entering event queue @ 18459273500. Starting simulation...
+info: Entering event queue @ 18459284000. Starting simulation...
switching cpus
-info: Entering event queue @ 18452732000. Starting simulation...
+info: Entering event queue @ 18459287500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 19452732000. Starting simulation...
-info: Entering event queue @ 19452741000. Starting simulation...
+info: Entering event queue @ 19459287500. Starting simulation...
switching cpus
-info: Entering event queue @ 19452745500. Starting simulation...
+info: Entering event queue @ 19459295000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 20452745500. Starting simulation...
+info: Entering event queue @ 20459295000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 21452745500. Starting simulation...
+info: Entering event queue @ 21459295000. Starting simulation...
switching cpus
-info: Entering event queue @ 21452746000. Starting simulation...
+info: Entering event queue @ 21459296000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 22452746000. Starting simulation...
+info: Entering event queue @ 22459296000. Starting simulation...
switching cpus
-info: Entering event queue @ 22452748000. Starting simulation...
+info: Entering event queue @ 22459303500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 23452748000. Starting simulation...
+info: Entering event queue @ 23459303500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 24452748000. Starting simulation...
+info: Entering event queue @ 24459303500. Starting simulation...
switching cpus
-info: Entering event queue @ 24452750000. Starting simulation...
+info: Entering event queue @ 24459311000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 25452750000. Starting simulation...
-info: Entering event queue @ 25452773000. Starting simulation...
+info: Entering event queue @ 25459311000. Starting simulation...
+info: Entering event queue @ 25459330000. Starting simulation...
+info: Entering event queue @ 25459339500. Starting simulation...
+info: Entering event queue @ 25459344000. Starting simulation...
switching cpus
-info: Entering event queue @ 25452778500. Starting simulation...
+info: Entering event queue @ 25459345000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 26452778500. Starting simulation...
+info: Entering event queue @ 26459345000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 27452778500. Starting simulation...
-info: Entering event queue @ 27452782500. Starting simulation...
+info: Entering event queue @ 27459345000. Starting simulation...
+info: Entering event queue @ 27459352500. Starting simulation...
switching cpus
-info: Entering event queue @ 27452786000. Starting simulation...
+info: Entering event queue @ 27459355500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 28452786000. Starting simulation...
-info: Entering event queue @ 28452802500. Starting simulation...
+info: Entering event queue @ 28459355500. Starting simulation...
+info: Entering event queue @ 28459377000. Starting simulation...
switching cpus
-info: Entering event queue @ 28452808000. Starting simulation...
+info: Entering event queue @ 28459573000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 29452808000. Starting simulation...
+info: Entering event queue @ 29459573000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 30452808000. Starting simulation...
+info: Entering event queue @ 30459573000. Starting simulation...
switching cpus
-info: Entering event queue @ 30452820500. Starting simulation...
+info: Entering event queue @ 30459580500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 31452820500. Starting simulation...
+info: Entering event queue @ 31459580500. Starting simulation...
+info: Entering event queue @ 31459590000. Starting simulation...
switching cpus
-info: Entering event queue @ 31452823500. Starting simulation...
+info: Entering event queue @ 31459594500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 32452823500. Starting simulation...
+info: Entering event queue @ 32459594500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 33452823500. Starting simulation...
+info: Entering event queue @ 33459594500. Starting simulation...
switching cpus
-info: Entering event queue @ 33452824500. Starting simulation...
+info: Entering event queue @ 33459602000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 34452824500. Starting simulation...
+info: Entering event queue @ 34459602000. Starting simulation...
switching cpus
-info: Entering event queue @ 34452827500. Starting simulation...
+info: Entering event queue @ 34459605000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 35452827500. Starting simulation...
+info: Entering event queue @ 35459605000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 36452827500. Starting simulation...
+info: Entering event queue @ 36459605000. Starting simulation...
switching cpus
-info: Entering event queue @ 36452828500. Starting simulation...
+info: Entering event queue @ 36459612500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 37452828500. Starting simulation...
+info: Entering event queue @ 37459612500. Starting simulation...
switching cpus
-info: Entering event queue @ 37452831500. Starting simulation...
+info: Entering event queue @ 37459615500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 38452831500. Starting simulation...
+info: Entering event queue @ 38459615500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 39452831500. Starting simulation...
+info: Entering event queue @ 39459615500. Starting simulation...
switching cpus
-info: Entering event queue @ 39452832500. Starting simulation...
+info: Entering event queue @ 39459623000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 40452832500. Starting simulation...
+info: Entering event queue @ 40459623000. Starting simulation...
switching cpus
-info: Entering event queue @ 40452835500. Starting simulation...
+info: Entering event queue @ 40459626000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 41452835500. Starting simulation...
+info: Entering event queue @ 41459626000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 42452835500. Starting simulation...
+info: Entering event queue @ 42459626000. Starting simulation...
switching cpus
-info: Entering event queue @ 42452836500. Starting simulation...
+info: Entering event queue @ 42459633500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 43452836500. Starting simulation...
+info: Entering event queue @ 43459633500. Starting simulation...
switching cpus
info: Entering event queue @ 43945335500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 304757835500. Starting simulation...
switching cpus
-info: Entering event queue @ 304758051500. Starting simulation...
+info: Entering event queue @ 304757908000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 305758051500. Starting simulation...
+info: Entering event queue @ 305757908000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 306758051500. Starting simulation...
+info: Entering event queue @ 306757908000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 307758051500. Starting simulation...
+info: Entering event queue @ 307757908000. Starting simulation...
switching cpus
info: Entering event queue @ 308593773000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 568406273000. Starting simulation...
switching cpus
-info: Entering event queue @ 568406301000. Starting simulation...
+info: Entering event queue @ 568406377000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569406301000. Starting simulation...
+info: Entering event queue @ 569406377000. Starting simulation...
switching cpus
info: Entering event queue @ 570312523000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 624093773500. Starting simulation...
switching cpus
-info: Entering event queue @ 624218766000. Starting simulation...
+info: Entering event queue @ 624218753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 625218766000. Starting simulation...
+info: Entering event queue @ 625218753000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 626218766000. Starting simulation...
+info: Entering event queue @ 626218753000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 627218766000. Starting simulation...
+info: Entering event queue @ 627218753000. Starting simulation...
switching cpus
info: Entering event queue @ 627929709000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 735398460500. Starting simulation...
switching cpus
-info: Entering event queue @ 735398461500. Starting simulation...
+info: Entering event queue @ 735398468000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 736398461500. Starting simulation...
+info: Entering event queue @ 736398468000. Starting simulation...
switching cpus
info: Entering event queue @ 737304710500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 840867210500. Starting simulation...
switching cpus
-info: Entering event queue @ 840867211500. Starting simulation...
+info: Entering event queue @ 840867218000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 841867211500. Starting simulation...
+info: Entering event queue @ 841867218000. Starting simulation...
switching cpus
info: Entering event queue @ 842773460500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 946335960500. Starting simulation...
switching cpus
-info: Entering event queue @ 946335961500. Starting simulation...
+info: Entering event queue @ 946335968000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 947335961500. Starting simulation...
+info: Entering event queue @ 947335968000. Starting simulation...
switching cpus
info: Entering event queue @ 948242210500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1157273460500. Starting simulation...
switching cpus
-info: Entering event queue @ 1157273461000. Starting simulation...
+info: Entering event queue @ 1157273468000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1158273461000. Starting simulation...
+info: Entering event queue @ 1158273468000. Starting simulation...
switching cpus
-info: Entering event queue @ 1159361004000. Starting simulation...
+info: Entering event queue @ 1159362057000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1160361004000. Starting simulation...
+info: Entering event queue @ 1160362057000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1161361004000. Starting simulation...
+info: Entering event queue @ 1161362057000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1162361004000. Starting simulation...
+info: Entering event queue @ 1162362057000. Starting simulation...
switching cpus
-info: Entering event queue @ 1162361007000. Starting simulation...
+info: Entering event queue @ 1162362060000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1163361007000. Starting simulation...
+info: Entering event queue @ 1163362060000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1164361007000. Starting simulation...
+info: Entering event queue @ 1164362060000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1165361007000. Starting simulation...
+info: Entering event queue @ 1165362060000. Starting simulation...
switching cpus
-info: Entering event queue @ 1165361010000. Starting simulation...
+info: Entering event queue @ 1165362063000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1166361010000. Starting simulation...
+info: Entering event queue @ 1166362063000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1167361010000. Starting simulation...
+info: Entering event queue @ 1167362063000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1168361010000. Starting simulation...
+info: Entering event queue @ 1168362063000. Starting simulation...
switching cpus
info: Entering event queue @ 1168945335500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1694382835500. Starting simulation...
switching cpus
-info: Entering event queue @ 1694382836500. Starting simulation...
+info: Entering event queue @ 1694382843000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1695382836500. Starting simulation...
+info: Entering event queue @ 1695382843000. Starting simulation...
switching cpus
info: Entering event queue @ 1696289085500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1706101585500. Starting simulation...
switching cpus
-info: Entering event queue @ 1706101586500. Starting simulation...
+info: Entering event queue @ 1706101593000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1707101586500. Starting simulation...
+info: Entering event queue @ 1707101593000. Starting simulation...
switching cpus
info: Entering event queue @ 1708007835500. Starting simulation...
Switching CPUs...
info: Entering event queue @ 1744164085500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-switching cpus
info: Entering event queue @ 1745164085500. Starting simulation...
+switching cpus
+info: Entering event queue @ 1745164093000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1746164085500. Starting simulation...
+info: Entering event queue @ 1746164093000. Starting simulation...
switching cpus
info: Entering event queue @ 1747070335500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1768601585500. Starting simulation...
switching cpus
-info: Entering event queue @ 1768601735500. Starting simulation...
+info: Entering event queue @ 1768601593000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769601735500. Starting simulation...
+info: Entering event queue @ 1769601593000. Starting simulation...
switching cpus
info: Entering event queue @ 1770507835500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1777414085500. Starting simulation...
switching cpus
-info: Entering event queue @ 1777414674000. Starting simulation...
+info: Entering event queue @ 1777415067000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1778414674000. Starting simulation...
+info: Entering event queue @ 1778415067000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1779414674000. Starting simulation...
+info: Entering event queue @ 1779415067000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1780414674000. Starting simulation...
+info: Entering event queue @ 1780415067000. Starting simulation...
switching cpus
info: Entering event queue @ 1781250023000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1783250023000. Starting simulation...
switching cpus
-info: Entering event queue @ 1783250024000. Starting simulation...
+info: Entering event queue @ 1783250030500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1784250024000. Starting simulation...
+info: Entering event queue @ 1784250030500. Starting simulation...
switching cpus
info: Entering event queue @ 1785156273000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1794968773000. Starting simulation...
switching cpus
-info: Entering event queue @ 1794968774000. Starting simulation...
+info: Entering event queue @ 1794968780500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1795968774000. Starting simulation...
+info: Entering event queue @ 1795968780500. Starting simulation...
switching cpus
info: Entering event queue @ 1796875023000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1806687523000. Starting simulation...
switching cpus
-info: Entering event queue @ 1806687524000. Starting simulation...
+info: Entering event queue @ 1806687530500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1807687524000. Starting simulation...
+info: Entering event queue @ 1807687530500. Starting simulation...
switching cpus
info: Entering event queue @ 1808593773000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1818406273000. Starting simulation...
switching cpus
-info: Entering event queue @ 1818406274000. Starting simulation...
+info: Entering event queue @ 1818406280500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819406274000. Starting simulation...
+info: Entering event queue @ 1819406280500. Starting simulation...
switching cpus
-info: Entering event queue @ 1819406403500. Starting simulation...
+info: Entering event queue @ 1819406919000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1820406403500. Starting simulation...
+info: Entering event queue @ 1820406919000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1821406403500. Starting simulation...
+info: Entering event queue @ 1821406919000. Starting simulation...
switching cpus
-info: Entering event queue @ 1821406404500. Starting simulation...
+info: Entering event queue @ 1821406926500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1822406404500. Starting simulation...
+info: Entering event queue @ 1822406926500. Starting simulation...
switching cpus
-info: Entering event queue @ 1822406407500. Starting simulation...
+info: Entering event queue @ 1822406934000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1823406407500. Starting simulation...
+info: Entering event queue @ 1823406934000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1824406407500. Starting simulation...
+info: Entering event queue @ 1824406934000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1825406407500. Starting simulation...
+info: Entering event queue @ 1825406934000. Starting simulation...
switching cpus
info: Entering event queue @ 1826171898000. Starting simulation...
Switching CPUs...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1829171898000. Starting simulation...
-info: Entering event queue @ 1829171913500. Starting simulation...
+info: Entering event queue @ 1829171905500. Starting simulation...
+info: Entering event queue @ 1829171910500. Starting simulation...
switching cpus
-info: Entering event queue @ 1829171918000. Starting simulation...
+info: Entering event queue @ 1829171915000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1830171918000. Starting simulation...
+info: Entering event queue @ 1830171915000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1831171918000. Starting simulation...
+info: Entering event queue @ 1831171915000. Starting simulation...
switching cpus
-info: Entering event queue @ 1831171920000. Starting simulation...
+info: Entering event queue @ 1831171922500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1832171920000. Starting simulation...
+info: Entering event queue @ 1832171922500. Starting simulation...
switching cpus
info: Entering event queue @ 1833007835500. Starting simulation...
Switching CPUs...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1838914085500. Starting simulation...
-info: Entering event queue @ 1838914092000. Starting simulation...
+info: Entering event queue @ 1838914097000. Starting simulation...
switching cpus
-info: Entering event queue @ 1838914095500. Starting simulation...
+info: Entering event queue @ 1838914100500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839914095500. Starting simulation...
-info: Entering event queue @ 1839914105000. Starting simulation...
+info: Entering event queue @ 1839914100500. Starting simulation...
+info: Entering event queue @ 1839914110000. Starting simulation...
switching cpus
-info: Entering event queue @ 1839914109500. Starting simulation...
+info: Entering event queue @ 1839914114500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1840914109500. Starting simulation...
+info: Entering event queue @ 1840914114500. Starting simulation...
---------- Begin Simulation Statistics ----------
-sim_seconds 1.841686 # Number of seconds simulated
-sim_ticks 1841685557500 # Number of ticks simulated
-final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.841723 # Number of seconds simulated
+sim_ticks 1841722715000 # Number of ticks simulated
+final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 257826 # Simulator instruction rate (inst/s)
-host_op_rate 257826 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6831790357 # Simulator tick rate (ticks/s)
-host_mem_usage 316032 # Number of bytes of host memory used
-host_seconds 269.58 # Real time elapsed on the host
-sim_insts 69503534 # Number of instructions simulated
-sim_ops 69503534 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 109963 # Total number of read requests seen
-system.physmem.writeReqs 45515 # Total number of write requests seen
-system.physmem.cpureqs 155519 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 7037632 # Total number of bytes read from memory
-system.physmem.bytesWritten 2912960 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis
+host_inst_rate 105391 # Simulator instruction rate (inst/s)
+host_op_rate 105391 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2775370642 # Simulator tick rate (ticks/s)
+host_mem_usage 350548 # Number of bytes of host memory used
+host_seconds 663.60 # Real time elapsed on the host
+sim_insts 69936964 # Number of instructions simulated
+sim_ops 69936964 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 109804 # Total number of read requests seen
+system.physmem.writeReqs 45341 # Total number of write requests seen
+system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 7027456 # Total number of bytes read from memory
+system.physmem.bytesWritten 2901824 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1840673470000 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1840710411000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 109963 # Categorize read packet sizes
+system.physmem.readPktSize::6 109804 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 45515 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 45341 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed
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system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl
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system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
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system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
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system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
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system.cpu0.kern.mode_good::user 1739
-system.cpu0.kern.mode_good::idle 170
-system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches
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-system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode
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-system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
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+system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 953667 # number of replacements
-system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use
-system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks.
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-system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 255.638706 # Average occupied blocks per requestor
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1221793 # DTB read hits
-system.cpu1.dtb.read_misses 1550 # DTB read misses
-system.cpu1.dtb.read_acv 45 # DTB read access violations
-system.cpu1.dtb.read_accesses 143987 # DTB read accesses
-system.cpu1.dtb.write_hits 928954 # DTB write hits
-system.cpu1.dtb.write_misses 206 # DTB write misses
+system.cpu1.dtb.read_hits 1221293 # DTB read hits
+system.cpu1.dtb.read_misses 1489 # DTB read misses
+system.cpu1.dtb.read_acv 40 # DTB read access violations
+system.cpu1.dtb.read_accesses 143781 # DTB read accesses
+system.cpu1.dtb.write_hits 930282 # DTB write hits
+system.cpu1.dtb.write_misses 202 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
-system.cpu1.dtb.write_accesses 60098 # DTB write accesses
-system.cpu1.dtb.data_hits 2150747 # DTB hits
-system.cpu1.dtb.data_misses 1756 # DTB misses
-system.cpu1.dtb.data_acv 69 # DTB access violations
-system.cpu1.dtb.data_accesses 204085 # DTB accesses
-system.cpu1.itb.fetch_hits 875028 # ITB hits
-system.cpu1.itb.fetch_misses 772 # ITB misses
-system.cpu1.itb.fetch_acv 46 # ITB acv
-system.cpu1.itb.fetch_accesses 875800 # ITB accesses
+system.cpu1.dtb.write_accesses 59266 # DTB write accesses
+system.cpu1.dtb.data_hits 2151575 # DTB hits
+system.cpu1.dtb.data_misses 1691 # DTB misses
+system.cpu1.dtb.data_acv 64 # DTB access violations
+system.cpu1.dtb.data_accesses 203047 # DTB accesses
+system.cpu1.itb.fetch_hits 872259 # ITB hits
+system.cpu1.itb.fetch_misses 756 # ITB misses
+system.cpu1.itb.fetch_acv 43 # ITB acv
+system.cpu1.itb.fetch_accesses 873015 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953543873 # number of cpu cycles simulated
+system.cpu1.numCycles 953618286 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7871049 # Number of instructions committed
-system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses
-system.cpu1.num_func_calls 212361 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7322486 # number of integer instructions
-system.cpu1.num_fp_insts 45486 # number of float instructions
-system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2158619 # number of memory refs
-system.cpu1.num_load_insts 1227197 # Number of load instructions
-system.cpu1.num_store_insts 931422 # Number of store instructions
-system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles
-system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles
-system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles
-system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles
+system.cpu1.committedInsts 7861577 # Number of instructions committed
+system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses
+system.cpu1.num_func_calls 212083 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7312995 # number of integer instructions
+system.cpu1.num_fp_insts 45507 # number of float instructions
+system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2159267 # number of memory refs
+system.cpu1.num_load_insts 1226545 # Number of load instructions
+system.cpu1.num_store_insts 932722 # Number of store instructions
+system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles
+system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles
+system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles
+system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 8388883 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits
+system.cpu2.branchPred.lookups 8378030 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3222753 # DTB read hits
-system.cpu2.dtb.read_misses 11767 # DTB read misses
-system.cpu2.dtb.read_acv 114 # DTB read access violations
-system.cpu2.dtb.read_accesses 216394 # DTB read accesses
-system.cpu2.dtb.write_hits 1997746 # DTB write hits
-system.cpu2.dtb.write_misses 2597 # DTB write misses
-system.cpu2.dtb.write_acv 133 # DTB write access violations
-system.cpu2.dtb.write_accesses 81219 # DTB write accesses
-system.cpu2.dtb.data_hits 5220499 # DTB hits
-system.cpu2.dtb.data_misses 14364 # DTB misses
-system.cpu2.dtb.data_acv 247 # DTB access violations
-system.cpu2.dtb.data_accesses 297613 # DTB accesses
-system.cpu2.itb.fetch_hits 371919 # ITB hits
-system.cpu2.itb.fetch_misses 5650 # ITB misses
-system.cpu2.itb.fetch_acv 270 # ITB acv
-system.cpu2.itb.fetch_accesses 377569 # ITB accesses
+system.cpu2.dtb.read_hits 3213070 # DTB read hits
+system.cpu2.dtb.read_misses 11858 # DTB read misses
+system.cpu2.dtb.read_acv 125 # DTB read access violations
+system.cpu2.dtb.read_accesses 216838 # DTB read accesses
+system.cpu2.dtb.write_hits 1985729 # DTB write hits
+system.cpu2.dtb.write_misses 2626 # DTB write misses
+system.cpu2.dtb.write_acv 132 # DTB write access violations
+system.cpu2.dtb.write_accesses 82100 # DTB write accesses
+system.cpu2.dtb.data_hits 5198799 # DTB hits
+system.cpu2.dtb.data_misses 14484 # DTB misses
+system.cpu2.dtb.data_acv 257 # DTB access violations
+system.cpu2.dtb.data_accesses 298938 # DTB accesses
+system.cpu2.itb.fetch_hits 371799 # ITB hits
+system.cpu2.itb.fetch_misses 5527 # ITB misses
+system.cpu2.itb.fetch_acv 268 # ITB acv
+system.cpu2.itb.fetch_accesses 377326 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 30487191 # number of cpu cycles simulated
+system.cpu2.numCycles 30456501 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued
-system.cpu2.iq.rate 0.995088 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued
+system.cpu2.iq.rate 0.994264 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1285615 # number of nop insts executed
-system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 6797242 # Number of branches executed
-system.cpu2.iew.exec_stores 2004831 # Number of stores executed
-system.cpu2.iew.exec_rate 0.989710 # Inst execution rate
-system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17352028 # num instructions producing a value
-system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1279986 # number of nop insts executed
+system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 6791959 # Number of branches executed
+system.cpu2.iew.exec_stores 1992832 # Number of stores executed
+system.cpu2.iew.exec_rate 0.989003 # Inst execution rate
+system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 17325737 # num instructions producing a value
+system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 30289973 # Number of instructions committed
-system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 30241196 # Number of instructions committed
+system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4894371 # Number of memory references committed
-system.cpu2.commit.loads 2968099 # Number of loads committed
-system.cpu2.commit.membars 65019 # Number of memory barriers committed
-system.cpu2.commit.branches 6647353 # Number of branches committed
-system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 231619 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 4874767 # Number of memory references committed
+system.cpu2.commit.loads 2959021 # Number of loads committed
+system.cpu2.commit.membars 64729 # Number of memory barriers committed
+system.cpu2.commit.branches 6642526 # Number of branches committed
+system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 230913 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 58337288 # The number of ROB reads
-system.cpu2.rob.rob_writes 65718838 # The number of ROB writes
-system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 29114232 # Number of Instructions Simulated
-system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated
-system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads
-system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes
+system.cpu2.rob.rob_reads 58235962 # The number of ROB reads
+system.cpu2.rob.rob_writes 65598028 # The number of ROB writes
+system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 29069459 # Number of Instructions Simulated
+system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated
+system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads
+system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=False
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 5720641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5728757500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5763076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5777835500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6298513500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 5695245000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
+warn: 5701912500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5710381500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5745167500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5760086500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6281852500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 52553050000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: 2291164927000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 52533955500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 2291148077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
-warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2497502713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2498707539500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2520262039500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2525942762500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2526449392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2527008451000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2527009567500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2527556775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
+warn: 2483713797000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2498675085000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2519713161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2520226805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2525908166000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2526415429500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2526974192500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2526975291500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
hack: be nice to actually delete the event here
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 25 2013 18:24:48
-gem5 started Feb 25 2013 22:59:32
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 01:26:55
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2533144795000 because m5_exit instruction encountered
+Exiting @ tick 2533114761500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533141 # Number of seconds simulated
-sim_ticks 2533140518500 # Number of ticks simulated
-final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533115 # Number of seconds simulated
+sim_ticks 2533114761500 # Number of ticks simulated
+final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 42664 # Simulator instruction rate (inst/s)
-host_op_rate 54897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1792038006 # Simulator tick rate (ticks/s)
-host_mem_usage 435912 # Number of bytes of host memory used
-host_seconds 1413.55 # Real time elapsed on the host
-sim_insts 60307702 # Number of instructions simulated
-sim_ops 77599241 # Number of ops (including micro ops) simulated
+host_inst_rate 19921 # Simulator instruction rate (inst/s)
+host_op_rate 25633 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 836738491 # Simulator tick rate (ticks/s)
+host_mem_usage 439300 # Number of bytes of host memory used
+host_seconds 3027.37 # Real time elapsed on the host
+sim_insts 60307912 # Number of instructions simulated
+sim_ops 77599507 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096807 # Total number of read requests seen
-system.physmem.writeReqs 813124 # Total number of write requests seen
-system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195648 # Total number of bytes read from memory
-system.physmem.bytesWritten 52039936 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096833 # Total number of read requests seen
+system.physmem.writeReqs 813132 # Total number of write requests seen
+system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966197312 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533139407500 # Total gap between requests
+system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533113625500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154563 # Categorize read packet sizes
+system.physmem.readPktSize::6 154589 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59106 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59114 # Categorize write packet sizes
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+system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see
-system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
+system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see
+system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482355000 # Total cycles spent in databus access
system.physmem.totBankLat 16909241250 # Total cycles spent in bank access
-system.physmem.avgQLat 26044.77 # Average queueing delay per request
+system.physmem.avgQLat 26046.04 # Average queueing delay per request
system.physmem.avgBankLat 1120.08 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32164.85 # Average memory access latency
-system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 32166.12 # Average memory access latency
+system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.32 # Average write queue length over time
-system.physmem.readRowHits 15020284 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793162 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 12.50 # Average write queue length over time
+system.physmem.readRowHits 15020252 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793086 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes
-system.physmem.avgGap 159217.50 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
+system.physmem.avgGap 159215.54 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14656582 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits
+system.cpu.branchPred.lookups 14667150 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987438 # DTB read hits
+system.cpu.checker.dtb.read_hits 14987498 # DTB read hits
system.cpu.checker.dtb.read_misses 7302 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227743 # DTB write hits
+system.cpu.checker.dtb.write_hits 11227787 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994740 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229932 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994800 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229976 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215181 # DTB hits
+system.cpu.checker.dtb.hits 26215285 # DTB hits
system.cpu.checker.dtb.misses 9491 # DTB misses
-system.cpu.checker.dtb.accesses 26224672 # DTB accesses
-system.cpu.checker.itb.inst_hits 61481703 # ITB inst hits
+system.cpu.checker.dtb.accesses 26224776 # DTB accesses
+system.cpu.checker.itb.inst_hits 61481914 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61486174 # ITB inst accesses
-system.cpu.checker.itb.hits 61481703 # DTB hits
+system.cpu.checker.itb.inst_accesses 61486385 # ITB inst accesses
+system.cpu.checker.itb.hits 61481914 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61486174 # DTB accesses
-system.cpu.checker.numCycles 77885049 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61486385 # DTB accesses
+system.cpu.checker.numCycles 77885316 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51396633 # DTB read hits
-system.cpu.dtb.read_misses 64067 # DTB read misses
-system.cpu.dtb.write_hits 11699653 # DTB write hits
-system.cpu.dtb.write_misses 15746 # DTB write misses
+system.cpu.dtb.read_hits 51396830 # DTB read hits
+system.cpu.dtb.read_misses 64077 # DTB read misses
+system.cpu.dtb.write_hits 11700143 # DTB write hits
+system.cpu.dtb.write_misses 15896 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51460700 # DTB read accesses
-system.cpu.dtb.write_accesses 11715399 # DTB write accesses
+system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51460907 # DTB read accesses
+system.cpu.dtb.write_accesses 11716039 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63096286 # DTB hits
-system.cpu.dtb.misses 79813 # DTB misses
-system.cpu.dtb.accesses 63176099 # DTB accesses
-system.cpu.itb.inst_hits 12325480 # ITB inst hits
-system.cpu.itb.inst_misses 11172 # ITB inst misses
+system.cpu.dtb.hits 63096973 # DTB hits
+system.cpu.dtb.misses 79973 # DTB misses
+system.cpu.dtb.accesses 63176946 # DTB accesses
+system.cpu.itb.inst_hits 12326910 # ITB inst hits
+system.cpu.itb.inst_misses 11389 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 4964 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12336652 # ITB inst accesses
-system.cpu.itb.hits 12325480 # DTB hits
-system.cpu.itb.misses 11172 # DTB misses
-system.cpu.itb.accesses 12336652 # DTB accesses
-system.cpu.numCycles 471810648 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12338299 # ITB inst accesses
+system.cpu.itb.hits 12326910 # DTB hits
+system.cpu.itb.misses 11389 # DTB misses
+system.cpu.itb.accesses 12338299 # DTB accesses
+system.cpu.numCycles 471812928 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.535276 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued
-system.cpu.iq.rate 0.263438 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued
+system.cpu.iq.rate 0.263458 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221429 # number of nop insts executed
-system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11545908 # Number of branches executed
-system.cpu.iew.exec_stores 12211356 # Number of stores executed
-system.cpu.iew.exec_rate 0.257527 # Inst execution rate
-system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47220023 # num instructions producing a value
-system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value
+system.cpu.iew.exec_nop 221256 # number of nop insts executed
+system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11548935 # Number of branches executed
+system.cpu.iew.exec_stores 12211863 # Number of stores executed
+system.cpu.iew.exec_rate 0.257542 # Inst execution rate
+system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47248906 # num instructions producing a value
+system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458083 # Number of instructions committed
-system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed
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-system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated
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system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads
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+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=False
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 25 2013 18:24:48
-gem5 started Feb 25 2013 23:05:46
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:41:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1102934903000 because m5_exit instruction encountered
+Exiting @ tick 2602778916500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.102937 # Number of seconds simulated
-sim_ticks 1102936899000 # Number of ticks simulated
-final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.602779 # Number of seconds simulated
+sim_ticks 2602778916500 # Number of ticks simulated
+final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56405 # Simulator instruction rate (inst/s)
-host_op_rate 72609 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1010130266 # Simulator tick rate (ticks/s)
-host_mem_usage 440004 # Number of bytes of host memory used
-host_seconds 1091.88 # Real time elapsed on the host
-sim_insts 61587196 # Number of instructions simulated
-sim_ops 79280303 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
+host_inst_rate 24161 # Simulator instruction rate (inst/s)
+host_op_rate 31106 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1001764915 # Simulator tick rate (ticks/s)
+host_mem_usage 444424 # Number of bytes of host memory used
+host_seconds 2598.19 # Real time elapsed on the host
+sim_insts 62774383 # Number of instructions simulated
+sim_ops 80820330 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 395584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4382196 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 426624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5245232 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131562340 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 395584 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 426624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 822208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4273600 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7302736 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6181 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68544 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6666 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 81983 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15302224 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66775 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257533 # Total number of read requests seen
-system.physmem.writeReqs 823123 # Total number of write requests seen
-system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 400482112 # Total number of bytes read from memory
-system.physmem.bytesWritten 52679872 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis
+system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 824059 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46531239 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 151985 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1683660 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 163911 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2015243 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50546875 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 151985 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 163911 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315896 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1641937 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6531 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 1157277 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2805746 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1641937 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46531239 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 151985 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1690192 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 163911 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3172520 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53352621 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15302224 # Total number of read requests seen
+system.physmem.writeReqs 824059 # Total number of write requests seen
+system.physmem.cpureqs 244149 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 979342336 # Total number of bytes read from memory
+system.physmem.bytesWritten 52739776 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 131562340 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7302736 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 337 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 14071 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 956809 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 956626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 956229 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 956838 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 956744 # Track reads on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1102935703000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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-system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.21 # Data bus utilization in percentage
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-system.physmem.avgWrQLen 11.59 # Average write queue length over time
-system.physmem.readRowHits 6213376 # Number of row buffer hits during reads
-system.physmem.writeRowHits 799550 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes
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-system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
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-system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.Writeback_hits::total 581284 # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data 780 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1976 # number of UpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.data 58735 # number of ReadExReq hits
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+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 6001640 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits
+system.cpu0.branchPred.lookups 6065134 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4623218 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 295247 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3783915 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2943990 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.802752 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 682666 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28697 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8910999 # DTB read hits
-system.cpu0.dtb.read_misses 29151 # DTB read misses
-system.cpu0.dtb.write_hits 5140269 # DTB write hits
-system.cpu0.dtb.write_misses 5702 # DTB write misses
+system.cpu0.dtb.read_hits 8964880 # DTB read hits
+system.cpu0.dtb.read_misses 29505 # DTB read misses
+system.cpu0.dtb.write_hits 5211507 # DTB write hits
+system.cpu0.dtb.write_misses 5768 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1820 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1111 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 256 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8940150 # DTB read accesses
-system.cpu0.dtb.write_accesses 5145971 # DTB write accesses
+system.cpu0.dtb.perms_faults 587 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8994385 # DTB read accesses
+system.cpu0.dtb.write_accesses 5217275 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14051268 # DTB hits
-system.cpu0.dtb.misses 34853 # DTB misses
-system.cpu0.dtb.accesses 14086121 # DTB accesses
-system.cpu0.itb.inst_hits 4221147 # ITB inst hits
-system.cpu0.itb.inst_misses 5166 # ITB inst misses
+system.cpu0.dtb.hits 14176387 # DTB hits
+system.cpu0.dtb.misses 35273 # DTB misses
+system.cpu0.dtb.accesses 14211660 # DTB accesses
+system.cpu0.itb.inst_hits 4271941 # ITB inst hits
+system.cpu0.itb.inst_misses 5082 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1340 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1395 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses
-system.cpu0.itb.hits 4221147 # DTB hits
-system.cpu0.itb.misses 5166 # DTB misses
-system.cpu0.itb.accesses 4226313 # DTB accesses
-system.cpu0.numCycles 67826289 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4277023 # ITB inst accesses
+system.cpu0.itb.hits 4271941 # DTB hits
+system.cpu0.itb.misses 5082 # DTB misses
+system.cpu0.itb.accesses 4277023 # DTB accesses
+system.cpu0.numCycles 68310391 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11985780 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32442629 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6065134 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3626656 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7605462 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1460769 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 62659 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 21080761 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 46842 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 87230 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4270468 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 157226 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2109 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41924364 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.999512 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.380874 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34326103 81.88% 81.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 570380 1.36% 83.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 823787 1.96% 85.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 686899 1.64% 86.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 778226 1.86% 88.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 563231 1.34% 90.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 676382 1.61% 91.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 356953 0.85% 92.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3142403 7.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41924364 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088788 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.474930 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12503811 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21012915 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6898585 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 522974 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 986079 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 948336 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64663 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40543036 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 211520 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 986079 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 13078116 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5721380 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13152385 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6797650 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2188754 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39433741 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1845 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 443177 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1244404 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39808870 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 178177695 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 178143549 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34146 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31430562 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8378307 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 419823 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 376669 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5441918 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7757618 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5774212 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1139116 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1209168 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37348543 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 904610 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37701629 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 81879 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6330369 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13296779 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 257143 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41924364 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.899277 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.510411 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26590532 63.43% 63.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5818938 13.88% 77.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3210799 7.66% 84.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2498063 5.96% 90.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2114705 5.04% 95.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 942628 2.25% 98.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 502674 1.20% 99.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 189300 0.45% 99.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 56725 0.14% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41924364 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 26752 2.49% 2.49% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 840001 78.12% 80.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 208012 19.35% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
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-system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.33% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.33% # Type of FU issued
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system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued
-system.cpu0.iq.rate 0.549158 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37701629 # Type of FU issued
+system.cpu0.iq.rate 0.551916 # Inst issue rate
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+system.cpu0.iq.fu_busy_rate 0.028519 # FU busy rate (busy events/executed inst)
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+system.cpu0.iq.fp_inst_queue_reads 8242 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes
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+system.cpu0.iq.fp_alu_accesses 4288 # Number of floating point alu accesses
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system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1380313 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2666 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13062 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 544614 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2149563 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5584 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute
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+system.cpu0.iew.iewBlockCycles 4106132 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 100687 # Number of cycles IEW is unblocking
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+system.cpu0.iew.iewDispStoreInsts 5774212 # Number of dispatched store instructions
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+system.cpu0.iew.iewIQFullEvents 40897 # Number of times the IQ has become full, causing a stall
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+system.cpu0.iew.branchMispredicts 267907 # Number of branch mispredicts detected at execute
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118142 # number of nop insts executed
-system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4856874 # Number of branches executed
-system.cpu0.iew.exec_stores 5400115 # Number of stores executed
-system.cpu0.iew.exec_rate 0.543622 # Inst execution rate
-system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18291021 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118280 # number of nop insts executed
+system.cpu0.iew.exec_refs 14765828 # number of memory reference insts executed
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+system.cpu0.iew.exec_rate 0.546382 # Inst execution rate
+system.cpu0.iew.wb_sent 37128467 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34842966 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18565053 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35706535 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.510068 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.519934 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6140110 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 647467 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 231710 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 0.775989 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.737548 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29080513 71.04% 71.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5796475 14.16% 85.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1964427 4.80% 89.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 998229 2.44% 92.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 793584 1.94% 94.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 517255 1.26% 95.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 395614 0.97% 96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 224138 0.55% 97.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1168050 2.85% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle
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-system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated
-system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads
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-system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6411840492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6411840492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6411840492 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6411840492 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13437088000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13437088000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251489878 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251489878 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688577878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688577878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030152 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030152 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027193 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027193 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056490 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056490 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053487 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053487 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.639253 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.639253 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30992.884012 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30992.884012 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7973.568019 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7973.568019 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4472.458720 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4472.458720 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9057370 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits
+system.cpu1.branchPred.lookups 9260108 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7598823 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 418413 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6211409 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5330705 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 85.821188 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 799378 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 44339 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42905047 # DTB read hits
-system.cpu1.dtb.read_misses 36603 # DTB read misses
-system.cpu1.dtb.write_hits 6822006 # DTB write hits
-system.cpu1.dtb.write_misses 10721 # DTB write misses
+system.cpu1.dtb.read_hits 43181625 # DTB read hits
+system.cpu1.dtb.read_misses 38342 # DTB read misses
+system.cpu1.dtb.write_hits 6975478 # DTB write hits
+system.cpu1.dtb.write_misses 10879 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 3080 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42941650 # DTB read accesses
-system.cpu1.dtb.write_accesses 6832727 # DTB write accesses
+system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 43219967 # DTB read accesses
+system.cpu1.dtb.write_accesses 6986357 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49727053 # DTB hits
-system.cpu1.dtb.misses 47324 # DTB misses
-system.cpu1.dtb.accesses 49774377 # DTB accesses
-system.cpu1.itb.inst_hits 8402267 # ITB inst hits
-system.cpu1.itb.inst_misses 5496 # ITB inst misses
+system.cpu1.dtb.hits 50157103 # DTB hits
+system.cpu1.dtb.misses 49221 # DTB misses
+system.cpu1.dtb.accesses 50206324 # DTB accesses
+system.cpu1.itb.inst_hits 8542294 # ITB inst hits
+system.cpu1.itb.inst_misses 5605 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1533 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1566 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses
-system.cpu1.itb.hits 8402267 # DTB hits
-system.cpu1.itb.misses 5496 # DTB misses
-system.cpu1.itb.accesses 8407763 # DTB accesses
-system.cpu1.numCycles 408754758 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8547899 # ITB inst accesses
+system.cpu1.itb.hits 8542294 # DTB hits
+system.cpu1.itb.misses 5605 # DTB misses
+system.cpu1.itb.accesses 8547899 # DTB accesses
+system.cpu1.numCycles 410577330 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 20304470 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 67058817 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9260108 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6130083 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14383842 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4002399 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 71431 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77735291 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 42666 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 133916 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8540383 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 747213 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 115405308 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.704397 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.049572 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 101028811 87.54% 87.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 815655 0.71% 88.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 964627 0.84% 89.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1914792 1.66% 90.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1533608 1.33% 92.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 591916 0.51% 92.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2159319 1.87% 94.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 420670 0.36% 94.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5975910 5.18% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 115405308 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022554 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.163328 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21846277 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 77383941 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 13006148 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 540398 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2628544 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1139252 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 100555 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 76481536 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 334945 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2628544 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 23246660 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32001614 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 41094778 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 12051133 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4382579 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 70980554 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18812 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 684543 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3106754 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 398 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 74967908 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 326797465 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 326738119 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59346 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 50107015 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 24860893 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 461639 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 401710 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8025653 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13466262 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8327830 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1061558 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1475331 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 64680036 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1175419 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 90315471 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 95817 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 16379719 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 46059622 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 276388 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 115405308 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.782594 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.520017 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 84537407 73.25% 73.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8582035 7.44% 80.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4411988 3.82% 84.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3834760 3.32% 87.83% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10634435 9.21% 97.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1994605 1.73% 98.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1053936 0.91% 99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 278337 0.24% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 77805 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 115405308 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 32501 0.41% 0.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 990 0.01% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7572486 95.74% 96.16% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 303829 3.84% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 38327866 42.44% 42.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 61115 0.07% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1704 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 44265466 49.01% 91.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7345367 8.13% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued
-system.cpu1.iq.rate 0.217993 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 90315471 # Type of FU issued
+system.cpu1.iq.rate 0.219972 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7909806 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.087580 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 304076071 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 82244261 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54749584 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14863 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6852 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 97903555 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7790 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 356637 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3487877 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17725 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1325961 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31951985 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 889967 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2628544 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24227901 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 361425 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 65958607 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 113659 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13466262 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8327830 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 878933 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 66066 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3533 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17725 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 207255 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 158224 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 365479 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87865625 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43564360 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2449846 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104097 # number of nop insts executed
-system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6984824 # Number of branches executed
-system.cpu1.iew.exec_stores 7107734 # Number of stores executed
-system.cpu1.iew.exec_rate 0.212002 # Inst execution rate
-system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29912489 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value
+system.cpu1.iew.exec_nop 103152 # number of nop insts executed
+system.cpu1.iew.exec_refs 50845626 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7156733 # Number of branches executed
+system.cpu1.iew.exec_stores 7281266 # Number of stores executed
+system.cpu1.iew.exec_rate 0.214005 # Inst execution rate
+system.cpu1.iew.wb_sent 86881552 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54756436 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30516075 # num instructions producing a value
+system.cpu1.iew.wb_consumers 54547350 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.133364 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.559442 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 16276380 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899031 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 319402 # The number of times a branch was mispredicted
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+system.cpu1.commit.committed_per_cycle::mean 0.436287 # Number of insts commited each cycle
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system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 95648521 84.81% 84.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8417489 7.46% 92.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2180084 1.93% 94.21% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1287029 1.14% 95.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1270394 1.13% 96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 584036 0.52% 96.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1018862 0.90% 97.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 513430 0.46% 98.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1856919 1.65% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38055916 # Number of instructions committed
-system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 112776764 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38866915 # Number of instructions committed
+system.cpu1.commit.committedOps 49203034 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16587382 # Number of memory references committed
-system.cpu1.commit.loads 9750804 # Number of loads committed
-system.cpu1.commit.membars 190065 # Number of memory barriers committed
-system.cpu1.commit.branches 5966253 # Number of branches committed
-system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 534450 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16980254 # Number of memory references committed
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+system.cpu1.commit.branches 6118836 # Number of branches committed
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+system.cpu1.commit.int_insts 43616937 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 553185 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1856919 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 172894643 # The number of ROB reads
-system.cpu1.rob.rob_writes 131171187 # The number of ROB writes
-system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 37986277 # Number of Instructions Simulated
-system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated
-system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes
-system.cpu1.icache.replacements 596198 # number of replacements
-system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use
-system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor
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-system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy
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-system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency
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+system.cpu1.committedOps 49133395 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 38797276 # Number of Instructions Simulated
+system.cpu1.cpi 10.582633 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.582633 # CPI: Total CPI of All Threads
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system.cpu1.icache.fast_writes 0 # number of fast writes performed
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu1.dcache.overall_miss_rate::total 0.133406 # miss rate for overall accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15278.371871 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 39392.953453 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9307.149908 # average LoadLockedReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 34437.286745 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 324138 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 327755 # number of writebacks
+system.cpu1.dcache.writebacks::total 327755 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 173193 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 173193 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400907 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1400907 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1451 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1451 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574100 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1574100 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574100 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1574100 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231345 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 231345 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163062 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 163062 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12731 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12731 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10917 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10917 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 394407 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 394407 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 394407 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 394407 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2902469000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2902469000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5146576709 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5146576709 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90486500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90486500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37019500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37019500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049045709 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8049045709 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049045709 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8049045709 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298073000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298073000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35738645182 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35738645182 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 205036718182 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 205036718182 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025935 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025935 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027943 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027943 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111484 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111484 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101096 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101096 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026729 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026729 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12546.063239 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12546.063239 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31562.085029 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31562.085029 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7107.572068 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7107.572068 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3390.995695 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3390.995695 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1245278858614 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1245278858614 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 42369 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 50346 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=False
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 25 2013 18:24:48
-gem5 started Feb 25 2013 22:58:34
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:43:56
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2533144795000 because m5_exit instruction encountered
+Exiting @ tick 2533114761500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533141 # Number of seconds simulated
-sim_ticks 2533140518500 # Number of ticks simulated
-final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533115 # Number of seconds simulated
+sim_ticks 2533114761500 # Number of ticks simulated
+final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 41838 # Simulator instruction rate (inst/s)
-host_op_rate 53833 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1757330352 # Simulator tick rate (ticks/s)
-host_mem_usage 435908 # Number of bytes of host memory used
-host_seconds 1441.47 # Real time elapsed on the host
-sim_insts 60307702 # Number of instructions simulated
-sim_ops 77599241 # Number of ops (including micro ops) simulated
+host_inst_rate 24105 # Simulator instruction rate (inst/s)
+host_op_rate 31016 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1012479744 # Simulator tick rate (ticks/s)
+host_mem_usage 439308 # Number of bytes of host memory used
+host_seconds 2501.89 # Real time elapsed on the host
+sim_insts 60307912 # Number of instructions simulated
+sim_ops 77599507 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096807 # Total number of read requests seen
-system.physmem.writeReqs 813124 # Total number of write requests seen
-system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195648 # Total number of bytes read from memory
-system.physmem.bytesWritten 52039936 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096833 # Total number of read requests seen
+system.physmem.writeReqs 813132 # Total number of write requests seen
+system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966197312 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533139407500 # Total gap between requests
+system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533113625500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154563 # Categorize read packet sizes
+system.physmem.readPktSize::6 154589 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59106 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59114 # Categorize write packet sizes
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+system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8 59177 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108732 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::11 108199 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16725 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16575 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::15 12714 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2572 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::5 2762 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see
-system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
+system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see
+system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482355000 # Total cycles spent in databus access
system.physmem.totBankLat 16909241250 # Total cycles spent in bank access
-system.physmem.avgQLat 26044.77 # Average queueing delay per request
+system.physmem.avgQLat 26046.04 # Average queueing delay per request
system.physmem.avgBankLat 1120.08 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32164.85 # Average memory access latency
-system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 32166.12 # Average memory access latency
+system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.32 # Average write queue length over time
-system.physmem.readRowHits 15020284 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793162 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 12.50 # Average write queue length over time
+system.physmem.readRowHits 15020252 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793086 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes
-system.physmem.avgGap 159217.50 # Average gap between requests
+system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
+system.physmem.avgGap 159215.54 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14656582 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits
+system.cpu.branchPred.lookups 14667150 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51396633 # DTB read hits
-system.cpu.dtb.read_misses 64067 # DTB read misses
-system.cpu.dtb.write_hits 11699653 # DTB write hits
-system.cpu.dtb.write_misses 15746 # DTB write misses
+system.cpu.dtb.read_hits 51396830 # DTB read hits
+system.cpu.dtb.read_misses 64077 # DTB read misses
+system.cpu.dtb.write_hits 11700143 # DTB write hits
+system.cpu.dtb.write_misses 15896 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51460700 # DTB read accesses
-system.cpu.dtb.write_accesses 11715399 # DTB write accesses
+system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51460907 # DTB read accesses
+system.cpu.dtb.write_accesses 11716039 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63096286 # DTB hits
-system.cpu.dtb.misses 79813 # DTB misses
-system.cpu.dtb.accesses 63176099 # DTB accesses
-system.cpu.itb.inst_hits 12325480 # ITB inst hits
-system.cpu.itb.inst_misses 11172 # ITB inst misses
+system.cpu.dtb.hits 63096973 # DTB hits
+system.cpu.dtb.misses 79973 # DTB misses
+system.cpu.dtb.accesses 63176946 # DTB accesses
+system.cpu.itb.inst_hits 12326910 # ITB inst hits
+system.cpu.itb.inst_misses 11389 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2484 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12336652 # ITB inst accesses
-system.cpu.itb.hits 12325480 # DTB hits
-system.cpu.itb.misses 11172 # DTB misses
-system.cpu.itb.accesses 12336652 # DTB accesses
-system.cpu.numCycles 471810648 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12338299 # ITB inst accesses
+system.cpu.itb.hits 12326910 # DTB hits
+system.cpu.itb.misses 11389 # DTB misses
+system.cpu.itb.accesses 12338299 # DTB accesses
+system.cpu.numCycles 471812928 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued
-system.cpu.iq.rate 0.263438 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued
+system.cpu.iq.rate 0.263458 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221429 # number of nop insts executed
-system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11545908 # Number of branches executed
-system.cpu.iew.exec_stores 12211356 # Number of stores executed
-system.cpu.iew.exec_rate 0.257527 # Inst execution rate
-system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47220023 # num instructions producing a value
-system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value
+system.cpu.iew.exec_nop 221256 # number of nop insts executed
+system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11548935 # Number of branches executed
+system.cpu.iew.exec_stores 12211863 # Number of stores executed
+system.cpu.iew.exec_rate 0.257542 # Inst execution rate
+system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47248906 # num instructions producing a value
+system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458083 # Number of instructions committed
-system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147854976 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60458293 # Number of instructions committed
+system.cpu.commit.committedOps 77749888 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386631 # Number of memory references committed
-system.cpu.commit.loads 15654552 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961338 # Number of branches committed
+system.cpu.commit.refs 27386737 # Number of memory references committed
+system.cpu.commit.loads 15654612 # Number of loads committed
+system.cpu.commit.membars 403603 # Number of memory barriers committed
+system.cpu.commit.branches 9961369 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854854 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991262 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68855092 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991267 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2901187 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242306963 # The number of ROB reads
-system.cpu.rob.rob_writes 201917005 # The number of ROB writes
-system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307702 # Number of Instructions Simulated
-system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated
-system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads
+system.cpu.rob.rob_reads 242290263 # The number of ROB reads
+system.cpu.rob.rob_writes 201932483 # The number of ROB writes
+system.cpu.timesIdled 1770811 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320491858 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4594333550 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60307912 # Number of Instructions Simulated
+system.cpu.committedOps 77599507 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307912 # Number of Instructions Simulated
+system.cpu.cpi 7.823400 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.823400 # CPI: Total CPI of All Threads
system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550141263 # number of integer regfile reads
-system.cpu.int_regfile_writes 88418139 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8398 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2928 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831893 # number of misc regfile writes
-system.cpu.icache.replacements 979850 # number of replacements
-system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use
-system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits
-system.cpu.icache.overall_hits::total 11261998 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses
-system.cpu.icache.overall_misses::total 1059902 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.int_regfile_reads 550176555 # number of integer regfile reads
+system.cpu.int_regfile_writes 88426576 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8298 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30118912 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
+system.cpu.icache.replacements 980182 # number of replacements
+system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use
+system.cpu.icache.total_refs 11263184 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980694 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 11.484912 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.616610 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 11263184 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11263184 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11263184 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11263184 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11263184 # number of overall hits
+system.cpu.icache.overall_hits::total 11263184 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1060219 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1060219 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1060219 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1060219 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1060219 # number of overall misses
+system.cpu.icache.overall_misses::total 1060219 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14018220995 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14018220995 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14018220995 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14018220995 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178 # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985820 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
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-system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency
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+system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30915.572325 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30915.572325 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 30983 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 18747 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2620 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.825573 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 74.689243 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks
-system.cpu.dcache.writebacks::total 607769 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607588 # number of writebacks
+system.cpu.dcache.writebacks::total 607588 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351544 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 351544 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714338 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2714338 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065882 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065882 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065882 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065882 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385586 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385586 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12167 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12167 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634608 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634608 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634608 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634608 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803296500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803296500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8203666916 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8203666916 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141299500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141299500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13006963416 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13006963416 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13006963416 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13006963416 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36699724336 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36699724336 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=False
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed.
-Program aborted at cycle 2395768530500
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 22:03:06
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:07:42
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
Next CPU: DerivO3CPU
info: Entering event queue @ 5000004000. Starting simulation...
switching cpus
-info: Entering event queue @ 5000004500. Starting simulation...
+info: Entering event queue @ 5000005000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000004500. Starting simulation...
+info: Entering event queue @ 6000005000. Starting simulation...
switching cpus
-info: Entering event queue @ 6000011000. Starting simulation...
+info: Entering event queue @ 6000010500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 7000011000. Starting simulation...
+info: Entering event queue @ 7000010500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 8000011000. Starting simulation...
+info: Entering event queue @ 8000010500. Starting simulation...
switching cpus
-info: Entering event queue @ 8000065000. Starting simulation...
+info: Entering event queue @ 8000121000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000065000. Starting simulation...
-info: Entering event queue @ 9000075500. Starting simulation...
+info: Entering event queue @ 9000121000. Starting simulation...
switching cpus
-info: Entering event queue @ 9000080000. Starting simulation...
+info: Entering event queue @ 9000131500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 10000080000. Starting simulation...
switching cpus
-info: Entering event queue @ 10000082500. Starting simulation...
+info: Entering event queue @ 10000131500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 11000082500. Starting simulation...
+info: Entering event queue @ 11000131500. Starting simulation...
switching cpus
-info: Entering event queue @ 11000084500. Starting simulation...
+info: Entering event queue @ 11000132500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 12000084500. Starting simulation...
+info: Entering event queue @ 12000132500. Starting simulation...
switching cpus
-info: Entering event queue @ 12000089500. Starting simulation...
+info: Entering event queue @ 12000140500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 13000140500. Starting simulation...
switching cpus
-info: Entering event queue @ 13000089500. Starting simulation...
+info: Entering event queue @ 13000141500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 14000089500. Starting simulation...
+info: Entering event queue @ 14000141500. Starting simulation...
switching cpus
-info: Entering event queue @ 14000090500. Starting simulation...
+info: Entering event queue @ 14000161500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 15000090500. Starting simulation...
+info: Entering event queue @ 15000161500. Starting simulation...
switching cpus
-info: Entering event queue @ 15000095000. Starting simulation...
+info: Entering event queue @ 15000173500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 16000095000. Starting simulation...
+info: Entering event queue @ 16000173500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 17000095000. Starting simulation...
+info: Entering event queue @ 17000173500. Starting simulation...
switching cpus
-info: Entering event queue @ 17000096000. Starting simulation...
+info: Entering event queue @ 17000181000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 18000096000. Starting simulation...
-info: Entering event queue @ 26044720500. Starting simulation...
-info: Entering event queue @ 26044727000. Starting simulation...
+info: Entering event queue @ 18000181000. Starting simulation...
+info: Entering event queue @ 26044694500. Starting simulation...
+info: Entering event queue @ 26044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 26044727500. Starting simulation...
+info: Entering event queue @ 26044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 27044727500. Starting simulation...
+info: Entering event queue @ 27044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 28044727500. Starting simulation...
+info: Entering event queue @ 28044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 29044727500. Starting simulation...
-info: Entering event queue @ 36044720500. Starting simulation...
-info: Entering event queue @ 36044727000. Starting simulation...
+info: Entering event queue @ 29044706000. Starting simulation...
+info: Entering event queue @ 36044694500. Starting simulation...
+info: Entering event queue @ 36044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 36044727500. Starting simulation...
+info: Entering event queue @ 36044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37044727500. Starting simulation...
+info: Entering event queue @ 37044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 37044728000. Starting simulation...
+info: Entering event queue @ 37044706500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 38044728000. Starting simulation...
-info: Entering event queue @ 38044743500. Starting simulation...
+info: Entering event queue @ 38044706500. Starting simulation...
+info: Entering event queue @ 38044722500. Starting simulation...
switching cpus
-info: Entering event queue @ 38044784500. Starting simulation...
+info: Entering event queue @ 38044806000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 39044784500. Starting simulation...
+info: Entering event queue @ 39044806000. Starting simulation...
switching cpus
-info: Entering event queue @ 39044856000. Starting simulation...
+info: Entering event queue @ 39044813500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 40044856000. Starting simulation...
+info: Entering event queue @ 40044813500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 41044856000. Starting simulation...
+info: Entering event queue @ 41044813500. Starting simulation...
switching cpus
-info: Entering event queue @ 41044857500. Starting simulation...
+info: Entering event queue @ 41044821000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 42044857500. Starting simulation...
+info: Entering event queue @ 42044821000. Starting simulation...
switching cpus
-info: Entering event queue @ 42045164500. Starting simulation...
+info: Entering event queue @ 42045002500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 43045164500. Starting simulation...
switching cpus
-info: Entering event queue @ 43045165500. Starting simulation...
+info: Entering event queue @ 43045002500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 44045165500. Starting simulation...
+info: Entering event queue @ 44045002500. Starting simulation...
switching cpus
-info: Entering event queue @ 44045166000. Starting simulation...
+info: Entering event queue @ 44045003500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 45045166000. Starting simulation...
+info: Entering event queue @ 45045003500. Starting simulation...
switching cpus
-info: Entering event queue @ 45045171000. Starting simulation...
+info: Entering event queue @ 45045006000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 46045171000. Starting simulation...
+info: Entering event queue @ 46045006000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 47045171000. Starting simulation...
+info: Entering event queue @ 47045006000. Starting simulation...
switching cpus
-info: Entering event queue @ 47045181500. Starting simulation...
+info: Entering event queue @ 47045010000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 48045181500. Starting simulation...
+info: Entering event queue @ 48045010000. Starting simulation...
switching cpus
-info: Entering event queue @ 48045187000. Starting simulation...
+info: Entering event queue @ 48045031000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 49045187000. Starting simulation...
+info: Entering event queue @ 49045031000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
+info: Entering event queue @ 50045031000. Starting simulation...
switching cpus
-info: Entering event queue @ 50045187000. Starting simulation...
+info: Entering event queue @ 50045038500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 51045187000. Starting simulation...
-info: Entering event queue @ 56044720500. Starting simulation...
-info: Entering event queue @ 56044727000. Starting simulation...
+info: Entering event queue @ 51045038500. Starting simulation...
+info: Entering event queue @ 56044694500. Starting simulation...
+info: Entering event queue @ 56044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 56044727500. Starting simulation...
+info: Entering event queue @ 56044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 57044727500. Starting simulation...
+info: Entering event queue @ 57044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 58044727500. Starting simulation...
+info: Entering event queue @ 58044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 59044727500. Starting simulation...
-info: Entering event queue @ 66044720500. Starting simulation...
-info: Entering event queue @ 66044727000. Starting simulation...
+info: Entering event queue @ 59044706000. Starting simulation...
+info: Entering event queue @ 66044694500. Starting simulation...
+info: Entering event queue @ 66044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 66044727500. Starting simulation...
+info: Entering event queue @ 66044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 67044727500. Starting simulation...
+info: Entering event queue @ 67044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 68044727500. Starting simulation...
+info: Entering event queue @ 68044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 69044727500. Starting simulation...
-info: Entering event queue @ 76044720500. Starting simulation...
-info: Entering event queue @ 76044727000. Starting simulation...
+info: Entering event queue @ 69044706000. Starting simulation...
+info: Entering event queue @ 76044694500. Starting simulation...
+info: Entering event queue @ 76044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 76044727500. Starting simulation...
+info: Entering event queue @ 76044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 77044727500. Starting simulation...
+info: Entering event queue @ 77044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 78044727500. Starting simulation...
+info: Entering event queue @ 78044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 79044727500. Starting simulation...
-info: Entering event queue @ 86044720500. Starting simulation...
-info: Entering event queue @ 86044727000. Starting simulation...
+info: Entering event queue @ 79044706000. Starting simulation...
+info: Entering event queue @ 86044694500. Starting simulation...
+info: Entering event queue @ 86044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 86044727500. Starting simulation...
+info: Entering event queue @ 86044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 87044727500. Starting simulation...
+info: Entering event queue @ 87044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 88044727500. Starting simulation...
+info: Entering event queue @ 88044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 89044727500. Starting simulation...
-info: Entering event queue @ 96044720500. Starting simulation...
-info: Entering event queue @ 96044727000. Starting simulation...
+info: Entering event queue @ 89044701500. Starting simulation...
+info: Entering event queue @ 96044694500. Starting simulation...
+info: Entering event queue @ 96044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 96044727500. Starting simulation...
+info: Entering event queue @ 96044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 97044727500. Starting simulation...
+info: Entering event queue @ 97044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 98044727500. Starting simulation...
+info: Entering event queue @ 98044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 99044727500. Starting simulation...
-info: Entering event queue @ 106044720500. Starting simulation...
-info: Entering event queue @ 106044727000. Starting simulation...
+info: Entering event queue @ 99044706000. Starting simulation...
+info: Entering event queue @ 106044694500. Starting simulation...
+info: Entering event queue @ 106044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 106044727500. Starting simulation...
+info: Entering event queue @ 106044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 107044727500. Starting simulation...
+info: Entering event queue @ 107044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 108044727500. Starting simulation...
+info: Entering event queue @ 108044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 109044727500. Starting simulation...
-info: Entering event queue @ 116044720500. Starting simulation...
-info: Entering event queue @ 116044727000. Starting simulation...
+info: Entering event queue @ 109044706000. Starting simulation...
+info: Entering event queue @ 116044694500. Starting simulation...
+info: Entering event queue @ 116044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 116044727500. Starting simulation...
+info: Entering event queue @ 116044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 117044727500. Starting simulation...
+info: Entering event queue @ 117044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 118044727500. Starting simulation...
+info: Entering event queue @ 118044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 119044727500. Starting simulation...
-info: Entering event queue @ 126044720500. Starting simulation...
-info: Entering event queue @ 126044727000. Starting simulation...
+info: Entering event queue @ 119044706000. Starting simulation...
+info: Entering event queue @ 126044695500. Starting simulation...
+info: Entering event queue @ 126044702000. Starting simulation...
switching cpus
-info: Entering event queue @ 126044727500. Starting simulation...
+info: Entering event queue @ 126044702500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 127044727500. Starting simulation...
+info: Entering event queue @ 127044702500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 128044727500. Starting simulation...
+info: Entering event queue @ 128044702500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 129044727500. Starting simulation...
-info: Entering event queue @ 136044720500. Starting simulation...
-info: Entering event queue @ 136044727000. Starting simulation...
+info: Entering event queue @ 129044702500. Starting simulation...
+info: Entering event queue @ 136044694500. Starting simulation...
+info: Entering event queue @ 136044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 136044727500. Starting simulation...
+info: Entering event queue @ 136044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 137044727500. Starting simulation...
+info: Entering event queue @ 137044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 138044727500. Starting simulation...
+info: Entering event queue @ 138044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 139044727500. Starting simulation...
-info: Entering event queue @ 146044720500. Starting simulation...
-info: Entering event queue @ 146044727000. Starting simulation...
+info: Entering event queue @ 139044701500. Starting simulation...
+info: Entering event queue @ 146044694500. Starting simulation...
+info: Entering event queue @ 146044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 146044727500. Starting simulation...
+info: Entering event queue @ 146044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 147044727500. Starting simulation...
+info: Entering event queue @ 147044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 148044727500. Starting simulation...
+info: Entering event queue @ 148044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 149044727500. Starting simulation...
-info: Entering event queue @ 156044720500. Starting simulation...
-info: Entering event queue @ 156044727000. Starting simulation...
+info: Entering event queue @ 149044706000. Starting simulation...
+info: Entering event queue @ 156044694500. Starting simulation...
+info: Entering event queue @ 156044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 156044727500. Starting simulation...
+info: Entering event queue @ 156044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 157044727500. Starting simulation...
+info: Entering event queue @ 157044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 158044727500. Starting simulation...
+info: Entering event queue @ 158044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 159044727500. Starting simulation...
-info: Entering event queue @ 166044720500. Starting simulation...
-info: Entering event queue @ 166044727000. Starting simulation...
+info: Entering event queue @ 159044706000. Starting simulation...
+info: Entering event queue @ 166044694500. Starting simulation...
+info: Entering event queue @ 166044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 166044727500. Starting simulation...
+info: Entering event queue @ 166044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 167044727500. Starting simulation...
+info: Entering event queue @ 167044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 168044727500. Starting simulation...
+info: Entering event queue @ 168044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 169044727500. Starting simulation...
-info: Entering event queue @ 176044720500. Starting simulation...
-info: Entering event queue @ 176044727000. Starting simulation...
+info: Entering event queue @ 169044706000. Starting simulation...
+info: Entering event queue @ 176044694500. Starting simulation...
+info: Entering event queue @ 176044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 176044727500. Starting simulation...
+info: Entering event queue @ 176044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 177044727500. Starting simulation...
+info: Entering event queue @ 177044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 178044727500. Starting simulation...
+info: Entering event queue @ 178044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 179044727500. Starting simulation...
-info: Entering event queue @ 186044720500. Starting simulation...
-info: Entering event queue @ 186044727000. Starting simulation...
+info: Entering event queue @ 179044706000. Starting simulation...
+info: Entering event queue @ 186044694500. Starting simulation...
+info: Entering event queue @ 186044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 186044727500. Starting simulation...
+info: Entering event queue @ 186044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 187044727500. Starting simulation...
+info: Entering event queue @ 187044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 188044727500. Starting simulation...
+info: Entering event queue @ 188044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 189044727500. Starting simulation...
-info: Entering event queue @ 196044720500. Starting simulation...
-info: Entering event queue @ 196044727000. Starting simulation...
+info: Entering event queue @ 189044706000. Starting simulation...
+info: Entering event queue @ 196044695500. Starting simulation...
+info: Entering event queue @ 196044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 196044727500. Starting simulation...
+info: Entering event queue @ 196044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 197044727500. Starting simulation...
+info: Entering event queue @ 197044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 198044727500. Starting simulation...
+info: Entering event queue @ 198044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 199044727500. Starting simulation...
-info: Entering event queue @ 206044720500. Starting simulation...
-info: Entering event queue @ 206044727000. Starting simulation...
+info: Entering event queue @ 199044707000. Starting simulation...
+info: Entering event queue @ 206044695500. Starting simulation...
+info: Entering event queue @ 206044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 206044727500. Starting simulation...
+info: Entering event queue @ 206044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 207044727500. Starting simulation...
+info: Entering event queue @ 207044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 208044727500. Starting simulation...
+info: Entering event queue @ 208044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 209044727500. Starting simulation...
-info: Entering event queue @ 216044720500. Starting simulation...
-info: Entering event queue @ 216044727000. Starting simulation...
+info: Entering event queue @ 209044707000. Starting simulation...
+info: Entering event queue @ 216044694500. Starting simulation...
+info: Entering event queue @ 216044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 216044727500. Starting simulation...
+info: Entering event queue @ 216044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 217044727500. Starting simulation...
+info: Entering event queue @ 217044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 218044727500. Starting simulation...
+info: Entering event queue @ 218044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 219044727500. Starting simulation...
-info: Entering event queue @ 226044720500. Starting simulation...
-info: Entering event queue @ 226044727000. Starting simulation...
+info: Entering event queue @ 219044706000. Starting simulation...
+info: Entering event queue @ 226044694500. Starting simulation...
+info: Entering event queue @ 226044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 226044727500. Starting simulation...
+info: Entering event queue @ 226044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 227044727500. Starting simulation...
+info: Entering event queue @ 227044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 228044727500. Starting simulation...
+info: Entering event queue @ 228044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 229044727500. Starting simulation...
-info: Entering event queue @ 236044720500. Starting simulation...
-info: Entering event queue @ 236044727000. Starting simulation...
+info: Entering event queue @ 229044706000. Starting simulation...
+info: Entering event queue @ 236044694500. Starting simulation...
+info: Entering event queue @ 236044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 236044727500. Starting simulation...
+info: Entering event queue @ 236044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 237044727500. Starting simulation...
+info: Entering event queue @ 237044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 238044727500. Starting simulation...
+info: Entering event queue @ 238044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 239044727500. Starting simulation...
-info: Entering event queue @ 246044720500. Starting simulation...
-info: Entering event queue @ 246044727000. Starting simulation...
+info: Entering event queue @ 239044706000. Starting simulation...
+info: Entering event queue @ 246044694500. Starting simulation...
+info: Entering event queue @ 246044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 246044727500. Starting simulation...
+info: Entering event queue @ 246044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 247044727500. Starting simulation...
+info: Entering event queue @ 247044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 248044727500. Starting simulation...
+info: Entering event queue @ 248044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 249044727500. Starting simulation...
-info: Entering event queue @ 256044720500. Starting simulation...
-info: Entering event queue @ 256044727000. Starting simulation...
+info: Entering event queue @ 249044701500. Starting simulation...
+info: Entering event queue @ 256044694500. Starting simulation...
+info: Entering event queue @ 256044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 256044727500. Starting simulation...
+info: Entering event queue @ 256044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 257044727500. Starting simulation...
+info: Entering event queue @ 257044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 258044727500. Starting simulation...
+info: Entering event queue @ 258044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 259044727500. Starting simulation...
-info: Entering event queue @ 266044720500. Starting simulation...
-info: Entering event queue @ 266847937000. Starting simulation...
+info: Entering event queue @ 259044706000. Starting simulation...
+info: Entering event queue @ 266044694500. Starting simulation...
+info: Entering event queue @ 266911751000. Starting simulation...
switching cpus
-info: Entering event queue @ 266847939000. Starting simulation...
+info: Entering event queue @ 266911753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 267847939000. Starting simulation...
+info: Entering event queue @ 267911753000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 268847939000. Starting simulation...
+info: Entering event queue @ 268911753000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 269847939000. Starting simulation...
-info: Entering event queue @ 276044720500. Starting simulation...
-info: Entering event queue @ 276044727000. Starting simulation...
+info: Entering event queue @ 269911753000. Starting simulation...
+info: Entering event queue @ 276044694500. Starting simulation...
+info: Entering event queue @ 276044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 276044727500. Starting simulation...
+info: Entering event queue @ 276044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 277044727500. Starting simulation...
+info: Entering event queue @ 277044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 278044727500. Starting simulation...
+info: Entering event queue @ 278044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 279044727500. Starting simulation...
-info: Entering event queue @ 286044720500. Starting simulation...
-info: Entering event queue @ 286044727000. Starting simulation...
+info: Entering event queue @ 279044706000. Starting simulation...
+info: Entering event queue @ 286044695500. Starting simulation...
+info: Entering event queue @ 286044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 286044727500. Starting simulation...
+info: Entering event queue @ 286044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 287044727500. Starting simulation...
+info: Entering event queue @ 287044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 288044727500. Starting simulation...
+info: Entering event queue @ 288044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 289044727500. Starting simulation...
-info: Entering event queue @ 296044720500. Starting simulation...
-info: Entering event queue @ 296044727000. Starting simulation...
+info: Entering event queue @ 289044707000. Starting simulation...
+info: Entering event queue @ 296044694500. Starting simulation...
+info: Entering event queue @ 296044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 296044727500. Starting simulation...
+info: Entering event queue @ 296044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 297044727500. Starting simulation...
+info: Entering event queue @ 297044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 298044727500. Starting simulation...
-info: Entering event queue @ 299584231000. Starting simulation...
+info: Entering event queue @ 298044701500. Starting simulation...
+info: Entering event queue @ 299648351000. Starting simulation...
switching cpus
-info: Entering event queue @ 299584233000. Starting simulation...
+info: Entering event queue @ 299648353000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 300584233000. Starting simulation...
-info: Entering event queue @ 306044720500. Starting simulation...
-info: Entering event queue @ 306044727000. Starting simulation...
+info: Entering event queue @ 300648353000. Starting simulation...
+info: Entering event queue @ 306044694500. Starting simulation...
+info: Entering event queue @ 306044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 306044727500. Starting simulation...
+info: Entering event queue @ 306044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 307044727500. Starting simulation...
+info: Entering event queue @ 307044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 308044727500. Starting simulation...
+info: Entering event queue @ 308044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 309044727500. Starting simulation...
-info: Entering event queue @ 316044720500. Starting simulation...
-info: Entering event queue @ 316044727000. Starting simulation...
+info: Entering event queue @ 309044706000. Starting simulation...
+info: Entering event queue @ 316044694500. Starting simulation...
+info: Entering event queue @ 316044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 316044727500. Starting simulation...
+info: Entering event queue @ 316044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 317044727500. Starting simulation...
+info: Entering event queue @ 317044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 318044727500. Starting simulation...
+info: Entering event queue @ 318044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 319044727500. Starting simulation...
-info: Entering event queue @ 326044720500. Starting simulation...
-info: Entering event queue @ 326044727000. Starting simulation...
+info: Entering event queue @ 319044706000. Starting simulation...
+info: Entering event queue @ 326044694500. Starting simulation...
+info: Entering event queue @ 326044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 326044727500. Starting simulation...
+info: Entering event queue @ 326044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 327044727500. Starting simulation...
+info: Entering event queue @ 327044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 328044727500. Starting simulation...
+info: Entering event queue @ 328044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 329044727500. Starting simulation...
-info: Entering event queue @ 336044720500. Starting simulation...
-info: Entering event queue @ 336044727000. Starting simulation...
+info: Entering event queue @ 329044706000. Starting simulation...
+info: Entering event queue @ 336044694500. Starting simulation...
+info: Entering event queue @ 336044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 336044727500. Starting simulation...
+info: Entering event queue @ 336044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 337044727500. Starting simulation...
+info: Entering event queue @ 337044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 338044727500. Starting simulation...
+info: Entering event queue @ 338044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 339044727500. Starting simulation...
-info: Entering event queue @ 346044720500. Starting simulation...
-info: Entering event queue @ 346044727000. Starting simulation...
+info: Entering event queue @ 339044706000. Starting simulation...
+info: Entering event queue @ 346044694500. Starting simulation...
+info: Entering event queue @ 346044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 346044727500. Starting simulation...
+info: Entering event queue @ 346044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 347044727500. Starting simulation...
+info: Entering event queue @ 347044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 348044727500. Starting simulation...
+info: Entering event queue @ 348044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 349044727500. Starting simulation...
-info: Entering event queue @ 356044720500. Starting simulation...
-info: Entering event queue @ 356044727000. Starting simulation...
+info: Entering event queue @ 349044706000. Starting simulation...
+info: Entering event queue @ 356044695500. Starting simulation...
+info: Entering event queue @ 356044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 356044727500. Starting simulation...
+info: Entering event queue @ 356044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 357044727500. Starting simulation...
+info: Entering event queue @ 357044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 358044727500. Starting simulation...
+info: Entering event queue @ 358044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 359044727500. Starting simulation...
-info: Entering event queue @ 366044720500. Starting simulation...
-info: Entering event queue @ 366044727000. Starting simulation...
+info: Entering event queue @ 359044707000. Starting simulation...
+info: Entering event queue @ 366044695500. Starting simulation...
+info: Entering event queue @ 366044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 366044727500. Starting simulation...
+info: Entering event queue @ 366044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 367044727500. Starting simulation...
+info: Entering event queue @ 367044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 368044727500. Starting simulation...
+info: Entering event queue @ 368044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 369044727500. Starting simulation...
-info: Entering event queue @ 376044720500. Starting simulation...
-info: Entering event queue @ 376044727000. Starting simulation...
+info: Entering event queue @ 369044707000. Starting simulation...
+info: Entering event queue @ 376044695500. Starting simulation...
+info: Entering event queue @ 376044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 376044727500. Starting simulation...
+info: Entering event queue @ 376044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 377044727500. Starting simulation...
+info: Entering event queue @ 377044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 378044727500. Starting simulation...
+info: Entering event queue @ 378044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 379044727500. Starting simulation...
-info: Entering event queue @ 386044720500. Starting simulation...
-info: Entering event queue @ 386044727000. Starting simulation...
+info: Entering event queue @ 379044708000. Starting simulation...
+info: Entering event queue @ 386044695500. Starting simulation...
+info: Entering event queue @ 386044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 386044727500. Starting simulation...
+info: Entering event queue @ 386044704000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 387044727500. Starting simulation...
+info: Entering event queue @ 387044704000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 388044727500. Starting simulation...
+info: Entering event queue @ 388044704000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 389044727500. Starting simulation...
-info: Entering event queue @ 396044720500. Starting simulation...
-info: Entering event queue @ 396044727000. Starting simulation...
+info: Entering event queue @ 389044704000. Starting simulation...
+info: Entering event queue @ 396044695500. Starting simulation...
+info: Entering event queue @ 396044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 396044727500. Starting simulation...
+info: Entering event queue @ 396044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 397044727500. Starting simulation...
+info: Entering event queue @ 397044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 398044727500. Starting simulation...
+info: Entering event queue @ 398044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 399044727500. Starting simulation...
-info: Entering event queue @ 406044720500. Starting simulation...
-info: Entering event queue @ 406044727000. Starting simulation...
+info: Entering event queue @ 399044708000. Starting simulation...
+info: Entering event queue @ 406044694500. Starting simulation...
+info: Entering event queue @ 406044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 406044727500. Starting simulation...
+info: Entering event queue @ 406044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 407044727500. Starting simulation...
+info: Entering event queue @ 407044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 408044727500. Starting simulation...
+info: Entering event queue @ 408044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 409044727500. Starting simulation...
-info: Entering event queue @ 416044720500. Starting simulation...
-info: Entering event queue @ 416044727000. Starting simulation...
+info: Entering event queue @ 409044701500. Starting simulation...
+info: Entering event queue @ 416044694500. Starting simulation...
+info: Entering event queue @ 416044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 416044727500. Starting simulation...
+info: Entering event queue @ 416044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 417044727500. Starting simulation...
+info: Entering event queue @ 417044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 418044727500. Starting simulation...
+info: Entering event queue @ 418044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 419044727500. Starting simulation...
-info: Entering event queue @ 426044720500. Starting simulation...
-info: Entering event queue @ 426044727000. Starting simulation...
+info: Entering event queue @ 419044706000. Starting simulation...
+info: Entering event queue @ 426044695500. Starting simulation...
+info: Entering event queue @ 426044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 426044727500. Starting simulation...
+info: Entering event queue @ 426044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 427044727500. Starting simulation...
+info: Entering event queue @ 427044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 428044727500. Starting simulation...
+info: Entering event queue @ 428044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 429044727500. Starting simulation...
-info: Entering event queue @ 436044720500. Starting simulation...
-info: Entering event queue @ 436044727000. Starting simulation...
+info: Entering event queue @ 429044708000. Starting simulation...
+info: Entering event queue @ 436044694500. Starting simulation...
+info: Entering event queue @ 436044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 436044727500. Starting simulation...
+info: Entering event queue @ 436044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 437044727500. Starting simulation...
+info: Entering event queue @ 437044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 438044727500. Starting simulation...
+info: Entering event queue @ 438044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 439044727500. Starting simulation...
-info: Entering event queue @ 446044720500. Starting simulation...
-info: Entering event queue @ 446044727000. Starting simulation...
+info: Entering event queue @ 439044706000. Starting simulation...
+info: Entering event queue @ 446044695500. Starting simulation...
+info: Entering event queue @ 446044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 446044727500. Starting simulation...
+info: Entering event queue @ 446044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 447044727500. Starting simulation...
+info: Entering event queue @ 447044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 448044727500. Starting simulation...
+info: Entering event queue @ 448044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 449044727500. Starting simulation...
-info: Entering event queue @ 456044720500. Starting simulation...
-info: Entering event queue @ 456044727000. Starting simulation...
+info: Entering event queue @ 449044707000. Starting simulation...
+info: Entering event queue @ 456044694500. Starting simulation...
+info: Entering event queue @ 456044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 456044727500. Starting simulation...
+info: Entering event queue @ 456044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 457044727500. Starting simulation...
+info: Entering event queue @ 457044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 458044727500. Starting simulation...
+info: Entering event queue @ 458044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 459044727500. Starting simulation...
-info: Entering event queue @ 466044720500. Starting simulation...
-info: Entering event queue @ 466044727000. Starting simulation...
+info: Entering event queue @ 459044701500. Starting simulation...
+info: Entering event queue @ 466044694500. Starting simulation...
+info: Entering event queue @ 466044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 466044727500. Starting simulation...
+info: Entering event queue @ 466044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 467044727500. Starting simulation...
+info: Entering event queue @ 467044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 468044727500. Starting simulation...
+info: Entering event queue @ 468044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 469044727500. Starting simulation...
-info: Entering event queue @ 476044720500. Starting simulation...
-info: Entering event queue @ 476044727000. Starting simulation...
+info: Entering event queue @ 469044706000. Starting simulation...
+info: Entering event queue @ 476044694500. Starting simulation...
+info: Entering event queue @ 476044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 476044727500. Starting simulation...
+info: Entering event queue @ 476044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 477044727500. Starting simulation...
+info: Entering event queue @ 477044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 478044727500. Starting simulation...
+info: Entering event queue @ 478044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 479044727500. Starting simulation...
-info: Entering event queue @ 486044720500. Starting simulation...
-info: Entering event queue @ 486044727000. Starting simulation...
+info: Entering event queue @ 479044706000. Starting simulation...
+info: Entering event queue @ 486044694500. Starting simulation...
+info: Entering event queue @ 486044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 486044727500. Starting simulation...
+info: Entering event queue @ 486044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 487044727500. Starting simulation...
+info: Entering event queue @ 487044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 488044727500. Starting simulation...
+info: Entering event queue @ 488044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 489044727500. Starting simulation...
-info: Entering event queue @ 496044720500. Starting simulation...
-info: Entering event queue @ 496044727000. Starting simulation...
+info: Entering event queue @ 489044706000. Starting simulation...
+info: Entering event queue @ 496044694500. Starting simulation...
+info: Entering event queue @ 496065726000. Starting simulation...
switching cpus
-info: Entering event queue @ 496044727500. Starting simulation...
+info: Entering event queue @ 496065728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 497044727500. Starting simulation...
+info: Entering event queue @ 497065728000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 498044727500. Starting simulation...
+info: Entering event queue @ 498065728000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 499044727500. Starting simulation...
-info: Entering event queue @ 506044720500. Starting simulation...
-info: Entering event queue @ 506044727000. Starting simulation...
+info: Entering event queue @ 499065728000. Starting simulation...
+info: Entering event queue @ 506044695500. Starting simulation...
+info: Entering event queue @ 506044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 506044727500. Starting simulation...
+info: Entering event queue @ 506044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 507044727500. Starting simulation...
+info: Entering event queue @ 507044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 508044727500. Starting simulation...
+info: Entering event queue @ 508044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 509044727500. Starting simulation...
-info: Entering event queue @ 516044720500. Starting simulation...
-info: Entering event queue @ 516044727000. Starting simulation...
+info: Entering event queue @ 509044708000. Starting simulation...
+info: Entering event queue @ 516044695500. Starting simulation...
+info: Entering event queue @ 516044703000. Starting simulation...
switching cpus
-info: Entering event queue @ 516044727500. Starting simulation...
+info: Entering event queue @ 516044703500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 517044727500. Starting simulation...
+info: Entering event queue @ 517044703500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 518044727500. Starting simulation...
+info: Entering event queue @ 518044703500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 519044727500. Starting simulation...
-info: Entering event queue @ 526044720500. Starting simulation...
-info: Entering event queue @ 526044727000. Starting simulation...
+info: Entering event queue @ 519044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 526044727500. Starting simulation...
+info: Entering event queue @ 526044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 527044727500. Starting simulation...
+info: Entering event queue @ 527044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 528044727500. Starting simulation...
-info: Entering event queue @ 528737989000. Starting simulation...
+info: Entering event queue @ 528044695500. Starting simulation...
+info: Entering event queue @ 528802326000. Starting simulation...
switching cpus
-info: Entering event queue @ 528737991000. Starting simulation...
+info: Entering event queue @ 528802328000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 529737991000. Starting simulation...
-info: Entering event queue @ 536044720500. Starting simulation...
-info: Entering event queue @ 536044727000. Starting simulation...
+info: Entering event queue @ 529802328000. Starting simulation...
switching cpus
-info: Entering event queue @ 536044727500. Starting simulation...
+info: Entering event queue @ 536044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 537044727500. Starting simulation...
+info: Entering event queue @ 537044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 538044727500. Starting simulation...
+info: Entering event queue @ 538044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 539044727500. Starting simulation...
-info: Entering event queue @ 546044720500. Starting simulation...
-info: Entering event queue @ 546044727000. Starting simulation...
+info: Entering event queue @ 539044695500. Starting simulation...
+info: Entering event queue @ 546044694500. Starting simulation...
+info: Entering event queue @ 546044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 546044727500. Starting simulation...
+info: Entering event queue @ 546044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 547044727500. Starting simulation...
+info: Entering event queue @ 547044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 548044727500. Starting simulation...
+info: Entering event queue @ 548044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 549044727500. Starting simulation...
-info: Entering event queue @ 556044720500. Starting simulation...
-info: Entering event queue @ 556044727000. Starting simulation...
+info: Entering event queue @ 549044706000. Starting simulation...
+info: Entering event queue @ 556044695500. Starting simulation...
+info: Entering event queue @ 556044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 556044727500. Starting simulation...
+info: Entering event queue @ 556044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 557044727500. Starting simulation...
+info: Entering event queue @ 557044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 558044727500. Starting simulation...
+info: Entering event queue @ 558044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 559044727500. Starting simulation...
-info: Entering event queue @ 566044720500. Starting simulation...
-info: Entering event queue @ 566044727000. Starting simulation...
+info: Entering event queue @ 559044708000. Starting simulation...
+info: Entering event queue @ 566044694500. Starting simulation...
+info: Entering event queue @ 566044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 566044727500. Starting simulation...
+info: Entering event queue @ 566044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 567044727500. Starting simulation...
+info: Entering event queue @ 567044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 568044727500. Starting simulation...
+info: Entering event queue @ 568044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569044727500. Starting simulation...
-info: Entering event queue @ 576044720500. Starting simulation...
-info: Entering event queue @ 576044727000. Starting simulation...
+info: Entering event queue @ 569044701500. Starting simulation...
+info: Entering event queue @ 576044694500. Starting simulation...
+info: Entering event queue @ 576044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 576044727500. Starting simulation...
+info: Entering event queue @ 576044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 577044727500. Starting simulation...
+info: Entering event queue @ 577044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 578044727500. Starting simulation...
+info: Entering event queue @ 578044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 579044727500. Starting simulation...
-info: Entering event queue @ 586044720500. Starting simulation...
-info: Entering event queue @ 586044727000. Starting simulation...
+info: Entering event queue @ 579044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 586044727500. Starting simulation...
+info: Entering event queue @ 586044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 587044727500. Starting simulation...
+info: Entering event queue @ 587044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 588044727500. Starting simulation...
+info: Entering event queue @ 588044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 589044727500. Starting simulation...
-info: Entering event queue @ 596044720500. Starting simulation...
-info: Entering event queue @ 596044727000. Starting simulation...
+info: Entering event queue @ 589044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 596044727500. Starting simulation...
+info: Entering event queue @ 596044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 597044727500. Starting simulation...
+info: Entering event queue @ 597044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 598044727500. Starting simulation...
+info: Entering event queue @ 598044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 599044727500. Starting simulation...
-info: Entering event queue @ 606044720500. Starting simulation...
-info: Entering event queue @ 606044727000. Starting simulation...
+info: Entering event queue @ 599044695500. Starting simulation...
+info: Entering event queue @ 606044695500. Starting simulation...
+info: Entering event queue @ 606044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 606044727500. Starting simulation...
+info: Entering event queue @ 606044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 607044727500. Starting simulation...
+info: Entering event queue @ 607044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 608044727500. Starting simulation...
+info: Entering event queue @ 608044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 609044727500. Starting simulation...
-info: Entering event queue @ 616044720500. Starting simulation...
-info: Entering event queue @ 616044727000. Starting simulation...
+info: Entering event queue @ 609044707000. Starting simulation...
+info: Entering event queue @ 616044694500. Starting simulation...
+info: Entering event queue @ 616044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 616044727500. Starting simulation...
+info: Entering event queue @ 616044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 617044727500. Starting simulation...
+info: Entering event queue @ 617044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 618044727500. Starting simulation...
+info: Entering event queue @ 618044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 619044727500. Starting simulation...
-info: Entering event queue @ 626044720500. Starting simulation...
-info: Entering event queue @ 626946715000. Starting simulation...
+info: Entering event queue @ 619044706000. Starting simulation...
+info: Entering event queue @ 626044694500. Starting simulation...
+info: Entering event queue @ 627010955000. Starting simulation...
switching cpus
-info: Entering event queue @ 626946717000. Starting simulation...
+info: Entering event queue @ 627010957000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 627946717000. Starting simulation...
+info: Entering event queue @ 628010957000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 628946717000. Starting simulation...
+info: Entering event queue @ 629010957000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 629946717000. Starting simulation...
-info: Entering event queue @ 636044720500. Starting simulation...
-info: Entering event queue @ 636044727000. Starting simulation...
+info: Entering event queue @ 630010957000. Starting simulation...
+info: Entering event queue @ 636044694500. Starting simulation...
+info: Entering event queue @ 636044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 636044727500. Starting simulation...
+info: Entering event queue @ 636044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 637044727500. Starting simulation...
+info: Entering event queue @ 637044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 638044727500. Starting simulation...
+info: Entering event queue @ 638044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 639044727500. Starting simulation...
-info: Entering event queue @ 646044720500. Starting simulation...
-info: Entering event queue @ 646044727000. Starting simulation...
+info: Entering event queue @ 639044706000. Starting simulation...
+info: Entering event queue @ 646044694500. Starting simulation...
+info: Entering event queue @ 646044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 646044727500. Starting simulation...
+info: Entering event queue @ 646044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 647044727500. Starting simulation...
+info: Entering event queue @ 647044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 648044727500. Starting simulation...
+info: Entering event queue @ 648044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 649044727500. Starting simulation...
-info: Entering event queue @ 656044720500. Starting simulation...
-info: Entering event queue @ 656044727000. Starting simulation...
+info: Entering event queue @ 649044706000. Starting simulation...
+info: Entering event queue @ 656044695500. Starting simulation...
+info: Entering event queue @ 656044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 656044727500. Starting simulation...
+info: Entering event queue @ 656044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 657044727500. Starting simulation...
+info: Entering event queue @ 657044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 658044727500. Starting simulation...
-info: Entering event queue @ 659682856000. Starting simulation...
+info: Entering event queue @ 658044707000. Starting simulation...
+info: Entering event queue @ 659746543000. Starting simulation...
switching cpus
-info: Entering event queue @ 659682858000. Starting simulation...
+info: Entering event queue @ 659746545000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 660682858000. Starting simulation...
-info: Entering event queue @ 666044720500. Starting simulation...
-info: Entering event queue @ 666044727000. Starting simulation...
+info: Entering event queue @ 660746545000. Starting simulation...
+info: Entering event queue @ 666044694500. Starting simulation...
+info: Entering event queue @ 666044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 666044727500. Starting simulation...
+info: Entering event queue @ 666044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 667044727500. Starting simulation...
+info: Entering event queue @ 667044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 668044727500. Starting simulation...
+info: Entering event queue @ 668044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 669044727500. Starting simulation...
-info: Entering event queue @ 676044720500. Starting simulation...
-info: Entering event queue @ 676044727000. Starting simulation...
+info: Entering event queue @ 669044706000. Starting simulation...
+info: Entering event queue @ 676044694500. Starting simulation...
+info: Entering event queue @ 676044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 676044727500. Starting simulation...
+info: Entering event queue @ 676044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 677044727500. Starting simulation...
+info: Entering event queue @ 677044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 678044727500. Starting simulation...
+info: Entering event queue @ 678044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 679044727500. Starting simulation...
-info: Entering event queue @ 686044720500. Starting simulation...
-info: Entering event queue @ 686044727000. Starting simulation...
+info: Entering event queue @ 679044706000. Starting simulation...
+info: Entering event queue @ 686044694500. Starting simulation...
+info: Entering event queue @ 686044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 686044727500. Starting simulation...
+info: Entering event queue @ 686044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 687044727500. Starting simulation...
+info: Entering event queue @ 687044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 688044727500. Starting simulation...
+info: Entering event queue @ 688044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 689044727500. Starting simulation...
-info: Entering event queue @ 696044720500. Starting simulation...
-info: Entering event queue @ 696044727000. Starting simulation...
+info: Entering event queue @ 689044706000. Starting simulation...
+info: Entering event queue @ 696044694500. Starting simulation...
+info: Entering event queue @ 696044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 696044727500. Starting simulation...
+info: Entering event queue @ 696044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 697044727500. Starting simulation...
+info: Entering event queue @ 697044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 698044727500. Starting simulation...
+info: Entering event queue @ 698044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 699044727500. Starting simulation...
-info: Entering event queue @ 706044720500. Starting simulation...
-info: Entering event queue @ 706044727000. Starting simulation...
+info: Entering event queue @ 699044706000. Starting simulation...
+info: Entering event queue @ 706044695500. Starting simulation...
+info: Entering event queue @ 706044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 706044727500. Starting simulation...
+info: Entering event queue @ 706044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 707044727500. Starting simulation...
+info: Entering event queue @ 707044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 708044727500. Starting simulation...
+info: Entering event queue @ 708044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 709044727500. Starting simulation...
-info: Entering event queue @ 716044720500. Starting simulation...
-info: Entering event queue @ 716044727000. Starting simulation...
+info: Entering event queue @ 709044707000. Starting simulation...
+info: Entering event queue @ 716044694500. Starting simulation...
+info: Entering event queue @ 716044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 716044727500. Starting simulation...
+info: Entering event queue @ 716044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 717044727500. Starting simulation...
+info: Entering event queue @ 717044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 718044727500. Starting simulation...
+info: Entering event queue @ 718044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 719044727500. Starting simulation...
-info: Entering event queue @ 726044720500. Starting simulation...
-info: Entering event queue @ 726044727000. Starting simulation...
+info: Entering event queue @ 719044706000. Starting simulation...
+info: Entering event queue @ 726044694500. Starting simulation...
+info: Entering event queue @ 726044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 726044727500. Starting simulation...
+info: Entering event queue @ 726044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 727044727500. Starting simulation...
+info: Entering event queue @ 727044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 728044727500. Starting simulation...
+info: Entering event queue @ 728044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 729044727500. Starting simulation...
-info: Entering event queue @ 736044720500. Starting simulation...
-info: Entering event queue @ 736044727000. Starting simulation...
+info: Entering event queue @ 729044706000. Starting simulation...
+info: Entering event queue @ 736044694500. Starting simulation...
+info: Entering event queue @ 736044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 736044727500. Starting simulation...
+info: Entering event queue @ 736044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 737044727500. Starting simulation...
+info: Entering event queue @ 737044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 738044727500. Starting simulation...
+info: Entering event queue @ 738044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 739044727500. Starting simulation...
-info: Entering event queue @ 746044720500. Starting simulation...
-info: Entering event queue @ 746044727000. Starting simulation...
+info: Entering event queue @ 739044701500. Starting simulation...
+info: Entering event queue @ 746044694500. Starting simulation...
+info: Entering event queue @ 746044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 746044727500. Starting simulation...
+info: Entering event queue @ 746044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 747044727500. Starting simulation...
+info: Entering event queue @ 747044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 748044727500. Starting simulation...
+info: Entering event queue @ 748044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 749044727500. Starting simulation...
-info: Entering event queue @ 756044720500. Starting simulation...
-info: Entering event queue @ 756044727000. Starting simulation...
+info: Entering event queue @ 749044706000. Starting simulation...
+info: Entering event queue @ 756044694500. Starting simulation...
+info: Entering event queue @ 756044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 756044727500. Starting simulation...
+info: Entering event queue @ 756044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 757044727500. Starting simulation...
+info: Entering event queue @ 757044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 758044727500. Starting simulation...
+info: Entering event queue @ 758044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 759044727500. Starting simulation...
-info: Entering event queue @ 766044720500. Starting simulation...
-info: Entering event queue @ 766044727000. Starting simulation...
+info: Entering event queue @ 759044706000. Starting simulation...
+info: Entering event queue @ 766044695500. Starting simulation...
+info: Entering event queue @ 766044762000. Starting simulation...
switching cpus
-info: Entering event queue @ 766044727500. Starting simulation...
+info: Entering event queue @ 766044766500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 767044727500. Starting simulation...
+info: Entering event queue @ 767044766500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 768044727500. Starting simulation...
+info: Entering event queue @ 768044766500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 769044727500. Starting simulation...
-info: Entering event queue @ 776044720500. Starting simulation...
-info: Entering event queue @ 776044727000. Starting simulation...
+info: Entering event queue @ 769044766500. Starting simulation...
+info: Entering event queue @ 776044694500. Starting simulation...
+info: Entering event queue @ 776044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 776044727500. Starting simulation...
+info: Entering event queue @ 776044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 777044727500. Starting simulation...
+info: Entering event queue @ 777044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 778044727500. Starting simulation...
+info: Entering event queue @ 778044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 779044727500. Starting simulation...
-info: Entering event queue @ 786044720500. Starting simulation...
-info: Entering event queue @ 786044727000. Starting simulation...
+info: Entering event queue @ 779044706000. Starting simulation...
+info: Entering event queue @ 786044694500. Starting simulation...
+info: Entering event queue @ 786044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 786044727500. Starting simulation...
+info: Entering event queue @ 786044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 787044727500. Starting simulation...
+info: Entering event queue @ 787044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 788044727500. Starting simulation...
+info: Entering event queue @ 788044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 789044727500. Starting simulation...
-info: Entering event queue @ 796044720500. Starting simulation...
-info: Entering event queue @ 796044727000. Starting simulation...
+info: Entering event queue @ 789044701500. Starting simulation...
+info: Entering event queue @ 796044694500. Starting simulation...
+info: Entering event queue @ 796044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 796044727500. Starting simulation...
+info: Entering event queue @ 796044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 797044727500. Starting simulation...
+info: Entering event queue @ 797044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 798044727500. Starting simulation...
+info: Entering event queue @ 798044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 799044727500. Starting simulation...
-info: Entering event queue @ 806044720500. Starting simulation...
-info: Entering event queue @ 806044727000. Starting simulation...
+info: Entering event queue @ 799044706000. Starting simulation...
+info: Entering event queue @ 806044694500. Starting simulation...
+info: Entering event queue @ 806044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 806044727500. Starting simulation...
+info: Entering event queue @ 806044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 807044727500. Starting simulation...
+info: Entering event queue @ 807044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 808044727500. Starting simulation...
+info: Entering event queue @ 808044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 809044727500. Starting simulation...
-info: Entering event queue @ 816044720500. Starting simulation...
-info: Entering event queue @ 816044727000. Starting simulation...
+info: Entering event queue @ 809044706000. Starting simulation...
+info: Entering event queue @ 816044694500. Starting simulation...
+info: Entering event queue @ 816044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 816044727500. Starting simulation...
+info: Entering event queue @ 816044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 817044727500. Starting simulation...
+info: Entering event queue @ 817044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 818044727500. Starting simulation...
+info: Entering event queue @ 818044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 819044727500. Starting simulation...
-info: Entering event queue @ 826044720500. Starting simulation...
-info: Entering event queue @ 826044727000. Starting simulation...
+info: Entering event queue @ 819044706000. Starting simulation...
+info: Entering event queue @ 826044694500. Starting simulation...
+info: Entering event queue @ 826044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 826044727500. Starting simulation...
+info: Entering event queue @ 826044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 827044727500. Starting simulation...
+info: Entering event queue @ 827044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 828044727500. Starting simulation...
+info: Entering event queue @ 828044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 829044727500. Starting simulation...
-info: Entering event queue @ 836044720500. Starting simulation...
-info: Entering event queue @ 836044727000. Starting simulation...
+info: Entering event queue @ 829044706000. Starting simulation...
+info: Entering event queue @ 836044695500. Starting simulation...
+info: Entering event queue @ 836044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 836044727500. Starting simulation...
+info: Entering event queue @ 836044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 837044727500. Starting simulation...
+info: Entering event queue @ 837044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 838044727500. Starting simulation...
+info: Entering event queue @ 838044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 839044727500. Starting simulation...
-info: Entering event queue @ 846044720500. Starting simulation...
-info: Entering event queue @ 846044727000. Starting simulation...
+info: Entering event queue @ 839044707000. Starting simulation...
+info: Entering event queue @ 846044695500. Starting simulation...
+info: Entering event queue @ 846044703000. Starting simulation...
switching cpus
-info: Entering event queue @ 846044727500. Starting simulation...
+info: Entering event queue @ 846044707500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 847044727500. Starting simulation...
+info: Entering event queue @ 847044707500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 848044727500. Starting simulation...
+info: Entering event queue @ 848044707500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 849044727500. Starting simulation...
-info: Entering event queue @ 856044720500. Starting simulation...
-info: Entering event queue @ 856100473000. Starting simulation...
+info: Entering event queue @ 849044707500. Starting simulation...
+info: Entering event queue @ 856044694500. Starting simulation...
+info: Entering event queue @ 856163939000. Starting simulation...
switching cpus
-info: Entering event queue @ 856100475000. Starting simulation...
+info: Entering event queue @ 856163941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 857100475000. Starting simulation...
+info: Entering event queue @ 857163941000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 858100475000. Starting simulation...
+info: Entering event queue @ 858163941000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 859100475000. Starting simulation...
-info: Entering event queue @ 866044720500. Starting simulation...
-info: Entering event queue @ 866044727000. Starting simulation...
+info: Entering event queue @ 859163941000. Starting simulation...
+info: Entering event queue @ 866044695500. Starting simulation...
+info: Entering event queue @ 866044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 866044727500. Starting simulation...
+info: Entering event queue @ 866044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 867044727500. Starting simulation...
+info: Entering event queue @ 867044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 868044727500. Starting simulation...
+info: Entering event queue @ 868044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 869044727500. Starting simulation...
-info: Entering event queue @ 876044720500. Starting simulation...
-info: Entering event queue @ 876044727000. Starting simulation...
+info: Entering event queue @ 869044707000. Starting simulation...
+info: Entering event queue @ 876044694500. Starting simulation...
+info: Entering event queue @ 876044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 876044727500. Starting simulation...
+info: Entering event queue @ 876044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 877044727500. Starting simulation...
+info: Entering event queue @ 877044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 878044727500. Starting simulation...
+info: Entering event queue @ 878044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 879044727500. Starting simulation...
-info: Entering event queue @ 886044720500. Starting simulation...
-info: Entering event queue @ 886044727000. Starting simulation...
+info: Entering event queue @ 879044706000. Starting simulation...
+info: Entering event queue @ 886044695500. Starting simulation...
+info: Entering event queue @ 886044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 886044727500. Starting simulation...
+info: Entering event queue @ 886044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 887044727500. Starting simulation...
+info: Entering event queue @ 887044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 888044727500. Starting simulation...
-info: Entering event queue @ 888837073000. Starting simulation...
+info: Entering event queue @ 888044708000. Starting simulation...
+info: Entering event queue @ 888900518000. Starting simulation...
switching cpus
-info: Entering event queue @ 888837075000. Starting simulation...
+info: Entering event queue @ 888900520000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 889837075000. Starting simulation...
-info: Entering event queue @ 896044720500. Starting simulation...
-info: Entering event queue @ 896044727000. Starting simulation...
+info: Entering event queue @ 889900520000. Starting simulation...
+info: Entering event queue @ 896044694500. Starting simulation...
+info: Entering event queue @ 896044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 896044727500. Starting simulation...
+info: Entering event queue @ 896044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 897044727500. Starting simulation...
+info: Entering event queue @ 897044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 898044727500. Starting simulation...
+info: Entering event queue @ 898044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 899044727500. Starting simulation...
-info: Entering event queue @ 906044720500. Starting simulation...
-info: Entering event queue @ 906044727000. Starting simulation...
+info: Entering event queue @ 899044701500. Starting simulation...
+info: Entering event queue @ 906044694500. Starting simulation...
+info: Entering event queue @ 906044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 906044727500. Starting simulation...
+info: Entering event queue @ 906044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 907044727500. Starting simulation...
+info: Entering event queue @ 907044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 908044727500. Starting simulation...
+info: Entering event queue @ 908044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 909044727500. Starting simulation...
-info: Entering event queue @ 916044720500. Starting simulation...
-info: Entering event queue @ 916044727000. Starting simulation...
+info: Entering event queue @ 909044706000. Starting simulation...
+info: Entering event queue @ 916044694500. Starting simulation...
+info: Entering event queue @ 916044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 916044727500. Starting simulation...
+info: Entering event queue @ 916044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 917044727500. Starting simulation...
+info: Entering event queue @ 917044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 918044727500. Starting simulation...
+info: Entering event queue @ 918044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 919044727500. Starting simulation...
-info: Entering event queue @ 926044720500. Starting simulation...
-info: Entering event queue @ 926044727000. Starting simulation...
+info: Entering event queue @ 919044706000. Starting simulation...
+info: Entering event queue @ 926044695500. Starting simulation...
+info: Entering event queue @ 926044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 926044727500. Starting simulation...
+info: Entering event queue @ 926044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 927044727500. Starting simulation...
+info: Entering event queue @ 927044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 928044727500. Starting simulation...
+info: Entering event queue @ 928044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 929044727500. Starting simulation...
-info: Entering event queue @ 936044720500. Starting simulation...
-info: Entering event queue @ 936044727000. Starting simulation...
+info: Entering event queue @ 929044708000. Starting simulation...
+info: Entering event queue @ 936044694500. Starting simulation...
+info: Entering event queue @ 936044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 936044727500. Starting simulation...
+info: Entering event queue @ 936044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 937044727500. Starting simulation...
+info: Entering event queue @ 937044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 938044727500. Starting simulation...
+info: Entering event queue @ 938044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 939044727500. Starting simulation...
-info: Entering event queue @ 946044720500. Starting simulation...
-info: Entering event queue @ 946044727000. Starting simulation...
+info: Entering event queue @ 939044706000. Starting simulation...
+info: Entering event queue @ 946044694500. Starting simulation...
+info: Entering event queue @ 946044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 946044727500. Starting simulation...
+info: Entering event queue @ 946044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 947044727500. Starting simulation...
+info: Entering event queue @ 947044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 948044727500. Starting simulation...
+info: Entering event queue @ 948044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 949044727500. Starting simulation...
-info: Entering event queue @ 956044720500. Starting simulation...
-info: Entering event queue @ 956044727000. Starting simulation...
+info: Entering event queue @ 949044701500. Starting simulation...
+info: Entering event queue @ 956044694500. Starting simulation...
+info: Entering event queue @ 956044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 956044727500. Starting simulation...
+info: Entering event queue @ 956044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 957044727500. Starting simulation...
+info: Entering event queue @ 957044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 958044727500. Starting simulation...
+info: Entering event queue @ 958044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 959044727500. Starting simulation...
-info: Entering event queue @ 966044720500. Starting simulation...
-info: Entering event queue @ 966044727000. Starting simulation...
+info: Entering event queue @ 959044706000. Starting simulation...
+info: Entering event queue @ 966044695500. Starting simulation...
+info: Entering event queue @ 966044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 966044727500. Starting simulation...
+info: Entering event queue @ 966044704000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 967044727500. Starting simulation...
+info: Entering event queue @ 967044704000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 968044727500. Starting simulation...
+info: Entering event queue @ 968044704000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 969044727500. Starting simulation...
-info: Entering event queue @ 976044720500. Starting simulation...
-info: Entering event queue @ 976044727000. Starting simulation...
+info: Entering event queue @ 969044704000. Starting simulation...
+info: Entering event queue @ 976044695500. Starting simulation...
+info: Entering event queue @ 976044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 976044727500. Starting simulation...
+info: Entering event queue @ 976044704000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 977044727500. Starting simulation...
+info: Entering event queue @ 977044704000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 978044727500. Starting simulation...
+info: Entering event queue @ 978044704000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 979044727500. Starting simulation...
-info: Entering event queue @ 986044720500. Starting simulation...
-info: Entering event queue @ 987045796000. Starting simulation...
+info: Entering event queue @ 979044704000. Starting simulation...
+info: Entering event queue @ 986044694500. Starting simulation...
+info: Entering event queue @ 987109151000. Starting simulation...
switching cpus
-info: Entering event queue @ 987045798000. Starting simulation...
+info: Entering event queue @ 987109153000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 988045798000. Starting simulation...
+info: Entering event queue @ 988109153000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 989045798000. Starting simulation...
+info: Entering event queue @ 989109153000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990045798000. Starting simulation...
-info: Entering event queue @ 996044720500. Starting simulation...
-info: Entering event queue @ 996044727000. Starting simulation...
+info: Entering event queue @ 990109153000. Starting simulation...
+info: Entering event queue @ 996044695500. Starting simulation...
+info: Entering event queue @ 996044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 996044727500. Starting simulation...
+info: Entering event queue @ 996044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 997044727500. Starting simulation...
+info: Entering event queue @ 997044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 998044727500. Starting simulation...
+info: Entering event queue @ 998044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 999044727500. Starting simulation...
-info: Entering event queue @ 1006044720500. Starting simulation...
-info: Entering event queue @ 1006044727000. Starting simulation...
+info: Entering event queue @ 999044707000. Starting simulation...
switching cpus
-info: Entering event queue @ 1006044727500. Starting simulation...
+info: Entering event queue @ 1006044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1007044727500. Starting simulation...
+info: Entering event queue @ 1007044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1008044727500. Starting simulation...
+info: Entering event queue @ 1008044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1009044727500. Starting simulation...
-info: Entering event queue @ 1016044720500. Starting simulation...
-info: Entering event queue @ 1016044727000. Starting simulation...
+info: Entering event queue @ 1009044695500. Starting simulation...
+info: Entering event queue @ 1016044694500. Starting simulation...
+info: Entering event queue @ 1016044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1016044727500. Starting simulation...
+info: Entering event queue @ 1016044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1017044727500. Starting simulation...
+info: Entering event queue @ 1017044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1018044727500. Starting simulation...
+info: Entering event queue @ 1018044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1019044727500. Starting simulation...
-info: Entering event queue @ 1026044720500. Starting simulation...
-info: Entering event queue @ 1026044727000. Starting simulation...
+info: Entering event queue @ 1019044706000. Starting simulation...
+info: Entering event queue @ 1026044695500. Starting simulation...
+info: Entering event queue @ 1026044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1026044727500. Starting simulation...
+info: Entering event queue @ 1026044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1027044727500. Starting simulation...
+info: Entering event queue @ 1027044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1028044727500. Starting simulation...
+info: Entering event queue @ 1028044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1029044727500. Starting simulation...
-info: Entering event queue @ 1036044720500. Starting simulation...
-info: Entering event queue @ 1036044727000. Starting simulation...
+info: Entering event queue @ 1029044708000. Starting simulation...
switching cpus
-info: Entering event queue @ 1036044727500. Starting simulation...
+info: Entering event queue @ 1036044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1037044727500. Starting simulation...
+info: Entering event queue @ 1037044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1038044727500. Starting simulation...
+info: Entering event queue @ 1038044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1039044727500. Starting simulation...
-info: Entering event queue @ 1046044720500. Starting simulation...
-info: Entering event queue @ 1046044727000. Starting simulation...
+info: Entering event queue @ 1039044695500. Starting simulation...
+info: Entering event queue @ 1046044694500. Starting simulation...
+info: Entering event queue @ 1046044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1046044727500. Starting simulation...
+info: Entering event queue @ 1046044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1047044727500. Starting simulation...
+info: Entering event queue @ 1047044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1048044727500. Starting simulation...
+info: Entering event queue @ 1048044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1049044727500. Starting simulation...
-info: Entering event queue @ 1056044720500. Starting simulation...
-info: Entering event queue @ 1056044727000. Starting simulation...
+info: Entering event queue @ 1049044706000. Starting simulation...
+info: Entering event queue @ 1056044694500. Starting simulation...
+info: Entering event queue @ 1056044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1056044727500. Starting simulation...
+info: Entering event queue @ 1056044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1057044727500. Starting simulation...
+info: Entering event queue @ 1057044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1058044727500. Starting simulation...
+info: Entering event queue @ 1058044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1059044727500. Starting simulation...
-info: Entering event queue @ 1066044720500. Starting simulation...
-info: Entering event queue @ 1066044727000. Starting simulation...
+info: Entering event queue @ 1059044706000. Starting simulation...
+info: Entering event queue @ 1066044694500. Starting simulation...
+info: Entering event queue @ 1066044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1066044727500. Starting simulation...
+info: Entering event queue @ 1066044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1067044727500. Starting simulation...
+info: Entering event queue @ 1067044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1068044727500. Starting simulation...
+info: Entering event queue @ 1068044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1069044727500. Starting simulation...
-info: Entering event queue @ 1076044720500. Starting simulation...
-info: Entering event queue @ 1076044727000. Starting simulation...
+info: Entering event queue @ 1069044701500. Starting simulation...
+info: Entering event queue @ 1076044694500. Starting simulation...
+info: Entering event queue @ 1076044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1076044727500. Starting simulation...
+info: Entering event queue @ 1076044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1077044727500. Starting simulation...
+info: Entering event queue @ 1077044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1078044727500. Starting simulation...
+info: Entering event queue @ 1078044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1079044727500. Starting simulation...
-info: Entering event queue @ 1086044720500. Starting simulation...
-info: Entering event queue @ 1086044727000. Starting simulation...
+info: Entering event queue @ 1079044706000. Starting simulation...
+info: Entering event queue @ 1086044694500. Starting simulation...
+info: Entering event queue @ 1086044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1086044727500. Starting simulation...
+info: Entering event queue @ 1086044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1087044727500. Starting simulation...
+info: Entering event queue @ 1087044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1088044727500. Starting simulation...
+info: Entering event queue @ 1088044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1089044727500. Starting simulation...
-info: Entering event queue @ 1096044720500. Starting simulation...
-info: Entering event queue @ 1096044727000. Starting simulation...
+info: Entering event queue @ 1089044706000. Starting simulation...
+info: Entering event queue @ 1096044695500. Starting simulation...
+info: Entering event queue @ 1096044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1096044727500. Starting simulation...
+info: Entering event queue @ 1096044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1097044727500. Starting simulation...
+info: Entering event queue @ 1097044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1098044727500. Starting simulation...
+info: Entering event queue @ 1098044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1099044727500. Starting simulation...
-info: Entering event queue @ 1106044720500. Starting simulation...
-info: Entering event queue @ 1106044727000. Starting simulation...
+info: Entering event queue @ 1099044708000. Starting simulation...
+info: Entering event queue @ 1106044694500. Starting simulation...
+info: Entering event queue @ 1106044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1106044727500. Starting simulation...
+info: Entering event queue @ 1106044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1107044727500. Starting simulation...
+info: Entering event queue @ 1107044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1108044727500. Starting simulation...
+info: Entering event queue @ 1108044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1109044727500. Starting simulation...
-info: Entering event queue @ 1116044720500. Starting simulation...
-info: Entering event queue @ 1116044727000. Starting simulation...
+info: Entering event queue @ 1109044706000. Starting simulation...
+info: Entering event queue @ 1116044694500. Starting simulation...
+info: Entering event queue @ 1116044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1116044727500. Starting simulation...
+info: Entering event queue @ 1116044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1117044727500. Starting simulation...
+info: Entering event queue @ 1117044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1118044727500. Starting simulation...
+info: Entering event queue @ 1118044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1119044727500. Starting simulation...
-info: Entering event queue @ 1126044720500. Starting simulation...
-info: Entering event queue @ 1126044727000. Starting simulation...
+info: Entering event queue @ 1119044701500. Starting simulation...
+info: Entering event queue @ 1126044694500. Starting simulation...
+info: Entering event queue @ 1126044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1126044727500. Starting simulation...
+info: Entering event queue @ 1126044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1127044727500. Starting simulation...
+info: Entering event queue @ 1127044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1128044727500. Starting simulation...
+info: Entering event queue @ 1128044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1129044727500. Starting simulation...
-info: Entering event queue @ 1136044720500. Starting simulation...
-info: Entering event queue @ 1136044727000. Starting simulation...
+info: Entering event queue @ 1129044706000. Starting simulation...
+info: Entering event queue @ 1136044695500. Starting simulation...
+info: Entering event queue @ 1136044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1136044727500. Starting simulation...
+info: Entering event queue @ 1136044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1137044727500. Starting simulation...
+info: Entering event queue @ 1137044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1138044727500. Starting simulation...
+info: Entering event queue @ 1138044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1139044727500. Starting simulation...
-info: Entering event queue @ 1146044720500. Starting simulation...
-info: Entering event queue @ 1146044727000. Starting simulation...
+info: Entering event queue @ 1139044707000. Starting simulation...
+info: Entering event queue @ 1146044694500. Starting simulation...
+info: Entering event queue @ 1146044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1146044727500. Starting simulation...
+info: Entering event queue @ 1146044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1147044727500. Starting simulation...
+info: Entering event queue @ 1147044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1148044727500. Starting simulation...
+info: Entering event queue @ 1148044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1149044727500. Starting simulation...
-info: Entering event queue @ 1156044720500. Starting simulation...
-info: Entering event queue @ 1156044727000. Starting simulation...
+info: Entering event queue @ 1149044706000. Starting simulation...
+info: Entering event queue @ 1156044694500. Starting simulation...
+info: Entering event queue @ 1156044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1156044727500. Starting simulation...
+info: Entering event queue @ 1156044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1157044727500. Starting simulation...
+info: Entering event queue @ 1157044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1158044727500. Starting simulation...
+info: Entering event queue @ 1158044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1159044727500. Starting simulation...
-info: Entering event queue @ 1166044720500. Starting simulation...
-info: Entering event queue @ 1166044727000. Starting simulation...
+info: Entering event queue @ 1159044706000. Starting simulation...
+info: Entering event queue @ 1166044695500. Starting simulation...
+info: Entering event queue @ 1166044704000. Starting simulation...
switching cpus
-info: Entering event queue @ 1166044727500. Starting simulation...
+info: Entering event queue @ 1166044708500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1167044727500. Starting simulation...
+info: Entering event queue @ 1167044708500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1168044727500. Starting simulation...
+info: Entering event queue @ 1168044708500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1169044727500. Starting simulation...
-info: Entering event queue @ 1176044720500. Starting simulation...
-info: Entering event queue @ 1176044727000. Starting simulation...
+info: Entering event queue @ 1169044708500. Starting simulation...
switching cpus
-info: Entering event queue @ 1176044727500. Starting simulation...
+info: Entering event queue @ 1176044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1177044727500. Starting simulation...
+info: Entering event queue @ 1177044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1178044727500. Starting simulation...
+info: Entering event queue @ 1178044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1179044727500. Starting simulation...
-info: Entering event queue @ 1186044720500. Starting simulation...
-info: Entering event queue @ 1186044727000. Starting simulation...
+info: Entering event queue @ 1179044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1186044727500. Starting simulation...
+info: Entering event queue @ 1186044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1187044727500. Starting simulation...
+info: Entering event queue @ 1187044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1188044727500. Starting simulation...
+info: Entering event queue @ 1188044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1189044727500. Starting simulation...
-info: Entering event queue @ 1196044720500. Starting simulation...
-info: Entering event queue @ 1196044727000. Starting simulation...
+info: Entering event queue @ 1189044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1196044727500. Starting simulation...
+info: Entering event queue @ 1196044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1197044727500. Starting simulation...
+info: Entering event queue @ 1197044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1198044727500. Starting simulation...
+info: Entering event queue @ 1198044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1199044727500. Starting simulation...
-info: Entering event queue @ 1206044720500. Starting simulation...
-info: Entering event queue @ 1206044727000. Starting simulation...
+info: Entering event queue @ 1199044695500. Starting simulation...
+info: Entering event queue @ 1206044694500. Starting simulation...
+info: Entering event queue @ 1206044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1206044727500. Starting simulation...
+info: Entering event queue @ 1206044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1207044727500. Starting simulation...
+info: Entering event queue @ 1207044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1208044727500. Starting simulation...
+info: Entering event queue @ 1208044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1209044727500. Starting simulation...
-info: Entering event queue @ 1216044720500. Starting simulation...
-info: Entering event queue @ 1216199554000. Starting simulation...
+info: Entering event queue @ 1209044706000. Starting simulation...
+info: Entering event queue @ 1216044695500. Starting simulation...
+info: Entering event queue @ 1216263126000. Starting simulation...
switching cpus
-info: Entering event queue @ 1216199556000. Starting simulation...
+info: Entering event queue @ 1216263128000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1217199556000. Starting simulation...
+info: Entering event queue @ 1217263128000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1218199556000. Starting simulation...
+info: Entering event queue @ 1218263128000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1219199556000. Starting simulation...
-info: Entering event queue @ 1226044720500. Starting simulation...
-info: Entering event queue @ 1226044727000. Starting simulation...
+info: Entering event queue @ 1219263128000. Starting simulation...
+info: Entering event queue @ 1226044694500. Starting simulation...
+info: Entering event queue @ 1226044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1226044727500. Starting simulation...
+info: Entering event queue @ 1226044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1227044727500. Starting simulation...
+info: Entering event queue @ 1227044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1228044727500. Starting simulation...
+info: Entering event queue @ 1228044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1229044727500. Starting simulation...
-info: Entering event queue @ 1236044720500. Starting simulation...
-info: Entering event queue @ 1236044727000. Starting simulation...
+info: Entering event queue @ 1229044701500. Starting simulation...
+info: Entering event queue @ 1236044694500. Starting simulation...
+info: Entering event queue @ 1236044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1236044727500. Starting simulation...
+info: Entering event queue @ 1236044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1237044727500. Starting simulation...
+info: Entering event queue @ 1237044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1238044727500. Starting simulation...
+info: Entering event queue @ 1238044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1239044727500. Starting simulation...
-info: Entering event queue @ 1246044720500. Starting simulation...
-info: Entering event queue @ 1246044727000. Starting simulation...
+info: Entering event queue @ 1239044706000. Starting simulation...
+info: Entering event queue @ 1246044694500. Starting simulation...
+info: Entering event queue @ 1246044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1246044727500. Starting simulation...
+info: Entering event queue @ 1246044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1247044727500. Starting simulation...
+info: Entering event queue @ 1247044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1248044727500. Starting simulation...
-info: Entering event queue @ 1248935845000. Starting simulation...
+info: Entering event queue @ 1248044706000. Starting simulation...
+info: Entering event queue @ 1248999726000. Starting simulation...
switching cpus
-info: Entering event queue @ 1248935847000. Starting simulation...
+info: Entering event queue @ 1248999728000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1249935847000. Starting simulation...
-info: Entering event queue @ 1256044720500. Starting simulation...
-info: Entering event queue @ 1256044727000. Starting simulation...
+info: Entering event queue @ 1249999728000. Starting simulation...
+info: Entering event queue @ 1256044695500. Starting simulation...
+info: Entering event queue @ 1256044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1256044727500. Starting simulation...
+info: Entering event queue @ 1256044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1257044727500. Starting simulation...
+info: Entering event queue @ 1257044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1258044727500. Starting simulation...
+info: Entering event queue @ 1258044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1259044727500. Starting simulation...
-info: Entering event queue @ 1266044720500. Starting simulation...
-info: Entering event queue @ 1266044727000. Starting simulation...
+info: Entering event queue @ 1259044708000. Starting simulation...
+info: Entering event queue @ 1266044694500. Starting simulation...
+info: Entering event queue @ 1266044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1266044727500. Starting simulation...
+info: Entering event queue @ 1266044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1267044727500. Starting simulation...
+info: Entering event queue @ 1267044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1268044727500. Starting simulation...
+info: Entering event queue @ 1268044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1269044727500. Starting simulation...
-info: Entering event queue @ 1276044720500. Starting simulation...
-info: Entering event queue @ 1276044727000. Starting simulation...
+info: Entering event queue @ 1269044706000. Starting simulation...
+info: Entering event queue @ 1276044694500. Starting simulation...
+info: Entering event queue @ 1276044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1276044727500. Starting simulation...
+info: Entering event queue @ 1276044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1277044727500. Starting simulation...
+info: Entering event queue @ 1277044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1278044727500. Starting simulation...
+info: Entering event queue @ 1278044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1279044727500. Starting simulation...
-info: Entering event queue @ 1286044720500. Starting simulation...
-info: Entering event queue @ 1286044727000. Starting simulation...
+info: Entering event queue @ 1279044701500. Starting simulation...
+info: Entering event queue @ 1286044694500. Starting simulation...
+info: Entering event queue @ 1286044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1286044727500. Starting simulation...
+info: Entering event queue @ 1286044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1287044727500. Starting simulation...
+info: Entering event queue @ 1287044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1288044727500. Starting simulation...
+info: Entering event queue @ 1288044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1289044727500. Starting simulation...
-info: Entering event queue @ 1296044720500. Starting simulation...
-info: Entering event queue @ 1296044727000. Starting simulation...
+info: Entering event queue @ 1289044706000. Starting simulation...
+info: Entering event queue @ 1296044695500. Starting simulation...
+info: Entering event queue @ 1296044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1296044727500. Starting simulation...
+info: Entering event queue @ 1296044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1297044727500. Starting simulation...
+info: Entering event queue @ 1297044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1298044727500. Starting simulation...
+info: Entering event queue @ 1298044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1299044727500. Starting simulation...
-info: Entering event queue @ 1306044720500. Starting simulation...
-info: Entering event queue @ 1306044727000. Starting simulation...
+info: Entering event queue @ 1299044707000. Starting simulation...
+info: Entering event queue @ 1306044694500. Starting simulation...
+info: Entering event queue @ 1306044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1306044727500. Starting simulation...
+info: Entering event queue @ 1306044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1307044727500. Starting simulation...
+info: Entering event queue @ 1307044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1308044727500. Starting simulation...
+info: Entering event queue @ 1308044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1309044727500. Starting simulation...
-info: Entering event queue @ 1316044720500. Starting simulation...
-info: Entering event queue @ 1316044727000. Starting simulation...
+info: Entering event queue @ 1309044706000. Starting simulation...
+info: Entering event queue @ 1316044694500. Starting simulation...
+info: Entering event queue @ 1316044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1316044727500. Starting simulation...
+info: Entering event queue @ 1316044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1317044727500. Starting simulation...
+info: Entering event queue @ 1317044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1318044727500. Starting simulation...
+info: Entering event queue @ 1318044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1319044727500. Starting simulation...
-info: Entering event queue @ 1326044720500. Starting simulation...
-info: Entering event queue @ 1326044727000. Starting simulation...
+info: Entering event queue @ 1319044706000. Starting simulation...
+info: Entering event queue @ 1326044695500. Starting simulation...
+info: Entering event queue @ 1326044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1326044727500. Starting simulation...
+info: Entering event queue @ 1326044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1327044727500. Starting simulation...
+info: Entering event queue @ 1327044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1328044727500. Starting simulation...
+info: Entering event queue @ 1328044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1329044727500. Starting simulation...
-info: Entering event queue @ 1336044720500. Starting simulation...
-info: Entering event queue @ 1336044727000. Starting simulation...
+info: Entering event queue @ 1329044707000. Starting simulation...
+info: Entering event queue @ 1336044695500. Starting simulation...
+info: Entering event queue @ 1336044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1336044727500. Starting simulation...
+info: Entering event queue @ 1336044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1337044727500. Starting simulation...
+info: Entering event queue @ 1337044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1338044727500. Starting simulation...
+info: Entering event queue @ 1338044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1339044727500. Starting simulation...
-info: Entering event queue @ 1346044720500. Starting simulation...
-info: Entering event queue @ 1347144421000. Starting simulation...
+info: Entering event queue @ 1339044707000. Starting simulation...
+info: Entering event queue @ 1346044695500. Starting simulation...
+info: Entering event queue @ 1347208355000. Starting simulation...
switching cpus
-info: Entering event queue @ 1347144423000. Starting simulation...
+info: Entering event queue @ 1347208357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1348144423000. Starting simulation...
+info: Entering event queue @ 1348208357000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1349144423000. Starting simulation...
+info: Entering event queue @ 1349208357000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1350144423000. Starting simulation...
-info: Entering event queue @ 1356044720500. Starting simulation...
-info: Entering event queue @ 1356044727000. Starting simulation...
+info: Entering event queue @ 1350208357000. Starting simulation...
switching cpus
-info: Entering event queue @ 1356044727500. Starting simulation...
+info: Entering event queue @ 1356044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1357044727500. Starting simulation...
+info: Entering event queue @ 1357044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1358044727500. Starting simulation...
+info: Entering event queue @ 1358044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1359044727500. Starting simulation...
-info: Entering event queue @ 1366044720500. Starting simulation...
-info: Entering event queue @ 1366044727000. Starting simulation...
+info: Entering event queue @ 1359044695500. Starting simulation...
+info: Entering event queue @ 1366044694500. Starting simulation...
+info: Entering event queue @ 1366044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1366044727500. Starting simulation...
+info: Entering event queue @ 1366044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1367044727500. Starting simulation...
+info: Entering event queue @ 1367044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1368044727500. Starting simulation...
+info: Entering event queue @ 1368044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1369044727500. Starting simulation...
-info: Entering event queue @ 1376044720500. Starting simulation...
-info: Entering event queue @ 1376044727000. Starting simulation...
+info: Entering event queue @ 1369044706000. Starting simulation...
+info: Entering event queue @ 1376044695500. Starting simulation...
+info: Entering event queue @ 1376044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1376044727500. Starting simulation...
+info: Entering event queue @ 1376044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1377044727500. Starting simulation...
+info: Entering event queue @ 1377044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1378044727500. Starting simulation...
+info: Entering event queue @ 1378044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1379044727500. Starting simulation...
-info: Entering event queue @ 1386044720500. Starting simulation...
-info: Entering event queue @ 1386044727000. Starting simulation...
+info: Entering event queue @ 1379044708000. Starting simulation...
+info: Entering event queue @ 1386044694500. Starting simulation...
+info: Entering event queue @ 1386044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1386044727500. Starting simulation...
+info: Entering event queue @ 1386044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1387044727500. Starting simulation...
+info: Entering event queue @ 1387044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1388044727500. Starting simulation...
+info: Entering event queue @ 1388044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1389044727500. Starting simulation...
-info: Entering event queue @ 1396044720500. Starting simulation...
-info: Entering event queue @ 1396044727000. Starting simulation...
+info: Entering event queue @ 1389044701500. Starting simulation...
+info: Entering event queue @ 1396044694500. Starting simulation...
+info: Entering event queue @ 1396044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1396044727500. Starting simulation...
+info: Entering event queue @ 1396044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1397044727500. Starting simulation...
+info: Entering event queue @ 1397044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1398044727500. Starting simulation...
+info: Entering event queue @ 1398044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1399044727500. Starting simulation...
-info: Entering event queue @ 1406044720500. Starting simulation...
-info: Entering event queue @ 1406044727000. Starting simulation...
+info: Entering event queue @ 1399044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 1406044727500. Starting simulation...
+info: Entering event queue @ 1406044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1407044727500. Starting simulation...
+info: Entering event queue @ 1407044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1408044727500. Starting simulation...
+info: Entering event queue @ 1408044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1409044727500. Starting simulation...
-info: Entering event queue @ 1416044720500. Starting simulation...
-info: Entering event queue @ 1416044727000. Starting simulation...
+info: Entering event queue @ 1409044695500. Starting simulation...
+info: Entering event queue @ 1416044694500. Starting simulation...
+info: Entering event queue @ 1416044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1416044727500. Starting simulation...
+info: Entering event queue @ 1416044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1417044727500. Starting simulation...
+info: Entering event queue @ 1417044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1418044727500. Starting simulation...
+info: Entering event queue @ 1418044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1419044727500. Starting simulation...
-info: Entering event queue @ 1426044720500. Starting simulation...
-info: Entering event queue @ 1426044727000. Starting simulation...
+info: Entering event queue @ 1419044706000. Starting simulation...
+info: Entering event queue @ 1426044694500. Starting simulation...
+info: Entering event queue @ 1426044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1426044727500. Starting simulation...
+info: Entering event queue @ 1426044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1427044727500. Starting simulation...
+info: Entering event queue @ 1427044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1428044727500. Starting simulation...
+info: Entering event queue @ 1428044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1429044727500. Starting simulation...
-info: Entering event queue @ 1436044720500. Starting simulation...
-info: Entering event queue @ 1436044727000. Starting simulation...
+info: Entering event queue @ 1429044706000. Starting simulation...
+info: Entering event queue @ 1436044694500. Starting simulation...
+info: Entering event queue @ 1436044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1436044727500. Starting simulation...
+info: Entering event queue @ 1436044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1437044727500. Starting simulation...
+info: Entering event queue @ 1437044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1438044727500. Starting simulation...
+info: Entering event queue @ 1438044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1439044727500. Starting simulation...
-info: Entering event queue @ 1446044720500. Starting simulation...
-info: Entering event queue @ 1446044727000. Starting simulation...
+info: Entering event queue @ 1439044701500. Starting simulation...
+info: Entering event queue @ 1446044694500. Starting simulation...
+info: Entering event queue @ 1446044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1446044727500. Starting simulation...
+info: Entering event queue @ 1446044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1447044727500. Starting simulation...
+info: Entering event queue @ 1447044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1448044727500. Starting simulation...
+info: Entering event queue @ 1448044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1449044727500. Starting simulation...
-info: Entering event queue @ 1456044720500. Starting simulation...
-info: Entering event queue @ 1456044727000. Starting simulation...
+info: Entering event queue @ 1449044706000. Starting simulation...
+info: Entering event queue @ 1456044695500. Starting simulation...
+info: Entering event queue @ 1456044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1456044727500. Starting simulation...
+info: Entering event queue @ 1456044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1457044727500. Starting simulation...
+info: Entering event queue @ 1457044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1458044727500. Starting simulation...
+info: Entering event queue @ 1458044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1459044727500. Starting simulation...
-info: Entering event queue @ 1466044720500. Starting simulation...
-info: Entering event queue @ 1466044727000. Starting simulation...
+info: Entering event queue @ 1459044707000. Starting simulation...
+info: Entering event queue @ 1466044694500. Starting simulation...
+info: Entering event queue @ 1466044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1466044727500. Starting simulation...
+info: Entering event queue @ 1466044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1467044727500. Starting simulation...
+info: Entering event queue @ 1467044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1468044727500. Starting simulation...
+info: Entering event queue @ 1468044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1469044727500. Starting simulation...
-info: Entering event queue @ 1476044720500. Starting simulation...
-info: Entering event queue @ 1476044727000. Starting simulation...
+info: Entering event queue @ 1469044706000. Starting simulation...
+info: Entering event queue @ 1476044694500. Starting simulation...
+info: Entering event queue @ 1476044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1476044727500. Starting simulation...
+info: Entering event queue @ 1476044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1477044727500. Starting simulation...
+info: Entering event queue @ 1477044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1478044727500. Starting simulation...
+info: Entering event queue @ 1478044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1479044727500. Starting simulation...
-info: Entering event queue @ 1486044720500. Starting simulation...
-info: Entering event queue @ 1486044727000. Starting simulation...
+info: Entering event queue @ 1479044706000. Starting simulation...
+info: Entering event queue @ 1486044695500. Starting simulation...
+info: Entering event queue @ 1486044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1486044727500. Starting simulation...
+info: Entering event queue @ 1486044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1487044727500. Starting simulation...
+info: Entering event queue @ 1487044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1488044727500. Starting simulation...
+info: Entering event queue @ 1488044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1489044727500. Starting simulation...
-info: Entering event queue @ 1496044720500. Starting simulation...
-info: Entering event queue @ 1496044727000. Starting simulation...
+info: Entering event queue @ 1489044707000. Starting simulation...
+info: Entering event queue @ 1496044695500. Starting simulation...
+info: Entering event queue @ 1496044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1496044727500. Starting simulation...
+info: Entering event queue @ 1496044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1497044727500. Starting simulation...
+info: Entering event queue @ 1497044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1498044727500. Starting simulation...
+info: Entering event queue @ 1498044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1499044727500. Starting simulation...
-info: Entering event queue @ 1506044720500. Starting simulation...
-info: Entering event queue @ 1506044727000. Starting simulation...
+info: Entering event queue @ 1499044707000. Starting simulation...
switching cpus
-info: Entering event queue @ 1506044727500. Starting simulation...
+info: Entering event queue @ 1506044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1507044727500. Starting simulation...
+info: Entering event queue @ 1507044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1508044727500. Starting simulation...
+info: Entering event queue @ 1508044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1509044727500. Starting simulation...
-info: Entering event queue @ 1516044720500. Starting simulation...
-info: Entering event queue @ 1516044727000. Starting simulation...
+info: Entering event queue @ 1509044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1516044727500. Starting simulation...
+info: Entering event queue @ 1516044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1517044727500. Starting simulation...
+info: Entering event queue @ 1517044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1518044727500. Starting simulation...
+info: Entering event queue @ 1518044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1519044727500. Starting simulation...
-info: Entering event queue @ 1526044720500. Starting simulation...
-info: Entering event queue @ 1526044727000. Starting simulation...
+info: Entering event queue @ 1519044695500. Starting simulation...
+info: Entering event queue @ 1526044694500. Starting simulation...
+info: Entering event queue @ 1526044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1526044727500. Starting simulation...
+info: Entering event queue @ 1526044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1527044727500. Starting simulation...
+info: Entering event queue @ 1527044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1528044727500. Starting simulation...
+info: Entering event queue @ 1528044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1529044727500. Starting simulation...
-info: Entering event queue @ 1536044720500. Starting simulation...
-info: Entering event queue @ 1536044727000. Starting simulation...
+info: Entering event queue @ 1529044706000. Starting simulation...
+info: Entering event queue @ 1536044695500. Starting simulation...
+info: Entering event queue @ 1536044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1536044727500. Starting simulation...
+info: Entering event queue @ 1536044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1537044727500. Starting simulation...
+info: Entering event queue @ 1537044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1538044727500. Starting simulation...
+info: Entering event queue @ 1538044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1539044727500. Starting simulation...
-info: Entering event queue @ 1546044720500. Starting simulation...
-info: Entering event queue @ 1546044727000. Starting simulation...
+info: Entering event queue @ 1539044708000. Starting simulation...
+info: Entering event queue @ 1546044694500. Starting simulation...
+info: Entering event queue @ 1546044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1546044727500. Starting simulation...
+info: Entering event queue @ 1546044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1547044727500. Starting simulation...
+info: Entering event queue @ 1547044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1548044727500. Starting simulation...
+info: Entering event queue @ 1548044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1549044727500. Starting simulation...
-info: Entering event queue @ 1556044720500. Starting simulation...
-info: Entering event queue @ 1556044727000. Starting simulation...
+info: Entering event queue @ 1549044701500. Starting simulation...
+info: Entering event queue @ 1556044694500. Starting simulation...
+info: Entering event queue @ 1556044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1556044727500. Starting simulation...
+info: Entering event queue @ 1556044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1557044727500. Starting simulation...
+info: Entering event queue @ 1557044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1558044727500. Starting simulation...
+info: Entering event queue @ 1558044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1559044727500. Starting simulation...
-info: Entering event queue @ 1566044720500. Starting simulation...
-info: Entering event queue @ 1566044727000. Starting simulation...
+info: Entering event queue @ 1559044706000. Starting simulation...
+info: Entering event queue @ 1566044695500. Starting simulation...
+info: Entering event queue @ 1566044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1566044727500. Starting simulation...
+info: Entering event queue @ 1566044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1567044727500. Starting simulation...
+info: Entering event queue @ 1567044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1568044727500. Starting simulation...
+info: Entering event queue @ 1568044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1569044727500. Starting simulation...
-info: Entering event queue @ 1576044720500. Starting simulation...
-info: Entering event queue @ 1576298326000. Starting simulation...
+info: Entering event queue @ 1569044708000. Starting simulation...
+info: Entering event queue @ 1576044695500. Starting simulation...
+info: Entering event queue @ 1576362334000. Starting simulation...
switching cpus
-info: Entering event queue @ 1576298328000. Starting simulation...
+info: Entering event queue @ 1576362336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1577298328000. Starting simulation...
+info: Entering event queue @ 1577362336000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1578298328000. Starting simulation...
+info: Entering event queue @ 1578362336000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1579298328000. Starting simulation...
-info: Entering event queue @ 1586044720500. Starting simulation...
-info: Entering event queue @ 1586044727000. Starting simulation...
+info: Entering event queue @ 1579362336000. Starting simulation...
+info: Entering event queue @ 1586044695500. Starting simulation...
+info: Entering event queue @ 1586044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1586044727500. Starting simulation...
+info: Entering event queue @ 1586044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1587044727500. Starting simulation...
+info: Entering event queue @ 1587044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1588044727500. Starting simulation...
+info: Entering event queue @ 1588044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1589044727500. Starting simulation...
-info: Entering event queue @ 1596044720500. Starting simulation...
-info: Entering event queue @ 1596044727000. Starting simulation...
+info: Entering event queue @ 1589044708000. Starting simulation...
+info: Entering event queue @ 1596044694500. Starting simulation...
+info: Entering event queue @ 1596044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1596044727500. Starting simulation...
+info: Entering event queue @ 1596044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1597044727500. Starting simulation...
+info: Entering event queue @ 1597044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1598044727500. Starting simulation...
+info: Entering event queue @ 1598044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1599044727500. Starting simulation...
-info: Entering event queue @ 1606044720500. Starting simulation...
-info: Entering event queue @ 1606044727000. Starting simulation...
+info: Entering event queue @ 1599044701500. Starting simulation...
+info: Entering event queue @ 1606044695500. Starting simulation...
+info: Entering event queue @ 1606044703000. Starting simulation...
switching cpus
-info: Entering event queue @ 1606044727500. Starting simulation...
+info: Entering event queue @ 1606044703500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1607044727500. Starting simulation...
+info: Entering event queue @ 1607044703500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1608044727500. Starting simulation...
-info: Entering event queue @ 1609034473000. Starting simulation...
+info: Entering event queue @ 1608044703500. Starting simulation...
+info: Entering event queue @ 1609097918000. Starting simulation...
switching cpus
-info: Entering event queue @ 1609034475000. Starting simulation...
+info: Entering event queue @ 1609097920000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610034475000. Starting simulation...
-info: Entering event queue @ 1616044720500. Starting simulation...
-info: Entering event queue @ 1616044727000. Starting simulation...
+info: Entering event queue @ 1610097920000. Starting simulation...
+info: Entering event queue @ 1616044694500. Starting simulation...
+info: Entering event queue @ 1616044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1616044727500. Starting simulation...
+info: Entering event queue @ 1616044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1617044727500. Starting simulation...
+info: Entering event queue @ 1617044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1618044727500. Starting simulation...
+info: Entering event queue @ 1618044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1619044727500. Starting simulation...
-info: Entering event queue @ 1626044720500. Starting simulation...
-info: Entering event queue @ 1626044727000. Starting simulation...
+info: Entering event queue @ 1619044706000. Starting simulation...
+info: Entering event queue @ 1626044694500. Starting simulation...
+info: Entering event queue @ 1626044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1626044727500. Starting simulation...
+info: Entering event queue @ 1626044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1627044727500. Starting simulation...
+info: Entering event queue @ 1627044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1628044727500. Starting simulation...
+info: Entering event queue @ 1628044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1629044727500. Starting simulation...
-info: Entering event queue @ 1636044720500. Starting simulation...
-info: Entering event queue @ 1636044727000. Starting simulation...
+info: Entering event queue @ 1629044706000. Starting simulation...
+info: Entering event queue @ 1636044694500. Starting simulation...
+info: Entering event queue @ 1636044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1636044727500. Starting simulation...
+info: Entering event queue @ 1636044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1637044727500. Starting simulation...
+info: Entering event queue @ 1637044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1638044727500. Starting simulation...
+info: Entering event queue @ 1638044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1639044727500. Starting simulation...
-info: Entering event queue @ 1646044720500. Starting simulation...
-info: Entering event queue @ 1646044727000. Starting simulation...
+info: Entering event queue @ 1639044706000. Starting simulation...
+info: Entering event queue @ 1646044695500. Starting simulation...
+info: Entering event queue @ 1646044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1646044727500. Starting simulation...
+info: Entering event queue @ 1646044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1647044727500. Starting simulation...
+info: Entering event queue @ 1647044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1648044727500. Starting simulation...
+info: Entering event queue @ 1648044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1649044727500. Starting simulation...
-info: Entering event queue @ 1656044720500. Starting simulation...
-info: Entering event queue @ 1656044727000. Starting simulation...
+info: Entering event queue @ 1649044707000. Starting simulation...
+info: Entering event queue @ 1656044695500. Starting simulation...
+info: Entering event queue @ 1656044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1656044727500. Starting simulation...
+info: Entering event queue @ 1656044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1657044727500. Starting simulation...
+info: Entering event queue @ 1657044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1658044727500. Starting simulation...
+info: Entering event queue @ 1658044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1659044727500. Starting simulation...
-info: Entering event queue @ 1666044720500. Starting simulation...
-info: Entering event queue @ 1666044727000. Starting simulation...
+info: Entering event queue @ 1659044707000. Starting simulation...
switching cpus
-info: Entering event queue @ 1666044727500. Starting simulation...
+info: Entering event queue @ 1666044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1667044727500. Starting simulation...
+info: Entering event queue @ 1667044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1668044727500. Starting simulation...
+info: Entering event queue @ 1668044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1669044727500. Starting simulation...
-info: Entering event queue @ 1676044720500. Starting simulation...
-info: Entering event queue @ 1676044727000. Starting simulation...
+info: Entering event queue @ 1669044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1676044727500. Starting simulation...
+info: Entering event queue @ 1676044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1677044727500. Starting simulation...
+info: Entering event queue @ 1677044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1678044727500. Starting simulation...
+info: Entering event queue @ 1678044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1679044727500. Starting simulation...
-info: Entering event queue @ 1686044720500. Starting simulation...
-info: Entering event queue @ 1686044727000. Starting simulation...
+info: Entering event queue @ 1679044695500. Starting simulation...
+info: Entering event queue @ 1686044694500. Starting simulation...
+info: Entering event queue @ 1686044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1686044727500. Starting simulation...
+info: Entering event queue @ 1686044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1687044727500. Starting simulation...
+info: Entering event queue @ 1687044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1688044727500. Starting simulation...
+info: Entering event queue @ 1688044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1689044727500. Starting simulation...
-info: Entering event queue @ 1696044720500. Starting simulation...
-info: Entering event queue @ 1696044727000. Starting simulation...
+info: Entering event queue @ 1689044706000. Starting simulation...
+info: Entering event queue @ 1696044695500. Starting simulation...
+info: Entering event queue @ 1696044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1696044727500. Starting simulation...
+info: Entering event queue @ 1696044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1697044727500. Starting simulation...
+info: Entering event queue @ 1697044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1698044727500. Starting simulation...
+info: Entering event queue @ 1698044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1699044727500. Starting simulation...
-info: Entering event queue @ 1706044720500. Starting simulation...
-info: Entering event queue @ 1707243505000. Starting simulation...
+info: Entering event queue @ 1699044708000. Starting simulation...
+info: Entering event queue @ 1706044694500. Starting simulation...
+info: Entering event queue @ 1707307739000. Starting simulation...
switching cpus
-info: Entering event queue @ 1707243507000. Starting simulation...
+info: Entering event queue @ 1707307741000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1708243507000. Starting simulation...
+info: Entering event queue @ 1708307741000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1709243507000. Starting simulation...
+info: Entering event queue @ 1709307741000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1710243507000. Starting simulation...
-info: Entering event queue @ 1716044720500. Starting simulation...
-info: Entering event queue @ 1716044727000. Starting simulation...
+info: Entering event queue @ 1710307741000. Starting simulation...
+info: Entering event queue @ 1716044694500. Starting simulation...
+info: Entering event queue @ 1716044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1716044727500. Starting simulation...
+info: Entering event queue @ 1716044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1717044727500. Starting simulation...
+info: Entering event queue @ 1717044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1718044727500. Starting simulation...
+info: Entering event queue @ 1718044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1719044727500. Starting simulation...
-info: Entering event queue @ 1726044720500. Starting simulation...
-info: Entering event queue @ 1726044727000. Starting simulation...
+info: Entering event queue @ 1719044706000. Starting simulation...
+info: Entering event queue @ 1726044694500. Starting simulation...
+info: Entering event queue @ 1726044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1726044727500. Starting simulation...
+info: Entering event queue @ 1726044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1727044727500. Starting simulation...
+info: Entering event queue @ 1727044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1728044727500. Starting simulation...
+info: Entering event queue @ 1728044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1729044727500. Starting simulation...
-info: Entering event queue @ 1736044720500. Starting simulation...
-info: Entering event queue @ 1736044727000. Starting simulation...
+info: Entering event queue @ 1729044706000. Starting simulation...
+info: Entering event queue @ 1736044695500. Starting simulation...
+info: Entering event queue @ 1736044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1736044727500. Starting simulation...
+info: Entering event queue @ 1736044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1737044727500. Starting simulation...
+info: Entering event queue @ 1737044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1738044727500. Starting simulation...
+info: Entering event queue @ 1738044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1739044727500. Starting simulation...
-info: Entering event queue @ 1746044720500. Starting simulation...
-info: Entering event queue @ 1746044727000. Starting simulation...
+info: Entering event queue @ 1739044708000. Starting simulation...
+info: Entering event queue @ 1746044695500. Starting simulation...
+info: Entering event queue @ 1746044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 1746044727500. Starting simulation...
+info: Entering event queue @ 1746044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1747044727500. Starting simulation...
+info: Entering event queue @ 1747044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1748044727500. Starting simulation...
+info: Entering event queue @ 1748044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1749044727500. Starting simulation...
-info: Entering event queue @ 1756044720500. Starting simulation...
-info: Entering event queue @ 1756044727000. Starting simulation...
+info: Entering event queue @ 1749044707000. Starting simulation...
+info: Entering event queue @ 1756044694500. Starting simulation...
+info: Entering event queue @ 1756044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1756044727500. Starting simulation...
+info: Entering event queue @ 1756044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1757044727500. Starting simulation...
+info: Entering event queue @ 1757044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1758044727500. Starting simulation...
+info: Entering event queue @ 1758044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1759044727500. Starting simulation...
-info: Entering event queue @ 1766044720500. Starting simulation...
-info: Entering event queue @ 1766044727000. Starting simulation...
+info: Entering event queue @ 1759044701500. Starting simulation...
+info: Entering event queue @ 1766044694500. Starting simulation...
+info: Entering event queue @ 1766044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1766044727500. Starting simulation...
+info: Entering event queue @ 1766044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1767044727500. Starting simulation...
+info: Entering event queue @ 1767044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1768044727500. Starting simulation...
+info: Entering event queue @ 1768044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769044727500. Starting simulation...
-info: Entering event queue @ 1776044720500. Starting simulation...
-info: Entering event queue @ 1776044727000. Starting simulation...
+info: Entering event queue @ 1769044706000. Starting simulation...
+info: Entering event queue @ 1776044695500. Starting simulation...
+info: Entering event queue @ 1776044703000. Starting simulation...
switching cpus
-info: Entering event queue @ 1776044727500. Starting simulation...
+info: Entering event queue @ 1776044703500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1777044727500. Starting simulation...
+info: Entering event queue @ 1777044703500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1778044727500. Starting simulation...
+info: Entering event queue @ 1778044703500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1779044727500. Starting simulation...
-info: Entering event queue @ 1786044720500. Starting simulation...
-info: Entering event queue @ 1786044727000. Starting simulation...
+info: Entering event queue @ 1779044703500. Starting simulation...
+info: Entering event queue @ 1786044694500. Starting simulation...
+info: Entering event queue @ 1786044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1786044727500. Starting simulation...
+info: Entering event queue @ 1786044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1787044727500. Starting simulation...
+info: Entering event queue @ 1787044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1788044727500. Starting simulation...
+info: Entering event queue @ 1788044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1789044727500. Starting simulation...
-info: Entering event queue @ 1796044720500. Starting simulation...
-info: Entering event queue @ 1796044727000. Starting simulation...
+info: Entering event queue @ 1789044706000. Starting simulation...
+info: Entering event queue @ 1796044694500. Starting simulation...
+info: Entering event queue @ 1796044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1796044727500. Starting simulation...
+info: Entering event queue @ 1796044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1797044727500. Starting simulation...
+info: Entering event queue @ 1797044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1798044727500. Starting simulation...
+info: Entering event queue @ 1798044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1799044727500. Starting simulation...
-info: Entering event queue @ 1806044720500. Starting simulation...
-info: Entering event queue @ 1806044727000. Starting simulation...
+info: Entering event queue @ 1799044706000. Starting simulation...
+info: Entering event queue @ 1806044695500. Starting simulation...
+info: Entering event queue @ 1806044704000. Starting simulation...
switching cpus
-info: Entering event queue @ 1806044727500. Starting simulation...
+info: Entering event queue @ 1806044704500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1807044727500. Starting simulation...
+info: Entering event queue @ 1807044704500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1808044727500. Starting simulation...
+info: Entering event queue @ 1808044704500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1809044727500. Starting simulation...
-info: Entering event queue @ 1816044720500. Starting simulation...
-info: Entering event queue @ 1816044727000. Starting simulation...
+info: Entering event queue @ 1809044704500. Starting simulation...
+info: Entering event queue @ 1816044694500. Starting simulation...
+info: Entering event queue @ 1816044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1816044727500. Starting simulation...
+info: Entering event queue @ 1816044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1817044727500. Starting simulation...
+info: Entering event queue @ 1817044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1818044727500. Starting simulation...
+info: Entering event queue @ 1818044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819044727500. Starting simulation...
-info: Entering event queue @ 1826044720500. Starting simulation...
-info: Entering event queue @ 1826044727000. Starting simulation...
+info: Entering event queue @ 1819044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 1826044727500. Starting simulation...
+info: Entering event queue @ 1826044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1827044727500. Starting simulation...
+info: Entering event queue @ 1827044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1828044727500. Starting simulation...
+info: Entering event queue @ 1828044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1829044727500. Starting simulation...
-info: Entering event queue @ 1836044720500. Starting simulation...
-info: Entering event queue @ 1836044727000. Starting simulation...
+info: Entering event queue @ 1829044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1836044727500. Starting simulation...
+info: Entering event queue @ 1836044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1837044727500. Starting simulation...
+info: Entering event queue @ 1837044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1838044727500. Starting simulation...
+info: Entering event queue @ 1838044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839044727500. Starting simulation...
-info: Entering event queue @ 1846044720500. Starting simulation...
-info: Entering event queue @ 1846044727000. Starting simulation...
+info: Entering event queue @ 1839044695500. Starting simulation...
+info: Entering event queue @ 1846044694500. Starting simulation...
+info: Entering event queue @ 1846044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1846044727500. Starting simulation...
+info: Entering event queue @ 1846044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1847044727500. Starting simulation...
+info: Entering event queue @ 1847044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1848044727500. Starting simulation...
+info: Entering event queue @ 1848044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1849044727500. Starting simulation...
-info: Entering event queue @ 1856044720500. Starting simulation...
-info: Entering event queue @ 1856044727000. Starting simulation...
+info: Entering event queue @ 1849044706000. Starting simulation...
+info: Entering event queue @ 1856044695500. Starting simulation...
+info: Entering event queue @ 1856044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1856044727500. Starting simulation...
+info: Entering event queue @ 1856044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1857044727500. Starting simulation...
+info: Entering event queue @ 1857044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1858044727500. Starting simulation...
+info: Entering event queue @ 1858044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1859044727500. Starting simulation...
-info: Entering event queue @ 1866044720500. Starting simulation...
-info: Entering event queue @ 1866044727000. Starting simulation...
+info: Entering event queue @ 1859044708000. Starting simulation...
+info: Entering event queue @ 1866044694500. Starting simulation...
+info: Entering event queue @ 1866044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1866044727500. Starting simulation...
+info: Entering event queue @ 1866044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1867044727500. Starting simulation...
+info: Entering event queue @ 1867044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1868044727500. Starting simulation...
+info: Entering event queue @ 1868044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1869044727500. Starting simulation...
-info: Entering event queue @ 1876044720500. Starting simulation...
-info: Entering event queue @ 1876044727000. Starting simulation...
+info: Entering event queue @ 1869044701500. Starting simulation...
+info: Entering event queue @ 1876044694500. Starting simulation...
+info: Entering event queue @ 1876044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1876044727500. Starting simulation...
+info: Entering event queue @ 1876044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1877044727500. Starting simulation...
+info: Entering event queue @ 1877044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1878044727500. Starting simulation...
+info: Entering event queue @ 1878044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1879044727500. Starting simulation...
-info: Entering event queue @ 1886044720500. Starting simulation...
-info: Entering event queue @ 1886044727000. Starting simulation...
+info: Entering event queue @ 1879044706000. Starting simulation...
+info: Entering event queue @ 1886044694500. Starting simulation...
+info: Entering event queue @ 1886044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1886044727500. Starting simulation...
+info: Entering event queue @ 1886044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1887044727500. Starting simulation...
+info: Entering event queue @ 1887044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1888044727500. Starting simulation...
+info: Entering event queue @ 1888044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1889044727500. Starting simulation...
-info: Entering event queue @ 1896044720500. Starting simulation...
-info: Entering event queue @ 1896044727000. Starting simulation...
+info: Entering event queue @ 1889044706000. Starting simulation...
+info: Entering event queue @ 1896044695500. Starting simulation...
+info: Entering event queue @ 1896044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1896044727500. Starting simulation...
+info: Entering event queue @ 1896044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1897044727500. Starting simulation...
+info: Entering event queue @ 1897044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1898044727500. Starting simulation...
+info: Entering event queue @ 1898044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1899044727500. Starting simulation...
-info: Entering event queue @ 1906044720500. Starting simulation...
-info: Entering event queue @ 1906044727000. Starting simulation...
+info: Entering event queue @ 1899044708000. Starting simulation...
switching cpus
-info: Entering event queue @ 1906044727500. Starting simulation...
+info: Entering event queue @ 1906044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1907044727500. Starting simulation...
+info: Entering event queue @ 1907044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1908044727500. Starting simulation...
+info: Entering event queue @ 1908044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1909044727500. Starting simulation...
-info: Entering event queue @ 1916044720500. Starting simulation...
-info: Entering event queue @ 1916044727000. Starting simulation...
+info: Entering event queue @ 1909044695500. Starting simulation...
+info: Entering event queue @ 1916044694500. Starting simulation...
+info: Entering event queue @ 1916044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 1916044727500. Starting simulation...
+info: Entering event queue @ 1916044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1917044727500. Starting simulation...
+info: Entering event queue @ 1917044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1918044727500. Starting simulation...
+info: Entering event queue @ 1918044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1919044727500. Starting simulation...
-info: Entering event queue @ 1926044720500. Starting simulation...
-info: Entering event queue @ 1926044727000. Starting simulation...
+info: Entering event queue @ 1919044701500. Starting simulation...
+info: Entering event queue @ 1926044694500. Starting simulation...
+info: Entering event queue @ 1926044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1926044727500. Starting simulation...
+info: Entering event queue @ 1926044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1927044727500. Starting simulation...
+info: Entering event queue @ 1927044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1928044727500. Starting simulation...
+info: Entering event queue @ 1928044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1929044727500. Starting simulation...
-info: Entering event queue @ 1936044720500. Starting simulation...
-info: Entering event queue @ 1936397407000. Starting simulation...
+info: Entering event queue @ 1929044706000. Starting simulation...
+info: Entering event queue @ 1936044695500. Starting simulation...
+info: Entering event queue @ 1936460526000. Starting simulation...
switching cpus
-info: Entering event queue @ 1936397409000. Starting simulation...
+info: Entering event queue @ 1936460528000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1937397409000. Starting simulation...
+info: Entering event queue @ 1937460528000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1938397409000. Starting simulation...
+info: Entering event queue @ 1938460528000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1939397409000. Starting simulation...
-info: Entering event queue @ 1946044720500. Starting simulation...
-info: Entering event queue @ 1946044727000. Starting simulation...
+info: Entering event queue @ 1939460528000. Starting simulation...
+info: Entering event queue @ 1946044694500. Starting simulation...
+info: Entering event queue @ 1946044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1946044727500. Starting simulation...
+info: Entering event queue @ 1946044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1947044727500. Starting simulation...
+info: Entering event queue @ 1947044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1948044727500. Starting simulation...
+info: Entering event queue @ 1948044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1949044727500. Starting simulation...
-info: Entering event queue @ 1956044720500. Starting simulation...
-info: Entering event queue @ 1956044727000. Starting simulation...
+info: Entering event queue @ 1949044706000. Starting simulation...
+info: Entering event queue @ 1956044694500. Starting simulation...
+info: Entering event queue @ 1956044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 1956044727500. Starting simulation...
+info: Entering event queue @ 1956044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1957044727500. Starting simulation...
+info: Entering event queue @ 1957044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1958044727500. Starting simulation...
+info: Entering event queue @ 1958044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1959044727500. Starting simulation...
-info: Entering event queue @ 1966044720500. Starting simulation...
-info: Entering event queue @ 1966044727000. Starting simulation...
+info: Entering event queue @ 1959044706000. Starting simulation...
+info: Entering event queue @ 1966044695500. Starting simulation...
+info: Entering event queue @ 1966044704000. Starting simulation...
switching cpus
-info: Entering event queue @ 1966044727500. Starting simulation...
+info: Entering event queue @ 1966044704500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1967044727500. Starting simulation...
+info: Entering event queue @ 1967044704500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1968044727500. Starting simulation...
-info: Entering event queue @ 1969133554000. Starting simulation...
+info: Entering event queue @ 1968044704500. Starting simulation...
+info: Entering event queue @ 1969197126000. Starting simulation...
switching cpus
-info: Entering event queue @ 1969133556000. Starting simulation...
+info: Entering event queue @ 1969197128000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1970133556000. Starting simulation...
-info: Entering event queue @ 1976044720500. Starting simulation...
-info: Entering event queue @ 1976044727000. Starting simulation...
+info: Entering event queue @ 1970197128000. Starting simulation...
+info: Entering event queue @ 1976044695500. Starting simulation...
+info: Entering event queue @ 1976044703000. Starting simulation...
switching cpus
-info: Entering event queue @ 1976044727500. Starting simulation...
+info: Entering event queue @ 1976044703500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1977044727500. Starting simulation...
+info: Entering event queue @ 1977044703500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1978044727500. Starting simulation...
+info: Entering event queue @ 1978044703500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1979044727500. Starting simulation...
-info: Entering event queue @ 1986044720500. Starting simulation...
-info: Entering event queue @ 1986044727000. Starting simulation...
+info: Entering event queue @ 1979044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 1986044727500. Starting simulation...
+info: Entering event queue @ 1986044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1987044727500. Starting simulation...
+info: Entering event queue @ 1987044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1988044727500. Starting simulation...
+info: Entering event queue @ 1988044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1989044727500. Starting simulation...
-info: Entering event queue @ 1996044720500. Starting simulation...
-info: Entering event queue @ 1996044727000. Starting simulation...
+info: Entering event queue @ 1989044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 1996044727500. Starting simulation...
+info: Entering event queue @ 1996044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1997044727500. Starting simulation...
+info: Entering event queue @ 1997044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1998044727500. Starting simulation...
+info: Entering event queue @ 1998044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1999044727500. Starting simulation...
-info: Entering event queue @ 2006044720500. Starting simulation...
-info: Entering event queue @ 2006044727000. Starting simulation...
+info: Entering event queue @ 1999044695500. Starting simulation...
+info: Entering event queue @ 2006044695500. Starting simulation...
+info: Entering event queue @ 2006044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 2006044727500. Starting simulation...
+info: Entering event queue @ 2006044704000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2007044727500. Starting simulation...
+info: Entering event queue @ 2007044704000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2008044727500. Starting simulation...
+info: Entering event queue @ 2008044704000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2009044727500. Starting simulation...
-info: Entering event queue @ 2016044720500. Starting simulation...
-info: Entering event queue @ 2016044727000. Starting simulation...
+info: Entering event queue @ 2009044704000. Starting simulation...
+info: Entering event queue @ 2016044695500. Starting simulation...
+info: Entering event queue @ 2016044702000. Starting simulation...
switching cpus
-info: Entering event queue @ 2016044727500. Starting simulation...
+info: Entering event queue @ 2016044702500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2017044727500. Starting simulation...
+info: Entering event queue @ 2017044702500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2018044727500. Starting simulation...
+info: Entering event queue @ 2018044702500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2019044727500. Starting simulation...
-info: Entering event queue @ 2026044720500. Starting simulation...
-info: Entering event queue @ 2026044727000. Starting simulation...
+info: Entering event queue @ 2019044702500. Starting simulation...
+info: Entering event queue @ 2026044694500. Starting simulation...
+info: Entering event queue @ 2026044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 2026044727500. Starting simulation...
+info: Entering event queue @ 2026044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2027044727500. Starting simulation...
+info: Entering event queue @ 2027044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2028044727500. Starting simulation...
+info: Entering event queue @ 2028044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2029044727500. Starting simulation...
-info: Entering event queue @ 2036044720500. Starting simulation...
-info: Entering event queue @ 2036044727000. Starting simulation...
+info: Entering event queue @ 2029044701500. Starting simulation...
+info: Entering event queue @ 2036044694500. Starting simulation...
+info: Entering event queue @ 2036044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2036044727500. Starting simulation...
+info: Entering event queue @ 2036044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2037044727500. Starting simulation...
+info: Entering event queue @ 2037044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2038044727500. Starting simulation...
+info: Entering event queue @ 2038044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2039044727500. Starting simulation...
-info: Entering event queue @ 2046044720500. Starting simulation...
-info: Entering event queue @ 2046044727000. Starting simulation...
+info: Entering event queue @ 2039044706000. Starting simulation...
+info: Entering event queue @ 2046044694500. Starting simulation...
+info: Entering event queue @ 2046044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2046044727500. Starting simulation...
+info: Entering event queue @ 2046044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2047044727500. Starting simulation...
+info: Entering event queue @ 2047044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2048044727500. Starting simulation...
+info: Entering event queue @ 2048044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2049044727500. Starting simulation...
-info: Entering event queue @ 2056044720500. Starting simulation...
-info: Entering event queue @ 2056044727000. Starting simulation...
+info: Entering event queue @ 2049044706000. Starting simulation...
+info: Entering event queue @ 2056044695500. Starting simulation...
+info: Entering event queue @ 2056044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 2056044727500. Starting simulation...
+info: Entering event queue @ 2056044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2057044727500. Starting simulation...
+info: Entering event queue @ 2057044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2058044727500. Starting simulation...
+info: Entering event queue @ 2058044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2059044727500. Starting simulation...
-info: Entering event queue @ 2066044720500. Starting simulation...
-info: Entering event queue @ 2067342280000. Starting simulation...
+info: Entering event queue @ 2059044708000. Starting simulation...
+info: Entering event queue @ 2066044695500. Starting simulation...
+info: Entering event queue @ 2067405755000. Starting simulation...
switching cpus
-info: Entering event queue @ 2067342282000. Starting simulation...
+info: Entering event queue @ 2067405757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2068342282000. Starting simulation...
+info: Entering event queue @ 2068405757000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2069342282000. Starting simulation...
+info: Entering event queue @ 2069405757000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2070342282000. Starting simulation...
-info: Entering event queue @ 2076044720500. Starting simulation...
-info: Entering event queue @ 2076044727000. Starting simulation...
+info: Entering event queue @ 2070405757000. Starting simulation...
+info: Entering event queue @ 2076044694500. Starting simulation...
+info: Entering event queue @ 2076044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 2076044727500. Starting simulation...
+info: Entering event queue @ 2076044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2077044727500. Starting simulation...
+info: Entering event queue @ 2077044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2078044727500. Starting simulation...
+info: Entering event queue @ 2078044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2079044727500. Starting simulation...
-info: Entering event queue @ 2086044720500. Starting simulation...
-info: Entering event queue @ 2086044727000. Starting simulation...
+info: Entering event queue @ 2079044701500. Starting simulation...
+info: Entering event queue @ 2086044694500. Starting simulation...
+info: Entering event queue @ 2086044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2086044727500. Starting simulation...
+info: Entering event queue @ 2086044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2087044727500. Starting simulation...
+info: Entering event queue @ 2087044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2088044727500. Starting simulation...
+info: Entering event queue @ 2088044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2089044727500. Starting simulation...
-info: Entering event queue @ 2096044720500. Starting simulation...
-info: Entering event queue @ 2096044727000. Starting simulation...
+info: Entering event queue @ 2089044706000. Starting simulation...
+info: Entering event queue @ 2096044695500. Starting simulation...
+info: Entering event queue @ 2096044702500. Starting simulation...
switching cpus
-info: Entering event queue @ 2096044727500. Starting simulation...
+info: Entering event queue @ 2096044707000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2097044727500. Starting simulation...
+info: Entering event queue @ 2097044707000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2098044727500. Starting simulation...
+info: Entering event queue @ 2098044707000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2099044727500. Starting simulation...
-info: Entering event queue @ 2106044720500. Starting simulation...
-info: Entering event queue @ 2106044727000. Starting simulation...
+info: Entering event queue @ 2099044707000. Starting simulation...
+info: Entering event queue @ 2106044694500. Starting simulation...
+info: Entering event queue @ 2106044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2106044727500. Starting simulation...
+info: Entering event queue @ 2106044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2107044727500. Starting simulation...
+info: Entering event queue @ 2107044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2108044727500. Starting simulation...
+info: Entering event queue @ 2108044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2109044727500. Starting simulation...
-info: Entering event queue @ 2116044720500. Starting simulation...
-info: Entering event queue @ 2116044727000. Starting simulation...
+info: Entering event queue @ 2109044706000. Starting simulation...
+info: Entering event queue @ 2116044694500. Starting simulation...
+info: Entering event queue @ 2116044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2116044727500. Starting simulation...
+info: Entering event queue @ 2116044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2117044727500. Starting simulation...
+info: Entering event queue @ 2117044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2118044727500. Starting simulation...
+info: Entering event queue @ 2118044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2119044727500. Starting simulation...
-info: Entering event queue @ 2126044720500. Starting simulation...
-info: Entering event queue @ 2126044727000. Starting simulation...
+info: Entering event queue @ 2119044706000. Starting simulation...
+info: Entering event queue @ 2126044695500. Starting simulation...
+info: Entering event queue @ 2126044704000. Starting simulation...
switching cpus
-info: Entering event queue @ 2126044727500. Starting simulation...
+info: Entering event queue @ 2126044708500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2127044727500. Starting simulation...
+info: Entering event queue @ 2127044708500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2128044727500. Starting simulation...
+info: Entering event queue @ 2128044708500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2129044727500. Starting simulation...
-info: Entering event queue @ 2136044720500. Starting simulation...
-info: Entering event queue @ 2136044727000. Starting simulation...
+info: Entering event queue @ 2129044708500. Starting simulation...
switching cpus
-info: Entering event queue @ 2136044727500. Starting simulation...
+info: Entering event queue @ 2136044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2137044727500. Starting simulation...
+info: Entering event queue @ 2137044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2138044727500. Starting simulation...
+info: Entering event queue @ 2138044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2139044727500. Starting simulation...
-info: Entering event queue @ 2146044720500. Starting simulation...
-info: Entering event queue @ 2146044727000. Starting simulation...
+info: Entering event queue @ 2139044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 2146044727500. Starting simulation...
+info: Entering event queue @ 2146044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2147044727500. Starting simulation...
+info: Entering event queue @ 2147044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2148044727500. Starting simulation...
+info: Entering event queue @ 2148044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2149044727500. Starting simulation...
-info: Entering event queue @ 2156044720500. Starting simulation...
-info: Entering event queue @ 2156044727000. Starting simulation...
+info: Entering event queue @ 2149044695500. Starting simulation...
switching cpus
-info: Entering event queue @ 2156044727500. Starting simulation...
+info: Entering event queue @ 2156044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2157044727500. Starting simulation...
+info: Entering event queue @ 2157044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2158044727500. Starting simulation...
+info: Entering event queue @ 2158044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2159044727500. Starting simulation...
-info: Entering event queue @ 2166044720500. Starting simulation...
-info: Entering event queue @ 2166044727000. Starting simulation...
+info: Entering event queue @ 2159044695500. Starting simulation...
+info: Entering event queue @ 2166044694500. Starting simulation...
+info: Entering event queue @ 2166044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2166044727500. Starting simulation...
+info: Entering event queue @ 2166044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2167044727500. Starting simulation...
+info: Entering event queue @ 2167044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2168044727500. Starting simulation...
+info: Entering event queue @ 2168044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2169044727500. Starting simulation...
-info: Entering event queue @ 2176044720500. Starting simulation...
-info: Entering event queue @ 2176044727000. Starting simulation...
+info: Entering event queue @ 2169044706000. Starting simulation...
+info: Entering event queue @ 2176044694500. Starting simulation...
+info: Entering event queue @ 2176044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2176044727500. Starting simulation...
+info: Entering event queue @ 2176044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2177044727500. Starting simulation...
+info: Entering event queue @ 2177044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2178044727500. Starting simulation...
+info: Entering event queue @ 2178044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2179044727500. Starting simulation...
-info: Entering event queue @ 2186044720500. Starting simulation...
-info: Entering event queue @ 2186044727000. Starting simulation...
+info: Entering event queue @ 2179044706000. Starting simulation...
+info: Entering event queue @ 2186044694500. Starting simulation...
+info: Entering event queue @ 2186044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 2186044727500. Starting simulation...
+info: Entering event queue @ 2186044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2187044727500. Starting simulation...
+info: Entering event queue @ 2187044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2188044727500. Starting simulation...
+info: Entering event queue @ 2188044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2189044727500. Starting simulation...
-info: Entering event queue @ 2196044720500. Starting simulation...
-info: Entering event queue @ 2196044727000. Starting simulation...
+info: Entering event queue @ 2189044701500. Starting simulation...
+info: Entering event queue @ 2196044694500. Starting simulation...
+info: Entering event queue @ 2196044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2196044727500. Starting simulation...
+info: Entering event queue @ 2196044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2197044727500. Starting simulation...
+info: Entering event queue @ 2197044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2198044727500. Starting simulation...
+info: Entering event queue @ 2198044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2199044727500. Starting simulation...
-info: Entering event queue @ 2206044720500. Starting simulation...
-info: Entering event queue @ 2206044727000. Starting simulation...
+info: Entering event queue @ 2199044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 2206044727500. Starting simulation...
+info: Entering event queue @ 2206044695500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2207044727500. Starting simulation...
+info: Entering event queue @ 2207044695500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2208044727500. Starting simulation...
+info: Entering event queue @ 2208044695500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2209044727500. Starting simulation...
-info: Entering event queue @ 2216044720500. Starting simulation...
-info: Entering event queue @ 2216044727000. Starting simulation...
+info: Entering event queue @ 2209044695500. Starting simulation...
+info: Entering event queue @ 2216044694500. Starting simulation...
+info: Entering event queue @ 2216044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2216044727500. Starting simulation...
+info: Entering event queue @ 2216044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2217044727500. Starting simulation...
+info: Entering event queue @ 2217044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2218044727500. Starting simulation...
+info: Entering event queue @ 2218044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2219044727500. Starting simulation...
-info: Entering event queue @ 2226044720500. Starting simulation...
-info: Entering event queue @ 2226044727000. Starting simulation...
+info: Entering event queue @ 2219044706000. Starting simulation...
+info: Entering event queue @ 2226044695500. Starting simulation...
+info: Entering event queue @ 2226044703500. Starting simulation...
switching cpus
-info: Entering event queue @ 2226044727500. Starting simulation...
+info: Entering event queue @ 2226044708000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2227044727500. Starting simulation...
+info: Entering event queue @ 2227044708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2228044727500. Starting simulation...
+info: Entering event queue @ 2228044708000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2229044727500. Starting simulation...
-info: Entering event queue @ 2236044720500. Starting simulation...
-info: Entering event queue @ 2236044727000. Starting simulation...
+info: Entering event queue @ 2229044708000. Starting simulation...
+info: Entering event queue @ 2236044694500. Starting simulation...
+info: Entering event queue @ 2236044701000. Starting simulation...
switching cpus
-info: Entering event queue @ 2236044727500. Starting simulation...
+info: Entering event queue @ 2236044701500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2237044727500. Starting simulation...
+info: Entering event queue @ 2237044701500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2238044727500. Starting simulation...
+info: Entering event queue @ 2238044701500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2239044727500. Starting simulation...
-info: Entering event queue @ 2246044720500. Starting simulation...
-info: Entering event queue @ 2246044727000. Starting simulation...
+info: Entering event queue @ 2239044701500. Starting simulation...
+info: Entering event queue @ 2246044694500. Starting simulation...
+info: Entering event queue @ 2246044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2246044727500. Starting simulation...
+info: Entering event queue @ 2246044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2247044727500. Starting simulation...
+info: Entering event queue @ 2247044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2248044727500. Starting simulation...
+info: Entering event queue @ 2248044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2249044727500. Starting simulation...
-info: Entering event queue @ 2256044720500. Starting simulation...
-info: Entering event queue @ 2256044727000. Starting simulation...
+info: Entering event queue @ 2249044706000. Starting simulation...
+info: Entering event queue @ 2256044694500. Starting simulation...
+info: Entering event queue @ 2256044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2256044727500. Starting simulation...
+info: Entering event queue @ 2256044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2257044727500. Starting simulation...
+info: Entering event queue @ 2257044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2258044727500. Starting simulation...
+info: Entering event queue @ 2258044706000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2259044727500. Starting simulation...
-info: Entering event queue @ 2266044720500. Starting simulation...
-info: Entering event queue @ 2266044727000. Starting simulation...
+info: Entering event queue @ 2259044706000. Starting simulation...
+info: Entering event queue @ 2266044694500. Starting simulation...
+info: Entering event queue @ 2266044701500. Starting simulation...
switching cpus
-info: Entering event queue @ 2266044727500. Starting simulation...
+info: Entering event queue @ 2266044706000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2267044727500. Starting simulation...
+info: Entering event queue @ 2267044706000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2268044727500. Starting simulation...
+info: Entering event queue @ 2268044706000. Starting simulation...
switching cpus
-info: Entering event queue @ 2268044728500. Starting simulation...
+info: Entering event queue @ 2268044713500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2269044728500. Starting simulation...
+info: Entering event queue @ 2269044713500. Starting simulation...
switching cpus
-info: Entering event queue @ 2269044739000. Starting simulation...
+info: Entering event queue @ 2269044786000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2270044739000. Starting simulation...
+info: Entering event queue @ 2270044786000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2271044739000. Starting simulation...
+info: Entering event queue @ 2271044786000. Starting simulation...
switching cpus
-info: Entering event queue @ 2271044767000. Starting simulation...
+info: Entering event queue @ 2271044847000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2272044767000. Starting simulation...
+info: Entering event queue @ 2272044847000. Starting simulation...
switching cpus
-info: Entering event queue @ 2272044790000. Starting simulation...
+info: Entering event queue @ 2272044909000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2273044790000. Starting simulation...
+info: Entering event queue @ 2273044909000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2274044790000. Starting simulation...
+info: Entering event queue @ 2274044909000. Starting simulation...
switching cpus
-info: Entering event queue @ 2274044828000. Starting simulation...
+info: Entering event queue @ 2274045051000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2275044828000. Starting simulation...
+info: Entering event queue @ 2275045051000. Starting simulation...
switching cpus
-info: Entering event queue @ 2275044925000. Starting simulation...
+info: Entering event queue @ 2275045114000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2276045114000. Starting simulation...
switching cpus
-info: Entering event queue @ 2276044925000. Starting simulation...
+info: Entering event queue @ 2276045117500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2277044925000. Starting simulation...
+info: Entering event queue @ 2277045117500. Starting simulation...
switching cpus
-info: Entering event queue @ 2277045053000. Starting simulation...
+info: Entering event queue @ 2277045208000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2278045053000. Starting simulation...
+info: Entering event queue @ 2278045208000. Starting simulation...
switching cpus
-info: Entering event queue @ 2278045122000. Starting simulation...
+info: Entering event queue @ 2278045280000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2279045122000. Starting simulation...
+info: Entering event queue @ 2279045280000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2280045122000. Starting simulation...
+info: Entering event queue @ 2280045280000. Starting simulation...
switching cpus
-info: Entering event queue @ 2280045138000. Starting simulation...
+info: Entering event queue @ 2280045384000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2281045138000. Starting simulation...
+info: Entering event queue @ 2281045384000. Starting simulation...
switching cpus
-info: Entering event queue @ 2281045900000. Starting simulation...
+info: Entering event queue @ 2281048528000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2282045900000. Starting simulation...
+info: Entering event queue @ 2282048528000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2283045900000. Starting simulation...
+info: Entering event queue @ 2283048528000. Starting simulation...
switching cpus
-info: Entering event queue @ 2283045901000. Starting simulation...
+info: Entering event queue @ 2283048535500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2284045901000. Starting simulation...
+info: Entering event queue @ 2284048535500. Starting simulation...
switching cpus
-info: Entering event queue @ 2284045960000. Starting simulation...
+info: Entering event queue @ 2284048596000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2285045960000. Starting simulation...
+info: Entering event queue @ 2285048596000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2286045960000. Starting simulation...
+info: Entering event queue @ 2286048596000. Starting simulation...
switching cpus
-info: Entering event queue @ 2286045982000. Starting simulation...
+info: Entering event queue @ 2286048638000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2287045982000. Starting simulation...
+info: Entering event queue @ 2287048638000. Starting simulation...
switching cpus
-info: Entering event queue @ 2287045989000. Starting simulation...
+info: Entering event queue @ 2287048678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2288045989000. Starting simulation...
+info: Entering event queue @ 2288048678500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2289045989000. Starting simulation...
+info: Entering event queue @ 2289048678500. Starting simulation...
switching cpus
-info: Entering event queue @ 2289046000000. Starting simulation...
+info: Entering event queue @ 2289048766000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2290046000000. Starting simulation...
+info: Entering event queue @ 2290048766000. Starting simulation...
switching cpus
-info: Entering event queue @ 2290046070000. Starting simulation...
+info: Entering event queue @ 2290048836000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2291046070000. Starting simulation...
+info: Entering event queue @ 2291048836000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2292046070000. Starting simulation...
+info: Entering event queue @ 2292048836000. Starting simulation...
switching cpus
-info: Entering event queue @ 2292046106000. Starting simulation...
+info: Entering event queue @ 2292048927000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2293046106000. Starting simulation...
+info: Entering event queue @ 2293048927000. Starting simulation...
switching cpus
-info: Entering event queue @ 2293046137000. Starting simulation...
+info: Entering event queue @ 2293049027000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2294046137000. Starting simulation...
+info: Entering event queue @ 2294049027000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2295046137000. Starting simulation...
-info: Entering event queue @ 2296496182000. Starting simulation...
+info: Entering event queue @ 2295049027000. Starting simulation...
+info: Entering event queue @ 2296559734000. Starting simulation...
switching cpus
-info: Entering event queue @ 2296496184000. Starting simulation...
+info: Entering event queue @ 2296559736000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2297496184000. Starting simulation...
+info: Entering event queue @ 2297559736000. Starting simulation...
switching cpus
-info: Entering event queue @ 2297496268000. Starting simulation...
+info: Entering event queue @ 2297559885000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2298496268000. Starting simulation...
+info: Entering event queue @ 2298559885000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2299496268000. Starting simulation...
+info: Entering event queue @ 2299559885000. Starting simulation...
switching cpus
-info: Entering event queue @ 2299496348000. Starting simulation...
+info: Entering event queue @ 2299559978000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2300496348000. Starting simulation...
+info: Entering event queue @ 2300559978000. Starting simulation...
switching cpus
-info: Entering event queue @ 2300496430000. Starting simulation...
+info: Entering event queue @ 2300560079000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2301496430000. Starting simulation...
+info: Entering event queue @ 2301560079000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2302496430000. Starting simulation...
+info: Entering event queue @ 2302560079000. Starting simulation...
switching cpus
-info: Entering event queue @ 2302496531000. Starting simulation...
+info: Entering event queue @ 2302560132000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2303496531000. Starting simulation...
+info: Entering event queue @ 2303560132000. Starting simulation...
switching cpus
-info: Entering event queue @ 2303496584000. Starting simulation...
+info: Entering event queue @ 2303560241000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2304496584000. Starting simulation...
+info: Entering event queue @ 2304560241000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2305496584000. Starting simulation...
+info: Entering event queue @ 2305560241000. Starting simulation...
switching cpus
-info: Entering event queue @ 2305496661000. Starting simulation...
+info: Entering event queue @ 2305560280000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2306496661000. Starting simulation...
+info: Entering event queue @ 2306560280000. Starting simulation...
switching cpus
-info: Entering event queue @ 2306496732000. Starting simulation...
+info: Entering event queue @ 2306560431000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2307496732000. Starting simulation...
+info: Entering event queue @ 2307560431000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2308496732000. Starting simulation...
+info: Entering event queue @ 2308560431000. Starting simulation...
switching cpus
-info: Entering event queue @ 2308496815000. Starting simulation...
+info: Entering event queue @ 2308560560000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2309496815000. Starting simulation...
+info: Entering event queue @ 2309560560000. Starting simulation...
switching cpus
-info: Entering event queue @ 2309496944500. Starting simulation...
+info: Entering event queue @ 2309560642000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2310496944500. Starting simulation...
+info: Entering event queue @ 2310560642000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2311496944500. Starting simulation...
+info: Entering event queue @ 2311560642000. Starting simulation...
switching cpus
-info: Entering event queue @ 2311496968000. Starting simulation...
+info: Entering event queue @ 2311560786000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2312496968000. Starting simulation...
+info: Entering event queue @ 2312560786000. Starting simulation...
switching cpus
-info: Entering event queue @ 2312497014000. Starting simulation...
+info: Entering event queue @ 2312560905000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2313497014000. Starting simulation...
+info: Entering event queue @ 2313560905000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2314497014000. Starting simulation...
+info: Entering event queue @ 2314560905000. Starting simulation...
switching cpus
-info: Entering event queue @ 2314497034000. Starting simulation...
+info: Entering event queue @ 2314561028000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2315497034000. Starting simulation...
+info: Entering event queue @ 2315561028000. Starting simulation...
switching cpus
-info: Entering event queue @ 2315497085000. Starting simulation...
+info: Entering event queue @ 2315561054000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2316497085000. Starting simulation...
+info: Entering event queue @ 2316561054000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2317497085000. Starting simulation...
+info: Entering event queue @ 2317561054000. Starting simulation...
switching cpus
-info: Entering event queue @ 2317497141000. Starting simulation...
+info: Entering event queue @ 2317561176000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2318497141000. Starting simulation...
+info: Entering event queue @ 2318561176000. Starting simulation...
switching cpus
-info: Entering event queue @ 2318497292000. Starting simulation...
+info: Entering event queue @ 2318561200000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2319497292000. Starting simulation...
+info: Entering event queue @ 2319561200000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2320497292000. Starting simulation...
+info: Entering event queue @ 2320561200000. Starting simulation...
switching cpus
-info: Entering event queue @ 2320497349000. Starting simulation...
+info: Entering event queue @ 2320561287000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2321497349000. Starting simulation...
+info: Entering event queue @ 2321561287000. Starting simulation...
switching cpus
-info: Entering event queue @ 2321497426000. Starting simulation...
+info: Entering event queue @ 2321561319000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2322497426000. Starting simulation...
+info: Entering event queue @ 2322561319000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2323497426000. Starting simulation...
+info: Entering event queue @ 2323561319000. Starting simulation...
switching cpus
-info: Entering event queue @ 2323497512000. Starting simulation...
+info: Entering event queue @ 2323561362000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2324497512000. Starting simulation...
+info: Entering event queue @ 2324561362000. Starting simulation...
switching cpus
-info: Entering event queue @ 2324497588000. Starting simulation...
+info: Entering event queue @ 2324561408000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2325497588000. Starting simulation...
+info: Entering event queue @ 2325561408000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2326497588000. Starting simulation...
+info: Entering event queue @ 2326561408000. Starting simulation...
switching cpus
-info: Entering event queue @ 2326497667000. Starting simulation...
+info: Entering event queue @ 2326561540000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2327497667000. Starting simulation...
+info: Entering event queue @ 2327561540000. Starting simulation...
switching cpus
-info: Entering event queue @ 2327497830500. Starting simulation...
+info: Entering event queue @ 2327561579000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2328497830500. Starting simulation...
+info: Entering event queue @ 2328561579000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2329497830500. Starting simulation...
+info: Entering event queue @ 2329561579000. Starting simulation...
switching cpus
-info: Entering event queue @ 2329497980000. Starting simulation...
+info: Entering event queue @ 2329561703000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2330497980000. Starting simulation...
+info: Entering event queue @ 2330561703000. Starting simulation...
switching cpus
-info: Entering event queue @ 2330498019000. Starting simulation...
+info: Entering event queue @ 2330561718000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2331498019000. Starting simulation...
+info: Entering event queue @ 2331561718000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2332498019000. Starting simulation...
+info: Entering event queue @ 2332561718000. Starting simulation...
switching cpus
-info: Entering event queue @ 2332498021000. Starting simulation...
+info: Entering event queue @ 2332561741000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2333498021000. Starting simulation...
+info: Entering event queue @ 2333561741000. Starting simulation...
switching cpus
-info: Entering event queue @ 2333498144000. Starting simulation...
+info: Entering event queue @ 2333561793000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2334498144000. Starting simulation...
+info: Entering event queue @ 2334561793000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2335498144000. Starting simulation...
+info: Entering event queue @ 2335561793000. Starting simulation...
switching cpus
-info: Entering event queue @ 2335498177000. Starting simulation...
+info: Entering event queue @ 2335561883000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2336498177000. Starting simulation...
+info: Entering event queue @ 2336561883000. Starting simulation...
switching cpus
-info: Entering event queue @ 2336498207000. Starting simulation...
+info: Entering event queue @ 2336561949000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2337498207000. Starting simulation...
+info: Entering event queue @ 2337561949000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2338498207000. Starting simulation...
+info: Entering event queue @ 2338561949000. Starting simulation...
switching cpus
-info: Entering event queue @ 2338498322500. Starting simulation...
+info: Entering event queue @ 2338562083000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2339498322500. Starting simulation...
+info: Entering event queue @ 2339562083000. Starting simulation...
switching cpus
-info: Entering event queue @ 2339498342500. Starting simulation...
+info: Entering event queue @ 2339562223000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2340498342500. Starting simulation...
+info: Entering event queue @ 2340562223000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2341498342500. Starting simulation...
+info: Entering event queue @ 2341562223000. Starting simulation...
switching cpus
-info: Entering event queue @ 2341498465000. Starting simulation...
+info: Entering event queue @ 2341562231000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2342498465000. Starting simulation...
+info: Entering event queue @ 2342562231000. Starting simulation...
switching cpus
-info: Entering event queue @ 2342498545000. Starting simulation...
+info: Entering event queue @ 2342562288000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2343498545000. Starting simulation...
+info: Entering event queue @ 2343562288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2344498545000. Starting simulation...
+info: Entering event queue @ 2344562288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2344498670000. Starting simulation...
+info: Entering event queue @ 2344562311000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2345498670000. Starting simulation...
+info: Entering event queue @ 2345562311000. Starting simulation...
switching cpus
-info: Entering event queue @ 2345498729000. Starting simulation...
+info: Entering event queue @ 2345562459000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2346498729000. Starting simulation...
+info: Entering event queue @ 2346562459000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2347498729000. Starting simulation...
+info: Entering event queue @ 2347562459000. Starting simulation...
switching cpus
-info: Entering event queue @ 2347498836000. Starting simulation...
+info: Entering event queue @ 2347562517000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2348498836000. Starting simulation...
+info: Entering event queue @ 2348562517000. Starting simulation...
switching cpus
-info: Entering event queue @ 2348498903500. Starting simulation...
+info: Entering event queue @ 2348562659000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2349498903500. Starting simulation...
+info: Entering event queue @ 2349562659000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2350498903500. Starting simulation...
+info: Entering event queue @ 2350562659000. Starting simulation...
switching cpus
-info: Entering event queue @ 2350499004000. Starting simulation...
+info: Entering event queue @ 2350562734000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2351499004000. Starting simulation...
+info: Entering event queue @ 2351562734000. Starting simulation...
switching cpus
-info: Entering event queue @ 2351499092000. Starting simulation...
+info: Entering event queue @ 2351562890000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2352499092000. Starting simulation...
+info: Entering event queue @ 2352562890000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2353499092000. Starting simulation...
+info: Entering event queue @ 2353562890000. Starting simulation...
switching cpus
-info: Entering event queue @ 2353499228000. Starting simulation...
+info: Entering event queue @ 2353562986000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2354499228000. Starting simulation...
+info: Entering event queue @ 2354562986000. Starting simulation...
switching cpus
-info: Entering event queue @ 2354499241000. Starting simulation...
+info: Entering event queue @ 2354563105000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2355499241000. Starting simulation...
+info: Entering event queue @ 2355563105000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2356499241000. Starting simulation...
+info: Entering event queue @ 2356563105000. Starting simulation...
switching cpus
-info: Entering event queue @ 2356499328000. Starting simulation...
+info: Entering event queue @ 2356563162000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2357499328000. Starting simulation...
+info: Entering event queue @ 2357563162000. Starting simulation...
switching cpus
-info: Entering event queue @ 2357499348000. Starting simulation...
+info: Entering event queue @ 2357568596000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2358499348000. Starting simulation...
+info: Entering event queue @ 2358568596000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2359499348000. Starting simulation...
+info: Entering event queue @ 2359568596000. Starting simulation...
switching cpus
-info: Entering event queue @ 2359499378000. Starting simulation...
+info: Entering event queue @ 2359568661000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2360499378000. Starting simulation...
-info: Entering event queue @ 2361968926000. Starting simulation...
+info: Entering event queue @ 2360568661000. Starting simulation...
+info: Entering event queue @ 2362032934000. Starting simulation...
switching cpus
-info: Entering event queue @ 2361968928000. Starting simulation...
+info: Entering event queue @ 2362032936000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2362968928000. Starting simulation...
+info: Entering event queue @ 2363032936000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2363968928000. Starting simulation...
+info: Entering event queue @ 2364032936000. Starting simulation...
switching cpus
-info: Entering event queue @ 2363969050000. Starting simulation...
+info: Entering event queue @ 2364033051000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2364969050000. Starting simulation...
+info: Entering event queue @ 2365033051000. Starting simulation...
switching cpus
-info: Entering event queue @ 2364969072000. Starting simulation...
+info: Entering event queue @ 2365033171000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2365969072000. Starting simulation...
+info: Entering event queue @ 2366033171000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2366969072000. Starting simulation...
+info: Entering event queue @ 2367033171000. Starting simulation...
switching cpus
-info: Entering event queue @ 2366969074000. Starting simulation...
+info: Entering event queue @ 2367033178500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2367969074000. Starting simulation...
+info: Entering event queue @ 2368033178500. Starting simulation...
switching cpus
-info: Entering event queue @ 2367969092500. Starting simulation...
+info: Entering event queue @ 2368033187500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2368969092500. Starting simulation...
+info: Entering event queue @ 2369033187500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2369969092500. Starting simulation...
+info: Entering event queue @ 2370033187500. Starting simulation...
switching cpus
-info: Entering event queue @ 2369969184000. Starting simulation...
+info: Entering event queue @ 2370033205000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2370969184000. Starting simulation...
+info: Entering event queue @ 2371033205000. Starting simulation...
switching cpus
-info: Entering event queue @ 2370969281000. Starting simulation...
+info: Entering event queue @ 2371033365500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2371969281000. Starting simulation...
+info: Entering event queue @ 2372033365500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2372969281000. Starting simulation...
+info: Entering event queue @ 2373033365500. Starting simulation...
+info: Entering event queue @ 2373033604000. Starting simulation...
switching cpus
-info: Entering event queue @ 2372969283000. Starting simulation...
+info: Entering event queue @ 2373033611500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2373969283000. Starting simulation...
+info: Entering event queue @ 2374033611500. Starting simulation...
switching cpus
-info: Entering event queue @ 2373969828500. Starting simulation...
+info: Entering event queue @ 2374033619000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2374969828500. Starting simulation...
+info: Entering event queue @ 2375033619000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2375969828500. Starting simulation...
+info: Entering event queue @ 2376033619000. Starting simulation...
switching cpus
-info: Entering event queue @ 2375969851000. Starting simulation...
+info: Entering event queue @ 2376033645000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2376969851000. Starting simulation...
+info: Entering event queue @ 2377033645000. Starting simulation...
switching cpus
-info: Entering event queue @ 2376969901000. Starting simulation...
+info: Entering event queue @ 2377043485500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2377969901000. Starting simulation...
+info: Entering event queue @ 2378043485500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2378969901000. Starting simulation...
+info: Entering event queue @ 2379043485500. Starting simulation...
switching cpus
-info: Entering event queue @ 2378969954000. Starting simulation...
+info: Entering event queue @ 2379043518000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2379969954000. Starting simulation...
+info: Entering event queue @ 2380043518000. Starting simulation...
switching cpus
-info: Entering event queue @ 2379970086500. Starting simulation...
+info: Entering event queue @ 2380043682500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2380970086500. Starting simulation...
+info: Entering event queue @ 2381043682500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2381970086500. Starting simulation...
+info: Entering event queue @ 2382043682500. Starting simulation...
switching cpus
-info: Entering event queue @ 2381970242000. Starting simulation...
+info: Entering event queue @ 2382043698000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2382970242000. Starting simulation...
+info: Entering event queue @ 2383043698000. Starting simulation...
switching cpus
-info: Entering event queue @ 2382978620000. Starting simulation...
+info: Entering event queue @ 2383051750000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2383978620000. Starting simulation...
+info: Entering event queue @ 2384051750000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2384978620000. Starting simulation...
+info: Entering event queue @ 2385051750000. Starting simulation...
switching cpus
-info: Entering event queue @ 2384978773000. Starting simulation...
+info: Entering event queue @ 2385051891000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2385978773000. Starting simulation...
+info: Entering event queue @ 2386051891000. Starting simulation...
+info: Entering event queue @ 2386051935000. Starting simulation...
switching cpus
-info: Entering event queue @ 2385978776000. Starting simulation...
+info: Entering event queue @ 2386052242750. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2386978776000. Starting simulation...
+info: Entering event queue @ 2387052242750. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2387978776000. Starting simulation...
+info: Entering event queue @ 2388052242750. Starting simulation...
switching cpus
-info: Entering event queue @ 2387978777500. Starting simulation...
+info: Entering event queue @ 2388052250250. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2388978777500. Starting simulation...
+info: Entering event queue @ 2389052250250. Starting simulation...
switching cpus
-info: Entering event queue @ 2388978785000. Starting simulation...
+info: Entering event queue @ 2389052257750. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2389978785000. Starting simulation...
+info: Entering event queue @ 2390052257750. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2390978785000. Starting simulation...
+info: Entering event queue @ 2391052257750. Starting simulation...
switching cpus
-info: Entering event queue @ 2390978786000. Starting simulation...
+info: Entering event queue @ 2391052265250. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2391978786000. Starting simulation...
-info: Entering event queue @ 2391978831000. Starting simulation...
-info: Entering event queue @ 2391978840500. Starting simulation...
-info: Entering event queue @ 2391978845000. Starting simulation...
+info: Entering event queue @ 2392052265250. Starting simulation...
switching cpus
-info: Entering event queue @ 2391978846000. Starting simulation...
+info: Entering event queue @ 2392062139500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2393062139500. Starting simulation...
switching cpus
-info: Entering event queue @ 2392978846000. Starting simulation...
+info: Entering event queue @ 2393062140000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2393978846000. Starting simulation...
-info: Entering event queue @ 2394705526000. Starting simulation...
+info: Entering event queue @ 2394062140000. Starting simulation...
+info: Entering event queue @ 2394135530000. Starting simulation...
switching cpus
-info: Entering event queue @ 2394705528000. Starting simulation...
+info: Entering event queue @ 2394135532000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2395705528000. Starting simulation...
+info: Entering event queue @ 2395135532000. Starting simulation...
switching cpus
-info: Entering event queue @ 2395708224000. Starting simulation...
+info: Entering event queue @ 2395135538000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2396708224000. Starting simulation...
+info: Entering event queue @ 2396135538000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2397708224000. Starting simulation...
+info: Entering event queue @ 2397135538000. Starting simulation...
switching cpus
-info: Entering event queue @ 2397708236000. Starting simulation...
+info: Entering event queue @ 2397135545500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2398708236000. Starting simulation...
+info: Entering event queue @ 2398135545500. Starting simulation...
switching cpus
-info: Entering event queue @ 2398708269500. Starting simulation...
+info: Entering event queue @ 2398135611000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2399708269500. Starting simulation...
+info: Entering event queue @ 2399135611000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2400708269500. Starting simulation...
+info: Entering event queue @ 2400135611000. Starting simulation...
switching cpus
-info: Entering event queue @ 2400708271500. Starting simulation...
+info: Entering event queue @ 2400135618500. Starting simulation...
---------- Begin Simulation Statistics ----------
-sim_seconds 2.401336 # Number of seconds simulated
-sim_ticks 2401336466000 # Number of ticks simulated
-final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.400708 # Number of seconds simulated
+sim_ticks 2400708253000 # Number of ticks simulated
+final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184517 # Simulator instruction rate (inst/s)
-host_op_rate 236966 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7343776984 # Simulator tick rate (ticks/s)
-host_mem_usage 427572 # Number of bytes of host memory used
-host_seconds 326.99 # Real time elapsed on the host
-sim_insts 60334938 # Number of instructions simulated
-sim_ops 77485485 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 71724 # Simulator instruction rate (inst/s)
+host_op_rate 92116 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2854182500 # Simulator tick rate (ticks/s)
+host_mem_usage 441348 # Number of bytes of host memory used
+host_seconds 841.12 # Real time elapsed on the host
+sim_insts 60328852 # Number of instructions simulated
+sim_ops 77480507 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7113744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 84352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 676992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1286200 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124661288 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 84352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 764640 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3747008 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6762824 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 111186 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1318 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10578 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 20110 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58547 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812501 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47827166 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 209658 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2963186 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 281997 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 73712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 535759 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51926879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 209658 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35136 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 73712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 318506 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1560793 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 620722 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 83080 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 552417 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2817012 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1560793 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47827166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 209658 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3583907 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 12617991 # Total number of read requests seen
-system.physmem.writeReqs 398645 # Total number of write requests seen
-system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 807551424 # Total number of bytes read from memory
-system.physmem.bytesWritten 25513280 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.inst 35136 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 365077 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 73712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1088176 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54743891 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 12544378 # Total number of read requests seen
+system.physmem.writeReqs 398835 # Total number of write requests seen
+system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 802840192 # Total number of bytes read from memory
+system.physmem.bytesWritten 25525440 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 102301752 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2640780 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 2352 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 784491 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 784138 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 784232 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 784566 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 784404 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 784106 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 784266 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 784324 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 783997 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 783399 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 783436 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 783681 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 783642 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::14 783837 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 784365 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::5 24650 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 24877 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 25285 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 25156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 24816 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 24782 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 24769 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 24956 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 24888 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 24972 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2400301266000 # Total gap between requests
+system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2399673084000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 15 # Categorize read packet sizes
-system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
+system.physmem.readPktSize::2 14 # Categorize read packet sizes
+system.physmem.readPktSize::3 12509600 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 35064 # Categorize read packet sizes
+system.physmem.readPktSize::6 34764 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 381229 # Categorize write packet sizes
+system.physmem.writePktSize::2 381411 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 17416 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see
-system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests
-system.physmem.totBusLat 63089955000 # Total cycles spent in databus access
-system.physmem.totBankLat 12731042500 # Total cycles spent in bank access
-system.physmem.avgQLat 21968.79 # Average queueing delay per request
-system.physmem.avgBankLat 1008.96 # Average bank access latency per request
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+system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see
+system.physmem.totQLat 275491085000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 350869643750 # Sum of mem lat for all requests
+system.physmem.totBusLat 62721890000 # Total cycles spent in databus access
+system.physmem.totBankLat 12656668750 # Total cycles spent in bank access
+system.physmem.avgQLat 21961.32 # Average queueing delay per request
+system.physmem.avgBankLat 1008.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27977.75 # Average memory access latency
-system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 27970.27 # Average memory access latency
+system.physmem.avgRdBW 334.42 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 42.61 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.71 # Data bus utilization in percentage
+system.physmem.busUtil 2.70 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 0.39 # Average write queue length over time
-system.physmem.readRowHits 12563370 # Number of row buffer hits during reads
-system.physmem.writeRowHits 392291 # Number of row buffer hits during writes
+system.physmem.readRowHits 12490088 # Number of row buffer hits during reads
+system.physmem.writeRowHits 392491 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
-system.physmem.avgGap 184402.58 # Average gap between requests
-system.l2c.replacements 63266 # number of replacements
-system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use
-system.l2c.total_refs 1749187 # Total number of references to valid blocks.
-system.l2c.sampled_refs 128660 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.595422 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor
+system.physmem.avgGap 185400.11 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 597831 # number of writebacks
+system.cpu0.dcache.writebacks::total 597831 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146824 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 146824 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539280 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 539280 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 409 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 409 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 686104 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 686104 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 686104 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 686104 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64738 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138260 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 202998 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29583 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52504 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 82087 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1722 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3462 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5184 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 94321 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 190764 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 285085 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 94321 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 190764 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 285085 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773418500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795552000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568970500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 669013000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1403739991 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2072752991 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19099500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40608500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59708000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442431500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3199291991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 4641723491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442431500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3199291991 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4641723491 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592956500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28992541000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56585497500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276098000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147117763 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423215763 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28869054500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43139658763 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 72008713263 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033252 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029031 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014682 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021563 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019319 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008035 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048113 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045047 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020708 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011858 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011858 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11946.901356 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12986.778533 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.151775 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22614.778758 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26735.867572 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25250.685139 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.463415 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11729.780474 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11517.746914 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2185339 # DTB read hits
-system.cpu1.dtb.read_misses 2099 # DTB read misses
-system.cpu1.dtb.write_hits 1465312 # DTB write hits
-system.cpu1.dtb.write_misses 382 # DTB write misses
+system.cpu1.dtb.read_hits 2162379 # DTB read hits
+system.cpu1.dtb.read_misses 2097 # DTB read misses
+system.cpu1.dtb.write_hits 1458481 # DTB write hits
+system.cpu1.dtb.write_misses 389 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2187438 # DTB read accesses
-system.cpu1.dtb.write_accesses 1465694 # DTB write accesses
+system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 2164476 # DTB read accesses
+system.cpu1.dtb.write_accesses 1458870 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3650651 # DTB hits
-system.cpu1.dtb.misses 2481 # DTB misses
-system.cpu1.dtb.accesses 3653132 # DTB accesses
-system.cpu1.itb.inst_hits 8513719 # ITB inst hits
-system.cpu1.itb.inst_misses 1131 # ITB inst misses
+system.cpu1.dtb.hits 3620860 # DTB hits
+system.cpu1.dtb.misses 2486 # DTB misses
+system.cpu1.dtb.accesses 3623346 # DTB accesses
+system.cpu1.itb.inst_hits 8379462 # ITB inst hits
+system.cpu1.itb.inst_misses 1132 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses
-system.cpu1.itb.hits 8513719 # DTB hits
-system.cpu1.itb.misses 1131 # DTB misses
-system.cpu1.itb.accesses 8514850 # DTB accesses
-system.cpu1.numCycles 574637078 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8380594 # ITB inst accesses
+system.cpu1.itb.hits 8379462 # DTB hits
+system.cpu1.itb.misses 1132 # DTB misses
+system.cpu1.itb.accesses 8380594 # DTB accesses
+system.cpu1.numCycles 573333879 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 8294211 # Number of instructions committed
-system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses
-system.cpu1.num_func_calls 319530 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9421872 # number of integer instructions
-system.cpu1.num_fp_insts 2078 # number of float instructions
-system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3824850 # number of memory refs
-system.cpu1.num_load_insts 2281405 # Number of load instructions
-system.cpu1.num_store_insts 1543445 # Number of store instructions
-system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles
-system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles
+system.cpu1.committedInsts 8178203 # Number of instructions committed
+system.cpu1.committedOps 10418210 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9330752 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses
+system.cpu1.num_func_calls 315480 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1141385 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9330752 # number of integer instructions
+system.cpu1.num_fp_insts 1998 # number of float instructions
+system.cpu1.num_int_register_reads 53785556 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10103056 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
+system.cpu1.num_mem_refs 3793769 # number of memory refs
+system.cpu1.num_load_insts 2257716 # Number of load instructions
+system.cpu1.num_store_insts 1536053 # Number of store instructions
+system.cpu1.num_idle_cycles 537669981.200710 # Number of idle cycles
+system.cpu1.num_busy_cycles 35663897.799290 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.062204 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.937796 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 4687055 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits
+system.cpu2.branchPred.lookups 4726334 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3843092 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 222010 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 2958856 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2529751 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 85.497604 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 412073 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21648 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 10844149 # DTB read hits
-system.cpu2.dtb.read_misses 22603 # DTB read misses
-system.cpu2.dtb.write_hits 3263914 # DTB write hits
-system.cpu2.dtb.write_misses 5857 # DTB write misses
+system.cpu2.dtb.read_hits 10884010 # DTB read hits
+system.cpu2.dtb.read_misses 22849 # DTB read misses
+system.cpu2.dtb.write_hits 3265307 # DTB write hits
+system.cpu2.dtb.write_misses 5901 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 675 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 176 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 10866752 # DTB read accesses
-system.cpu2.dtb.write_accesses 3269771 # DTB write accesses
+system.cpu2.dtb.perms_faults 462 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 10906859 # DTB read accesses
+system.cpu2.dtb.write_accesses 3271208 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14108063 # DTB hits
-system.cpu2.dtb.misses 28460 # DTB misses
-system.cpu2.dtb.accesses 14136523 # DTB accesses
-system.cpu2.itb.inst_hits 4055013 # ITB inst hits
-system.cpu2.itb.inst_misses 4560 # ITB inst misses
+system.cpu2.dtb.hits 14149317 # DTB hits
+system.cpu2.dtb.misses 28750 # DTB misses
+system.cpu2.dtb.accesses 14178067 # DTB accesses
+system.cpu2.itb.inst_hits 4064296 # ITB inst hits
+system.cpu2.itb.inst_misses 4509 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 1562 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 968 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses
-system.cpu2.itb.hits 4055013 # DTB hits
-system.cpu2.itb.misses 4560 # DTB misses
-system.cpu2.itb.accesses 4059573 # DTB accesses
-system.cpu2.numCycles 88254759 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 4068805 # ITB inst accesses
+system.cpu2.itb.hits 4064296 # DTB hits
+system.cpu2.itb.misses 4509 # DTB misses
+system.cpu2.itb.accesses 4068805 # DTB accesses
+system.cpu2.numCycles 88279018 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9458864 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32433194 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4726334 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2941824 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6832879 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1816174 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 51286 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 19337351 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 2080 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 975 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 33815 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 56915 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 312 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 4063011 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 310021 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 1911 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 37021672 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.050656 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.436806 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 30193705 81.56% 81.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 383800 1.04% 82.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 509282 1.38% 83.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 813035 2.20% 86.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 655040 1.77% 87.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 344627 0.93% 88.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1013096 2.74% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 238978 0.65% 92.25% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2870109 7.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 37021672 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.053539 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.367394 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10074280 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19273281 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6183203 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 295071 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1194753 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 612486 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 53708 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36748038 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 181597 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1194753 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10649029 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 6564844 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11163009 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5883991 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1564995 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 34501786 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2424 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 422794 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 878812 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 93 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 37014698 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 157694934 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 157667196 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 27738 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 25798325 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11216372 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 231057 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 207527 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3357295 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6536002 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3838530 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 533894 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 787090 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 31736542 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 511835 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 34275347 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 54662 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7411950 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 19918044 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 155690 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 37021672 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.925818 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.580792 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24452597 66.05% 66.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3909614 10.56% 76.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2349010 6.34% 82.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 1972018 5.33% 88.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2798812 7.56% 95.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 886009 2.39% 98.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 484017 1.31% 99.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 134496 0.36% 99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 35099 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 37021672 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 18701 1.22% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.22% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1408658 91.63% 92.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 109949 7.15% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 61376 0.18% 0.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 19371931 56.52% 56.70% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11383572 33.21% 89.99% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3432179 10.01% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued
-system.cpu2.iq.rate 0.386887 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 34275347 # Type of FU issued
+system.cpu2.iq.rate 0.388262 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1537308 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.044852 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 107186070 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 39665615 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 27402348 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 6887 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3783 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3156 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 35747644 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3635 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 208180 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1582611 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1901 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9388 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 582353 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5366761 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 352360 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1194753 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 4874895 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 91791 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32329432 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 60600 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6536002 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3838530 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 369520 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 31433 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2533 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9388 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 105889 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 88624 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 194513 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 33284218 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11095059 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 991129 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 72670 # number of nop insts executed
-system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3670278 # Number of branches executed
-system.cpu2.iew.exec_stores 3398105 # Number of stores executed
-system.cpu2.iew.exec_rate 0.375646 # Inst execution rate
-system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 15591378 # num instructions producing a value
-system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value
+system.cpu2.iew.exec_nop 81055 # number of nop insts executed
+system.cpu2.iew.exec_refs 14494094 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3696710 # Number of branches executed
+system.cpu2.iew.exec_stores 3399035 # Number of stores executed
+system.cpu2.iew.exec_rate 0.377034 # Inst execution rate
+system.cpu2.iew.wb_sent 32864100 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 27405504 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 15677727 # num instructions producing a value
+system.cpu2.iew.wb_consumers 28502633 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.310442 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.550045 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 7348668 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 356145 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 169071 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35826783 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.689728 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.717733 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 27184585 75.88% 75.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4182145 11.67% 87.55% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1258559 3.51% 91.06% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 654760 1.83% 92.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 571167 1.59% 94.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 316320 0.88% 95.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 401210 1.12% 96.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 290625 0.81% 97.30% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 967412 2.70% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 19883492 # Number of instructions committed
-system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 35826783 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 20002486 # Number of instructions committed
+system.cpu2.commit.committedOps 24710742 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8174125 # Number of memory references committed
-system.cpu2.commit.loads 4916766 # Number of loads committed
-system.cpu2.commit.membars 94500 # Number of memory barriers committed
-system.cpu2.commit.branches 3146107 # Number of branches committed
-system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 293773 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 8209568 # Number of memory references committed
+system.cpu2.commit.loads 4953391 # Number of loads committed
+system.cpu2.commit.membars 94240 # Number of memory barriers committed
+system.cpu2.commit.branches 3168906 # Number of branches committed
+system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 21931175 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 294969 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 967412 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 66150526 # The number of ROB reads
-system.cpu2.rob.rob_writes 64978873 # The number of ROB writes
-system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 19835003 # Number of Instructions Simulated
-system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated
-system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads
-system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes
+system.cpu2.rob.rob_reads 66393860 # The number of ROB reads
+system.cpu2.rob.rob_writes 65354684 # The number of ROB writes
+system.cpu2.timesIdled 360581 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51257346 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3567291742 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 19948293 # Number of Instructions Simulated
+system.cpu2.committedOps 24656549 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 19948293 # Number of Instructions Simulated
+system.cpu2.cpi 4.425392 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.425392 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.225969 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.225969 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 153783407 # number of integer regfile reads
+system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 9021581 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 975317722127 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 975317722127 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 975317722127 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 975317722127 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=False
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 22:10:12
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:19:45
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
Next CPU: DerivO3CPU
info: Entering event queue @ 1000000000. Starting simulation...
switching cpus
-info: Entering event queue @ 1000004500. Starting simulation...
+info: Entering event queue @ 1000007500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2000004500. Starting simulation...
+info: Entering event queue @ 2000007500. Starting simulation...
switching cpus
-info: Entering event queue @ 2000028000. Starting simulation...
+info: Entering event queue @ 2000059000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 3000028000. Starting simulation...
+info: Entering event queue @ 3000059000. Starting simulation...
switching cpus
-info: Entering event queue @ 3000031000. Starting simulation...
+info: Entering event queue @ 3000062500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 4000031000. Starting simulation...
+info: Entering event queue @ 4000062500. Starting simulation...
switching cpus
-info: Entering event queue @ 4000247000. Starting simulation...
+info: Entering event queue @ 4000382000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 5000247000. Starting simulation...
+info: Entering event queue @ 5000382000. Starting simulation...
+info: Entering event queue @ 5000388500. Starting simulation...
switching cpus
-info: Entering event queue @ 5000410000. Starting simulation...
+info: Entering event queue @ 5000393500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 6000410000. Starting simulation...
-info: Entering event queue @ 6000457500. Starting simulation...
-info: Entering event queue @ 6000493000. Starting simulation...
+info: Entering event queue @ 6000393500. Starting simulation...
switching cpus
-info: Entering event queue @ 6000497500. Starting simulation...
+info: Entering event queue @ 6000471000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 7000497500. Starting simulation...
-info: Entering event queue @ 7000507000. Starting simulation...
+info: Entering event queue @ 7000471000. Starting simulation...
+info: Entering event queue @ 7000479500. Starting simulation...
switching cpus
-info: Entering event queue @ 7000511500. Starting simulation...
+info: Entering event queue @ 7000484000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 8000511500. Starting simulation...
+info: Entering event queue @ 8000484000. Starting simulation...
switching cpus
-info: Entering event queue @ 8000635000. Starting simulation...
+info: Entering event queue @ 8000798500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 9000635000. Starting simulation...
+info: Entering event queue @ 9000798500. Starting simulation...
+info: Entering event queue @ 9000819500. Starting simulation...
+info: Entering event queue @ 9000821500. Starting simulation...
switching cpus
-info: Entering event queue @ 9000641000. Starting simulation...
+info: Entering event queue @ 9000826000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 10000641000. Starting simulation...
+info: Entering event queue @ 10000826000. Starting simulation...
switching cpus
-info: Entering event queue @ 10000646500. Starting simulation...
+info: Entering event queue @ 10000828500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 11000646500. Starting simulation...
+info: Entering event queue @ 11000828500. Starting simulation...
switching cpus
-info: Entering event queue @ 11000922500. Starting simulation...
+info: Entering event queue @ 11000860500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 12000922500. Starting simulation...
-info: Entering event queue @ 12000932500. Starting simulation...
+info: Entering event queue @ 12000860500. Starting simulation...
switching cpus
-info: Entering event queue @ 12000937000. Starting simulation...
+info: Entering event queue @ 12000871500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 13000937000. Starting simulation...
-info: Entering event queue @ 13000946500. Starting simulation...
+info: Entering event queue @ 13000871500. Starting simulation...
switching cpus
-info: Entering event queue @ 13000951000. Starting simulation...
+info: Entering event queue @ 13000879000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 14000951000. Starting simulation...
+info: Entering event queue @ 14000879000. Starting simulation...
+info: Entering event queue @ 14000902000. Starting simulation...
+info: Entering event queue @ 14000911000. Starting simulation...
switching cpus
-info: Entering event queue @ 14000960000. Starting simulation...
+info: Entering event queue @ 14000916504. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 15000960000. Starting simulation...
-info: Entering event queue @ 15000966000. Starting simulation...
+info: Entering event queue @ 15000916504. Starting simulation...
+info: Entering event queue @ 15000925500. Starting simulation...
+info: Entering event queue @ 15000931500. Starting simulation...
switching cpus
-info: Entering event queue @ 15000970500. Starting simulation...
+info: Entering event queue @ 15000936000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 16000970500. Starting simulation...
+info: Entering event queue @ 16000936000. Starting simulation...
switching cpus
-info: Entering event queue @ 16001125000. Starting simulation...
+info: Entering event queue @ 16001197000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 17001125000. Starting simulation...
+info: Entering event queue @ 17001197000. Starting simulation...
switching cpus
-info: Entering event queue @ 25966288000. Starting simulation...
+info: Entering event queue @ 26026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 26966288000. Starting simulation...
+info: Entering event queue @ 27026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 35966288000. Starting simulation...
+info: Entering event queue @ 36026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 36966288000. Starting simulation...
+info: Entering event queue @ 37026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 45966288000. Starting simulation...
+info: Entering event queue @ 46026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 46966288000. Starting simulation...
-info: Entering event queue @ 48430354000. Starting simulation...
+info: Entering event queue @ 47026543000. Starting simulation...
+info: Entering event queue @ 48597551000. Starting simulation...
switching cpus
-info: Entering event queue @ 48430356000. Starting simulation...
+info: Entering event queue @ 48597553000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 49430356000. Starting simulation...
+info: Entering event queue @ 49597553000. Starting simulation...
switching cpus
-info: Entering event queue @ 49430481500. Starting simulation...
+info: Entering event queue @ 49597756250. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 50430481500. Starting simulation...
+info: Entering event queue @ 50597756250. Starting simulation...
switching cpus
-info: Entering event queue @ 50430618000. Starting simulation...
+info: Entering event queue @ 50597763750. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 51430618000. Starting simulation...
+info: Entering event queue @ 51597763750. Starting simulation...
switching cpus
-info: Entering event queue @ 51430627000. Starting simulation...
+info: Entering event queue @ 51597906750. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 52430627000. Starting simulation...
-info: Entering event queue @ 52430630500. Starting simulation...
+info: Entering event queue @ 52597906750. Starting simulation...
+info: Entering event queue @ 52597914250. Starting simulation...
+info: Entering event queue @ 52597920000. Starting simulation...
switching cpus
-info: Entering event queue @ 52430635000. Starting simulation...
+info: Entering event queue @ 52597924500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 53430635000. Starting simulation...
+info: Entering event queue @ 53597924500. Starting simulation...
+info: Entering event queue @ 53597946500. Starting simulation...
switching cpus
-info: Entering event queue @ 53430641000. Starting simulation...
+info: Entering event queue @ 53597952000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 54430641000. Starting simulation...
-info: Entering event queue @ 54430651500. Starting simulation...
+info: Entering event queue @ 54597952000. Starting simulation...
switching cpus
-info: Entering event queue @ 54430656000. Starting simulation...
+info: Entering event queue @ 54597974500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 55430656000. Starting simulation...
-info: Entering event queue @ 55430664500. Starting simulation...
+info: Entering event queue @ 55597974500. Starting simulation...
+info: Entering event queue @ 55597991000. Starting simulation...
+info: Entering event queue @ 55597997500. Starting simulation...
switching cpus
-info: Entering event queue @ 55430669000. Starting simulation...
+info: Entering event queue @ 55598002000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 56430669000. Starting simulation...
+info: Entering event queue @ 56598002000. Starting simulation...
switching cpus
-info: Entering event queue @ 56430965500. Starting simulation...
+info: Entering event queue @ 56598009500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 57430965500. Starting simulation...
+info: Entering event queue @ 57598009500. Starting simulation...
+info: Entering event queue @ 57598017000. Starting simulation...
+info: Entering event queue @ 57598021000. Starting simulation...
switching cpus
-info: Entering event queue @ 65966288000. Starting simulation...
+info: Entering event queue @ 57598025500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 66966288000. Starting simulation...
+info: Entering event queue @ 58598025500. Starting simulation...
switching cpus
-info: Entering event queue @ 75966288000. Starting simulation...
+info: Entering event queue @ 66026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 76966288000. Starting simulation...
+info: Entering event queue @ 67026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 85966288000. Starting simulation...
+info: Entering event queue @ 76026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 86966288000. Starting simulation...
+info: Entering event queue @ 77026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 95966288000. Starting simulation...
+info: Entering event queue @ 86026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 96966288000. Starting simulation...
+info: Entering event queue @ 87026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 105966288000. Starting simulation...
+info: Entering event queue @ 96026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 106966288000. Starting simulation...
+info: Entering event queue @ 97026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 115966288000. Starting simulation...
+info: Entering event queue @ 106026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 116966288000. Starting simulation...
+info: Entering event queue @ 107026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 125966288000. Starting simulation...
+info: Entering event queue @ 116026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 126966288000. Starting simulation...
+info: Entering event queue @ 117026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 135966288000. Starting simulation...
+info: Entering event queue @ 126026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 136966288000. Starting simulation...
+info: Entering event queue @ 127026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 145966288000. Starting simulation...
+info: Entering event queue @ 136026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 146966288000. Starting simulation...
+info: Entering event queue @ 137026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 155966288000. Starting simulation...
+info: Entering event queue @ 146026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 156966288000. Starting simulation...
+info: Entering event queue @ 147026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 165966288000. Starting simulation...
+info: Entering event queue @ 156026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 166966288000. Starting simulation...
+info: Entering event queue @ 157026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 175966288000. Starting simulation...
+info: Entering event queue @ 166026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 176966288000. Starting simulation...
+info: Entering event queue @ 167026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 185966288000. Starting simulation...
+info: Entering event queue @ 176026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 186966288000. Starting simulation...
+info: Entering event queue @ 177026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 195966288000. Starting simulation...
+info: Entering event queue @ 186026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 196966288000. Starting simulation...
+info: Entering event queue @ 187026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 205966288000. Starting simulation...
+info: Entering event queue @ 196026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 206966288000. Starting simulation...
-info: Entering event queue @ 206966298000. Starting simulation...
-info: Entering event queue @ 206966304500. Starting simulation...
+info: Entering event queue @ 197026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 206966309000. Starting simulation...
+info: Entering event queue @ 206026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 207966309000. Starting simulation...
+info: Entering event queue @ 207026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 215966288000. Starting simulation...
+info: Entering event queue @ 216026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 216966288000. Starting simulation...
+info: Entering event queue @ 217026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 225966288000. Starting simulation...
+info: Entering event queue @ 217026554500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 226966288000. Starting simulation...
+info: Entering event queue @ 218026554500. Starting simulation...
switching cpus
-info: Entering event queue @ 235966288000. Starting simulation...
+info: Entering event queue @ 226026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 236966288000. Starting simulation...
+info: Entering event queue @ 227026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 245966288000. Starting simulation...
+info: Entering event queue @ 236026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 246966288000. Starting simulation...
+info: Entering event queue @ 237026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 255966288000. Starting simulation...
+info: Entering event queue @ 246026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 256966288000. Starting simulation...
+info: Entering event queue @ 247026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 265966288000. Starting simulation...
+info: Entering event queue @ 256026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 266966288000. Starting simulation...
-info: Entering event queue @ 275966288000. Starting simulation...
-info: Entering event queue @ 276772747000. Starting simulation...
+info: Entering event queue @ 257026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 276772749000. Starting simulation...
+info: Entering event queue @ 266026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 277772749000. Starting simulation...
+info: Entering event queue @ 267026543000. Starting simulation...
+info: Entering event queue @ 276026543000. Starting simulation...
+info: Entering event queue @ 276896939000. Starting simulation...
switching cpus
-info: Entering event queue @ 285966288000. Starting simulation...
+info: Entering event queue @ 276896941000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 286966288000. Starting simulation...
+info: Entering event queue @ 277896941000. Starting simulation...
switching cpus
-info: Entering event queue @ 295966288000. Starting simulation...
+info: Entering event queue @ 286026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 296966288000. Starting simulation...
+info: Entering event queue @ 287026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 305966288000. Starting simulation...
+info: Entering event queue @ 296026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 306966288000. Starting simulation...
+info: Entering event queue @ 297026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 315966288000. Starting simulation...
+info: Entering event queue @ 306026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 316966288000. Starting simulation...
+info: Entering event queue @ 307026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 325966288000. Starting simulation...
+info: Entering event queue @ 316026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 326966288000. Starting simulation...
+info: Entering event queue @ 317026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 335966288000. Starting simulation...
+info: Entering event queue @ 326026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 336966288000. Starting simulation...
+info: Entering event queue @ 327026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 345966288000. Starting simulation...
+info: Entering event queue @ 336026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 346966288000. Starting simulation...
+info: Entering event queue @ 337026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 355966288000. Starting simulation...
+info: Entering event queue @ 346026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 356966288000. Starting simulation...
+info: Entering event queue @ 347026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 365966288000. Starting simulation...
+info: Entering event queue @ 356026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 366966288000. Starting simulation...
+info: Entering event queue @ 357026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 375966288000. Starting simulation...
+info: Entering event queue @ 366026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 376966288000. Starting simulation...
+info: Entering event queue @ 367026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 385966288000. Starting simulation...
+info: Entering event queue @ 376026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 386966288000. Starting simulation...
+info: Entering event queue @ 377026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 395966288000. Starting simulation...
+info: Entering event queue @ 386026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 396966288000. Starting simulation...
+info: Entering event queue @ 387026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 405966288000. Starting simulation...
+info: Entering event queue @ 396026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 406966288000. Starting simulation...
+info: Entering event queue @ 397026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 415966288000. Starting simulation...
+info: Entering event queue @ 406026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 416966288000. Starting simulation...
+info: Entering event queue @ 407026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 425966288000. Starting simulation...
+info: Entering event queue @ 416026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 426966288000. Starting simulation...
+info: Entering event queue @ 417026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 435966288000. Starting simulation...
+info: Entering event queue @ 426026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 436966288000. Starting simulation...
+info: Entering event queue @ 427026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 445966288000. Starting simulation...
+info: Entering event queue @ 436026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 446966288000. Starting simulation...
+info: Entering event queue @ 437026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 455966288000. Starting simulation...
+info: Entering event queue @ 446026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 456966288000. Starting simulation...
+info: Entering event queue @ 447026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 465966288000. Starting simulation...
+info: Entering event queue @ 456026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 466966288000. Starting simulation...
+info: Entering event queue @ 457026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 475966288000. Starting simulation...
+info: Entering event queue @ 466026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 476966288000. Starting simulation...
+info: Entering event queue @ 467026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 485966288000. Starting simulation...
+info: Entering event queue @ 476026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 486966288000. Starting simulation...
+info: Entering event queue @ 477026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 495966288000. Starting simulation...
+info: Entering event queue @ 486026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 496966288000. Starting simulation...
+info: Entering event queue @ 487026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 505966288000. Starting simulation...
+info: Entering event queue @ 496026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 506966288000. Starting simulation...
+info: Entering event queue @ 497026543000. Starting simulation...
+info: Entering event queue @ 506026543000. Starting simulation...
+info: Entering event queue @ 506050935000. Starting simulation...
switching cpus
-info: Entering event queue @ 515966288000. Starting simulation...
+info: Entering event queue @ 506050937000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 516966288000. Starting simulation...
+info: Entering event queue @ 507050937000. Starting simulation...
switching cpus
-info: Entering event queue @ 525966288000. Starting simulation...
+info: Entering event queue @ 516026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 526966288000. Starting simulation...
+info: Entering event queue @ 517026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 535966288000. Starting simulation...
+info: Entering event queue @ 526026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 536966288000. Starting simulation...
+info: Entering event queue @ 527026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 545966288000. Starting simulation...
+info: Entering event queue @ 536026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 546966288000. Starting simulation...
+info: Entering event queue @ 537026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 555966288000. Starting simulation...
+info: Entering event queue @ 546026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 556966288000. Starting simulation...
+info: Entering event queue @ 547026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 565966288000. Starting simulation...
+info: Entering event queue @ 556026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 566966288000. Starting simulation...
+info: Entering event queue @ 557026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 575966288000. Starting simulation...
+info: Entering event queue @ 566026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 576966288000. Starting simulation...
+info: Entering event queue @ 567026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 585966288000. Starting simulation...
+info: Entering event queue @ 576026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 586966288000. Starting simulation...
+info: Entering event queue @ 577026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 595966288000. Starting simulation...
+info: Entering event queue @ 586026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 596966288000. Starting simulation...
+info: Entering event queue @ 587026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 605966288000. Starting simulation...
+info: Entering event queue @ 596026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 606966288000. Starting simulation...
+info: Entering event queue @ 597026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 615966288000. Starting simulation...
+info: Entering event queue @ 606026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 616966288000. Starting simulation...
+info: Entering event queue @ 607026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 625966288000. Starting simulation...
+info: Entering event queue @ 616026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 626966288000. Starting simulation...
-info: Entering event queue @ 635966288000. Starting simulation...
-info: Entering event queue @ 636871372000. Starting simulation...
+info: Entering event queue @ 617026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 636871374000. Starting simulation...
+info: Entering event queue @ 626026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 637871374000. Starting simulation...
+info: Entering event queue @ 627026543000. Starting simulation...
+info: Entering event queue @ 636026543000. Starting simulation...
+info: Entering event queue @ 636994938000. Starting simulation...
switching cpus
-info: Entering event queue @ 645966288000. Starting simulation...
+info: Entering event queue @ 636994940000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 646966288000. Starting simulation...
+info: Entering event queue @ 637994940000. Starting simulation...
switching cpus
-info: Entering event queue @ 655966288000. Starting simulation...
+info: Entering event queue @ 646026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 656966288000. Starting simulation...
+info: Entering event queue @ 647026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 665966288000. Starting simulation...
+info: Entering event queue @ 656026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 666966288000. Starting simulation...
+info: Entering event queue @ 657026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 675966288000. Starting simulation...
+info: Entering event queue @ 666026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 676966288000. Starting simulation...
+info: Entering event queue @ 667026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 685966288000. Starting simulation...
+info: Entering event queue @ 676026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 686966288000. Starting simulation...
+info: Entering event queue @ 677026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 695966288000. Starting simulation...
+info: Entering event queue @ 686026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 696966288000. Starting simulation...
+info: Entering event queue @ 687026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 705966288000. Starting simulation...
+info: Entering event queue @ 696026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 706966288000. Starting simulation...
+info: Entering event queue @ 697026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 715966288000. Starting simulation...
+info: Entering event queue @ 706026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 716966288000. Starting simulation...
+info: Entering event queue @ 707026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 725966288000. Starting simulation...
+info: Entering event queue @ 716026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 726966288000. Starting simulation...
+info: Entering event queue @ 717026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 735966288000. Starting simulation...
+info: Entering event queue @ 726026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 736966288000. Starting simulation...
+info: Entering event queue @ 727026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 745966288000. Starting simulation...
+info: Entering event queue @ 736026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 746966288000. Starting simulation...
+info: Entering event queue @ 737026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 755966288000. Starting simulation...
+info: Entering event queue @ 746026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 756966288000. Starting simulation...
+info: Entering event queue @ 747026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 765966288000. Starting simulation...
+info: Entering event queue @ 756026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 766966288000. Starting simulation...
+info: Entering event queue @ 757026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 775966288000. Starting simulation...
+info: Entering event queue @ 766026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 776966288000. Starting simulation...
+info: Entering event queue @ 767026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 785966288000. Starting simulation...
+info: Entering event queue @ 776026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 786966288000. Starting simulation...
+info: Entering event queue @ 777026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 795966288000. Starting simulation...
+info: Entering event queue @ 786026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 796966288000. Starting simulation...
+info: Entering event queue @ 787026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 805966288000. Starting simulation...
+info: Entering event queue @ 796026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 806966288000. Starting simulation...
+info: Entering event queue @ 797026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 815966288000. Starting simulation...
+info: Entering event queue @ 806026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 816966288000. Starting simulation...
+info: Entering event queue @ 807026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 825966288000. Starting simulation...
+info: Entering event queue @ 816026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 826966288000. Starting simulation...
+info: Entering event queue @ 817026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 835966288000. Starting simulation...
+info: Entering event queue @ 826026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 836966288000. Starting simulation...
+info: Entering event queue @ 827026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 845966288000. Starting simulation...
+info: Entering event queue @ 836026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 846966288000. Starting simulation...
+info: Entering event queue @ 837026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 855966288000. Starting simulation...
+info: Entering event queue @ 846026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 856966288000. Starting simulation...
-info: Entering event queue @ 865966288000. Starting simulation...
-info: Entering event queue @ 866025280000. Starting simulation...
+info: Entering event queue @ 847026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 866025282000. Starting simulation...
+info: Entering event queue @ 856026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 867025282000. Starting simulation...
+info: Entering event queue @ 857026543000. Starting simulation...
+info: Entering event queue @ 866026543000. Starting simulation...
+info: Entering event queue @ 866148955000. Starting simulation...
switching cpus
-info: Entering event queue @ 875966288000. Starting simulation...
+info: Entering event queue @ 866148957000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 876966288000. Starting simulation...
+info: Entering event queue @ 867148957000. Starting simulation...
switching cpus
-info: Entering event queue @ 885966288000. Starting simulation...
+info: Entering event queue @ 876026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 886966288000. Starting simulation...
+info: Entering event queue @ 877026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 895966288000. Starting simulation...
+info: Entering event queue @ 886026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 896966288000. Starting simulation...
+info: Entering event queue @ 887026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 905966288000. Starting simulation...
+info: Entering event queue @ 896026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 906966288000. Starting simulation...
+info: Entering event queue @ 897026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 915966288000. Starting simulation...
+info: Entering event queue @ 906026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 916966288000. Starting simulation...
+info: Entering event queue @ 907026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 925966288000. Starting simulation...
+info: Entering event queue @ 916026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 926966288000. Starting simulation...
+info: Entering event queue @ 917026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 935966288000. Starting simulation...
+info: Entering event queue @ 926026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 936966288000. Starting simulation...
+info: Entering event queue @ 927026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 945966288000. Starting simulation...
+info: Entering event queue @ 936026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 946966288000. Starting simulation...
+info: Entering event queue @ 937026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 955966288000. Starting simulation...
+info: Entering event queue @ 946026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 956966288000. Starting simulation...
+info: Entering event queue @ 947026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 965966288000. Starting simulation...
+info: Entering event queue @ 956026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 966966288000. Starting simulation...
+info: Entering event queue @ 957026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 975966288000. Starting simulation...
+info: Entering event queue @ 966026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 976966288000. Starting simulation...
+info: Entering event queue @ 967026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 985966288000. Starting simulation...
+info: Entering event queue @ 976026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 986966288000. Starting simulation...
-info: Entering event queue @ 995966288000. Starting simulation...
-info: Entering event queue @ 996970147000. Starting simulation...
+info: Entering event queue @ 977026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 996970149000. Starting simulation...
+info: Entering event queue @ 986026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 997970149000. Starting simulation...
+info: Entering event queue @ 987026543000. Starting simulation...
+info: Entering event queue @ 996026543000. Starting simulation...
+info: Entering event queue @ 997094339000. Starting simulation...
switching cpus
-info: Entering event queue @ 1005966288000. Starting simulation...
+info: Entering event queue @ 997094341000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1006966288000. Starting simulation...
+info: Entering event queue @ 998094341000. Starting simulation...
switching cpus
-info: Entering event queue @ 1015966288000. Starting simulation...
+info: Entering event queue @ 1006026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1016966288000. Starting simulation...
+info: Entering event queue @ 1007026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1025966288000. Starting simulation...
+info: Entering event queue @ 1016026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1026966288000. Starting simulation...
+info: Entering event queue @ 1017026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1035966288000. Starting simulation...
+info: Entering event queue @ 1026026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1036966288000. Starting simulation...
+info: Entering event queue @ 1027026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1045966288000. Starting simulation...
+info: Entering event queue @ 1036026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1046966288000. Starting simulation...
+info: Entering event queue @ 1037026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1055966288000. Starting simulation...
+info: Entering event queue @ 1046026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1056966288000. Starting simulation...
+info: Entering event queue @ 1047026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1065966288000. Starting simulation...
+info: Entering event queue @ 1056026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1066966288000. Starting simulation...
+info: Entering event queue @ 1057026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1075966288000. Starting simulation...
+info: Entering event queue @ 1066026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1076966288000. Starting simulation...
+info: Entering event queue @ 1067026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1085966288000. Starting simulation...
+info: Entering event queue @ 1076026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1086966288000. Starting simulation...
+info: Entering event queue @ 1077026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1095966288000. Starting simulation...
+info: Entering event queue @ 1086026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1096966288000. Starting simulation...
+info: Entering event queue @ 1087026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1105966288000. Starting simulation...
+info: Entering event queue @ 1096026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1106966288000. Starting simulation...
+info: Entering event queue @ 1097026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1115966288000. Starting simulation...
+info: Entering event queue @ 1106026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1116966288000. Starting simulation...
+info: Entering event queue @ 1107026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1125966288000. Starting simulation...
+info: Entering event queue @ 1116026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1126966288000. Starting simulation...
+info: Entering event queue @ 1117026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1135966288000. Starting simulation...
+info: Entering event queue @ 1126026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1136966288000. Starting simulation...
+info: Entering event queue @ 1127026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1145966288000. Starting simulation...
+info: Entering event queue @ 1136026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1146966288000. Starting simulation...
+info: Entering event queue @ 1137026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1155966288000. Starting simulation...
+info: Entering event queue @ 1146026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1156966288000. Starting simulation...
+info: Entering event queue @ 1147026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1165966288000. Starting simulation...
+info: Entering event queue @ 1156026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1166966288000. Starting simulation...
+info: Entering event queue @ 1157026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1175966288000. Starting simulation...
+info: Entering event queue @ 1166026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1176966288000. Starting simulation...
+info: Entering event queue @ 1167026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1185966288000. Starting simulation...
+info: Entering event queue @ 1176026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1186966288000. Starting simulation...
+info: Entering event queue @ 1177026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1195966288000. Starting simulation...
+info: Entering event queue @ 1186026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1196966288000. Starting simulation...
+info: Entering event queue @ 1187026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1205966288000. Starting simulation...
+info: Entering event queue @ 1196026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1206966288000. Starting simulation...
+info: Entering event queue @ 1197026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1215966288000. Starting simulation...
+info: Entering event queue @ 1206026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1216966288000. Starting simulation...
-info: Entering event queue @ 1225966288000. Starting simulation...
-info: Entering event queue @ 1226123905000. Starting simulation...
+info: Entering event queue @ 1207026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1226123907000. Starting simulation...
+info: Entering event queue @ 1216026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1227123907000. Starting simulation...
+info: Entering event queue @ 1217026543000. Starting simulation...
+info: Entering event queue @ 1226026543000. Starting simulation...
+info: Entering event queue @ 1226248314000. Starting simulation...
switching cpus
-info: Entering event queue @ 1235966288000. Starting simulation...
+info: Entering event queue @ 1226248316000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1236966288000. Starting simulation...
+info: Entering event queue @ 1227248316000. Starting simulation...
switching cpus
-info: Entering event queue @ 1245966288000. Starting simulation...
+info: Entering event queue @ 1236026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1246966288000. Starting simulation...
+info: Entering event queue @ 1237026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1255966288000. Starting simulation...
+info: Entering event queue @ 1246026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1256966288000. Starting simulation...
+info: Entering event queue @ 1247026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1265966288000. Starting simulation...
+info: Entering event queue @ 1256026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1266966288000. Starting simulation...
+info: Entering event queue @ 1257026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1275966288000. Starting simulation...
+info: Entering event queue @ 1266026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1276966288000. Starting simulation...
+info: Entering event queue @ 1267026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1285966288000. Starting simulation...
+info: Entering event queue @ 1276026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1286966288000. Starting simulation...
+info: Entering event queue @ 1277026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1295966288000. Starting simulation...
+info: Entering event queue @ 1286026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1296966288000. Starting simulation...
+info: Entering event queue @ 1287026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1305966288000. Starting simulation...
+info: Entering event queue @ 1296026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1306966288000. Starting simulation...
+info: Entering event queue @ 1297026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1315966288000. Starting simulation...
+info: Entering event queue @ 1306026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1316966288000. Starting simulation...
+info: Entering event queue @ 1307026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1325966288000. Starting simulation...
+info: Entering event queue @ 1316026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1326966288000. Starting simulation...
+info: Entering event queue @ 1317026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1335966288000. Starting simulation...
+info: Entering event queue @ 1326026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1336966288000. Starting simulation...
+info: Entering event queue @ 1327026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1345966288000. Starting simulation...
+info: Entering event queue @ 1336026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1346966288000. Starting simulation...
-info: Entering event queue @ 1355966288000. Starting simulation...
-info: Entering event queue @ 1357069231000. Starting simulation...
+info: Entering event queue @ 1337026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1357069233000. Starting simulation...
+info: Entering event queue @ 1346026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1358069233000. Starting simulation...
+info: Entering event queue @ 1347026543000. Starting simulation...
+info: Entering event queue @ 1356026543000. Starting simulation...
+info: Entering event queue @ 1357193547000. Starting simulation...
switching cpus
-info: Entering event queue @ 1365966288000. Starting simulation...
+info: Entering event queue @ 1357193549000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1366966288000. Starting simulation...
+info: Entering event queue @ 1358193549000. Starting simulation...
switching cpus
-info: Entering event queue @ 1375966288000. Starting simulation...
+info: Entering event queue @ 1366026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1376966288000. Starting simulation...
+info: Entering event queue @ 1367026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1385966288000. Starting simulation...
+info: Entering event queue @ 1376026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1386966288000. Starting simulation...
+info: Entering event queue @ 1377026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1395966288000. Starting simulation...
+info: Entering event queue @ 1386026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1396966288000. Starting simulation...
+info: Entering event queue @ 1387026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1405966288000. Starting simulation...
+info: Entering event queue @ 1396026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1406966288000. Starting simulation...
+info: Entering event queue @ 1397026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1415966288000. Starting simulation...
+info: Entering event queue @ 1406026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1416966288000. Starting simulation...
+info: Entering event queue @ 1407026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1425966288000. Starting simulation...
+info: Entering event queue @ 1416026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1426966288000. Starting simulation...
+info: Entering event queue @ 1417026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1435966288000. Starting simulation...
+info: Entering event queue @ 1426026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1436966288000. Starting simulation...
+info: Entering event queue @ 1427026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1445966288000. Starting simulation...
+info: Entering event queue @ 1436026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1446966288000. Starting simulation...
+info: Entering event queue @ 1437026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1455966288000. Starting simulation...
+info: Entering event queue @ 1446026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1456966288000. Starting simulation...
+info: Entering event queue @ 1447026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1465966288000. Starting simulation...
+info: Entering event queue @ 1456026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1466966288000. Starting simulation...
+info: Entering event queue @ 1457026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1475966288000. Starting simulation...
+info: Entering event queue @ 1466026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1476966288000. Starting simulation...
+info: Entering event queue @ 1467026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1485966288000. Starting simulation...
+info: Entering event queue @ 1476026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1486966288000. Starting simulation...
+info: Entering event queue @ 1477026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1495966288000. Starting simulation...
+info: Entering event queue @ 1486026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1496966288000. Starting simulation...
+info: Entering event queue @ 1487026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1505966288000. Starting simulation...
+info: Entering event queue @ 1496026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1506966288000. Starting simulation...
+info: Entering event queue @ 1497026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1515966288000. Starting simulation...
+info: Entering event queue @ 1506026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1516966288000. Starting simulation...
+info: Entering event queue @ 1507026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1525966288000. Starting simulation...
+info: Entering event queue @ 1516026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1526966288000. Starting simulation...
+info: Entering event queue @ 1517026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1535966288000. Starting simulation...
+info: Entering event queue @ 1526026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1536966288000. Starting simulation...
+info: Entering event queue @ 1527026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1545966288000. Starting simulation...
+info: Entering event queue @ 1536026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1546966288000. Starting simulation...
+info: Entering event queue @ 1537026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1555966288000. Starting simulation...
+info: Entering event queue @ 1546026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1556966288000. Starting simulation...
+info: Entering event queue @ 1547026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1565966288000. Starting simulation...
+info: Entering event queue @ 1556026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1566966288000. Starting simulation...
+info: Entering event queue @ 1557026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1575966288000. Starting simulation...
+info: Entering event queue @ 1566026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1576966288000. Starting simulation...
-info: Entering event queue @ 1585966288000. Starting simulation...
-info: Entering event queue @ 1586222989000. Starting simulation...
+info: Entering event queue @ 1567026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1586222991000. Starting simulation...
+info: Entering event queue @ 1576026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1587222991000. Starting simulation...
+info: Entering event queue @ 1577026543000. Starting simulation...
+info: Entering event queue @ 1586026543000. Starting simulation...
+info: Entering event queue @ 1586347543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1595966288000. Starting simulation...
+info: Entering event queue @ 1586347545000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1596966288000. Starting simulation...
+info: Entering event queue @ 1587347545000. Starting simulation...
switching cpus
-info: Entering event queue @ 1605966288000. Starting simulation...
+info: Entering event queue @ 1596026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1606966288000. Starting simulation...
+info: Entering event queue @ 1597026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1615966288000. Starting simulation...
+info: Entering event queue @ 1606026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1616966288000. Starting simulation...
+info: Entering event queue @ 1607026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1625966288000. Starting simulation...
+info: Entering event queue @ 1616026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1626966288000. Starting simulation...
+info: Entering event queue @ 1617026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1635966288000. Starting simulation...
+info: Entering event queue @ 1626026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1636966288000. Starting simulation...
+info: Entering event queue @ 1627026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1645966288000. Starting simulation...
+info: Entering event queue @ 1636026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1646966288000. Starting simulation...
+info: Entering event queue @ 1637026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1655966288000. Starting simulation...
+info: Entering event queue @ 1646026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1656966288000. Starting simulation...
+info: Entering event queue @ 1647026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1665966288000. Starting simulation...
+info: Entering event queue @ 1656026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1666966288000. Starting simulation...
+info: Entering event queue @ 1657026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1675966288000. Starting simulation...
+info: Entering event queue @ 1666026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1676966288000. Starting simulation...
+info: Entering event queue @ 1667026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1685966288000. Starting simulation...
+info: Entering event queue @ 1676026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1686966288000. Starting simulation...
+info: Entering event queue @ 1677026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1695966288000. Starting simulation...
+info: Entering event queue @ 1686026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1696966288000. Starting simulation...
+info: Entering event queue @ 1687026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1705966288000. Starting simulation...
+info: Entering event queue @ 1696026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1706966288000. Starting simulation...
-info: Entering event queue @ 1715966288000. Starting simulation...
-info: Entering event queue @ 1717167856000. Starting simulation...
+info: Entering event queue @ 1697026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1717167858000. Starting simulation...
+info: Entering event queue @ 1706026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1718167858000. Starting simulation...
+info: Entering event queue @ 1707026543000. Starting simulation...
+info: Entering event queue @ 1716026543000. Starting simulation...
+info: Entering event queue @ 1717291739000. Starting simulation...
switching cpus
-info: Entering event queue @ 1725966288000. Starting simulation...
+info: Entering event queue @ 1717291741000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1726966288000. Starting simulation...
+info: Entering event queue @ 1718291741000. Starting simulation...
switching cpus
-info: Entering event queue @ 1735966288000. Starting simulation...
+info: Entering event queue @ 1726026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1736966288000. Starting simulation...
+info: Entering event queue @ 1727026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1745966288000. Starting simulation...
+info: Entering event queue @ 1736026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1746966288000. Starting simulation...
+info: Entering event queue @ 1737026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1755966288000. Starting simulation...
+info: Entering event queue @ 1746026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1756966288000. Starting simulation...
+info: Entering event queue @ 1747026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1765966288000. Starting simulation...
+info: Entering event queue @ 1756026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1766966288000. Starting simulation...
+info: Entering event queue @ 1757026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1775966288000. Starting simulation...
+info: Entering event queue @ 1766026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1776966288000. Starting simulation...
+info: Entering event queue @ 1767026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1785966288000. Starting simulation...
+info: Entering event queue @ 1776026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1786966288000. Starting simulation...
+info: Entering event queue @ 1777026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1795966288000. Starting simulation...
+info: Entering event queue @ 1786026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1796966288000. Starting simulation...
+info: Entering event queue @ 1787026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1805966288000. Starting simulation...
+info: Entering event queue @ 1796026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1806966288000. Starting simulation...
+info: Entering event queue @ 1797026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1815966288000. Starting simulation...
+info: Entering event queue @ 1806026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1816966288000. Starting simulation...
+info: Entering event queue @ 1807026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1825966288000. Starting simulation...
+info: Entering event queue @ 1816026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1826966288000. Starting simulation...
+info: Entering event queue @ 1817026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1835966288000. Starting simulation...
+info: Entering event queue @ 1826026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1836966288000. Starting simulation...
+info: Entering event queue @ 1827026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1845966288000. Starting simulation...
+info: Entering event queue @ 1836026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1846966288000. Starting simulation...
+info: Entering event queue @ 1837026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1855966288000. Starting simulation...
+info: Entering event queue @ 1846026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1856966288000. Starting simulation...
+info: Entering event queue @ 1847026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1865966288000. Starting simulation...
+info: Entering event queue @ 1856026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1866966288000. Starting simulation...
+info: Entering event queue @ 1857026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1875966288000. Starting simulation...
+info: Entering event queue @ 1866026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1876966288000. Starting simulation...
+info: Entering event queue @ 1867026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1885966288000. Starting simulation...
+info: Entering event queue @ 1876026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1886966288000. Starting simulation...
+info: Entering event queue @ 1877026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1895966288000. Starting simulation...
+info: Entering event queue @ 1886026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1896966288000. Starting simulation...
+info: Entering event queue @ 1887026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1905966288000. Starting simulation...
+info: Entering event queue @ 1896026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1906966288000. Starting simulation...
+info: Entering event queue @ 1897026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1915966288000. Starting simulation...
+info: Entering event queue @ 1906026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1916966288000. Starting simulation...
+info: Entering event queue @ 1907026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1925966288000. Starting simulation...
+info: Entering event queue @ 1916026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1926966288000. Starting simulation...
+info: Entering event queue @ 1917026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1935966288000. Starting simulation...
+info: Entering event queue @ 1926026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1936966288000. Starting simulation...
-info: Entering event queue @ 1945966288000. Starting simulation...
-info: Entering event queue @ 1946321761000. Starting simulation...
+info: Entering event queue @ 1927026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1946321763000. Starting simulation...
+info: Entering event queue @ 1936026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1947321763000. Starting simulation...
+info: Entering event queue @ 1937026543000. Starting simulation...
+info: Entering event queue @ 1946026543000. Starting simulation...
+info: Entering event queue @ 1946445714000. Starting simulation...
switching cpus
-info: Entering event queue @ 1955966288000. Starting simulation...
+info: Entering event queue @ 1946445716000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1956966288000. Starting simulation...
+info: Entering event queue @ 1947445716000. Starting simulation...
switching cpus
-info: Entering event queue @ 1965966288000. Starting simulation...
+info: Entering event queue @ 1956026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1966966288000. Starting simulation...
+info: Entering event queue @ 1957026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1975966288000. Starting simulation...
+info: Entering event queue @ 1966026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1976966288000. Starting simulation...
+info: Entering event queue @ 1967026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1985966288000. Starting simulation...
+info: Entering event queue @ 1976026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1986966288000. Starting simulation...
+info: Entering event queue @ 1977026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 1995966288000. Starting simulation...
+info: Entering event queue @ 1986026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1996966288000. Starting simulation...
+info: Entering event queue @ 1987026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2005966288000. Starting simulation...
+info: Entering event queue @ 1996026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2006966288000. Starting simulation...
+info: Entering event queue @ 1997026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2015966288000. Starting simulation...
+info: Entering event queue @ 2006026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2016966288000. Starting simulation...
+info: Entering event queue @ 2007026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2025966288000. Starting simulation...
+info: Entering event queue @ 2016026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2026966288000. Starting simulation...
+info: Entering event queue @ 2017026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2035966288000. Starting simulation...
+info: Entering event queue @ 2026026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2036966288000. Starting simulation...
+info: Entering event queue @ 2027026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2045966288000. Starting simulation...
+info: Entering event queue @ 2036026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2046966288000. Starting simulation...
+info: Entering event queue @ 2037026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2055966288000. Starting simulation...
+info: Entering event queue @ 2046026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2056966288000. Starting simulation...
+info: Entering event queue @ 2047026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2065966288000. Starting simulation...
+info: Entering event queue @ 2056026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2066966288000. Starting simulation...
-info: Entering event queue @ 2075966288000. Starting simulation...
-info: Entering event queue @ 2077266937000. Starting simulation...
+info: Entering event queue @ 2057026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2077266939000. Starting simulation...
+info: Entering event queue @ 2066026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2078266939000. Starting simulation...
+info: Entering event queue @ 2067026543000. Starting simulation...
+info: Entering event queue @ 2076026543000. Starting simulation...
+info: Entering event queue @ 2077390947000. Starting simulation...
switching cpus
-info: Entering event queue @ 2085966288000. Starting simulation...
+info: Entering event queue @ 2077390949000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2086966288000. Starting simulation...
+info: Entering event queue @ 2078390949000. Starting simulation...
switching cpus
-info: Entering event queue @ 2095966288000. Starting simulation...
+info: Entering event queue @ 2086026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2096966288000. Starting simulation...
+info: Entering event queue @ 2087026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2105966288000. Starting simulation...
+info: Entering event queue @ 2096026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2106966288000. Starting simulation...
+info: Entering event queue @ 2097026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2115966288000. Starting simulation...
+info: Entering event queue @ 2106026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2116966288000. Starting simulation...
+info: Entering event queue @ 2107026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2125966288000. Starting simulation...
+info: Entering event queue @ 2116026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2126966288000. Starting simulation...
+info: Entering event queue @ 2117026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2135966288000. Starting simulation...
+info: Entering event queue @ 2126026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2136966288000. Starting simulation...
+info: Entering event queue @ 2127026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2145966288000. Starting simulation...
+info: Entering event queue @ 2136026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2146966288000. Starting simulation...
+info: Entering event queue @ 2137026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2155966288000. Starting simulation...
+info: Entering event queue @ 2146026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2156966288000. Starting simulation...
+info: Entering event queue @ 2147026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2165966288000. Starting simulation...
+info: Entering event queue @ 2156026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2166966288000. Starting simulation...
+info: Entering event queue @ 2157026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2175966288000. Starting simulation...
+info: Entering event queue @ 2166026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2176966288000. Starting simulation...
+info: Entering event queue @ 2167026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2185966288000. Starting simulation...
+info: Entering event queue @ 2176026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2186966288000. Starting simulation...
+info: Entering event queue @ 2177026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2195966288000. Starting simulation...
+info: Entering event queue @ 2186026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2196966288000. Starting simulation...
+info: Entering event queue @ 2187026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2205966288000. Starting simulation...
+info: Entering event queue @ 2196026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2206966288000. Starting simulation...
+info: Entering event queue @ 2197026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2215966288000. Starting simulation...
+info: Entering event queue @ 2206026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2216966288000. Starting simulation...
+info: Entering event queue @ 2207026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2225966288000. Starting simulation...
+info: Entering event queue @ 2216026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2226966288000. Starting simulation...
+info: Entering event queue @ 2217026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2235966288000. Starting simulation...
+info: Entering event queue @ 2226026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2236966288000. Starting simulation...
+info: Entering event queue @ 2227026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2245966288000. Starting simulation...
+info: Entering event queue @ 2236026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2246966288000. Starting simulation...
+info: Entering event queue @ 2237026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2255966288000. Starting simulation...
+info: Entering event queue @ 2246026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2256966288000. Starting simulation...
+info: Entering event queue @ 2247026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2265966288000. Starting simulation...
+info: Entering event queue @ 2256026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2266966288000. Starting simulation...
+info: Entering event queue @ 2257026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2275966288000. Starting simulation...
+info: Entering event queue @ 2266026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2276966288000. Starting simulation...
-info: Entering event queue @ 2276966296500. Starting simulation...
-info: Entering event queue @ 2276966301000. Starting simulation...
+info: Entering event queue @ 2267026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2276966305500. Starting simulation...
+info: Entering event queue @ 2276026543000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2277966305500. Starting simulation...
-info: Entering event queue @ 2277966669500. Starting simulation...
-info: Entering event queue @ 2277966675000. Starting simulation...
+info: Entering event queue @ 2277026543000. Starting simulation...
switching cpus
-info: Entering event queue @ 2277966679500. Starting simulation...
+info: Entering event queue @ 2277026550500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2278966679500. Starting simulation...
+info: Entering event queue @ 2278026550500. Starting simulation...
switching cpus
-info: Entering event queue @ 2278966727000. Starting simulation...
+info: Entering event queue @ 2278026844500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2279966727000. Starting simulation...
+info: Entering event queue @ 2279026844500. Starting simulation...
switching cpus
-info: Entering event queue @ 2279966892500. Starting simulation...
+info: Entering event queue @ 2279028634000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2280966892500. Starting simulation...
+info: Entering event queue @ 2280028634000. Starting simulation...
switching cpus
-info: Entering event queue @ 2280967718000. Starting simulation...
+info: Entering event queue @ 2280028792000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2281967718000. Starting simulation...
+info: Entering event queue @ 2281028792000. Starting simulation...
switching cpus
-info: Entering event queue @ 2281967767000. Starting simulation...
+info: Entering event queue @ 2281031728500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2282967767000. Starting simulation...
+info: Entering event queue @ 2282031728500. Starting simulation...
switching cpus
-info: Entering event queue @ 2282971689500. Starting simulation...
+info: Entering event queue @ 2282031872000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2283971689500. Starting simulation...
+info: Entering event queue @ 2283031872000. Starting simulation...
switching cpus
-info: Entering event queue @ 2283971806000. Starting simulation...
+info: Entering event queue @ 2283037827500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2284971806000. Starting simulation...
+info: Entering event queue @ 2284037827500. Starting simulation...
switching cpus
-info: Entering event queue @ 2284971880000. Starting simulation...
+info: Entering event queue @ 2284037973000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2285971880000. Starting simulation...
+info: Entering event queue @ 2285037973000. Starting simulation...
switching cpus
-info: Entering event queue @ 2285971904500. Starting simulation...
+info: Entering event queue @ 2285038127500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2286971904500. Starting simulation...
+info: Entering event queue @ 2286038127500. Starting simulation...
switching cpus
-info: Entering event queue @ 2286972050000. Starting simulation...
+info: Entering event queue @ 2286038281000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2287972050000. Starting simulation...
+info: Entering event queue @ 2287038281000. Starting simulation...
switching cpus
-info: Entering event queue @ 2287972064000. Starting simulation...
+info: Entering event queue @ 2287038326000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2288972064000. Starting simulation...
+info: Entering event queue @ 2288038326000. Starting simulation...
switching cpus
-info: Entering event queue @ 2288972091500. Starting simulation...
+info: Entering event queue @ 2288038395000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2289972091500. Starting simulation...
+info: Entering event queue @ 2289038395000. Starting simulation...
switching cpus
-info: Entering event queue @ 2289980099000. Starting simulation...
+info: Entering event queue @ 2289038454000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2290980099000. Starting simulation...
+info: Entering event queue @ 2290038454000. Starting simulation...
switching cpus
-info: Entering event queue @ 2290980164000. Starting simulation...
+info: Entering event queue @ 2290043867000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2291980164000. Starting simulation...
+info: Entering event queue @ 2291043867000. Starting simulation...
switching cpus
-info: Entering event queue @ 2291980173000. Starting simulation...
+info: Entering event queue @ 2291044009000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2292980173000. Starting simulation...
+info: Entering event queue @ 2292044009000. Starting simulation...
switching cpus
-info: Entering event queue @ 2292980190000. Starting simulation...
+info: Entering event queue @ 2292044100000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2293980190000. Starting simulation...
+info: Entering event queue @ 2293044100000. Starting simulation...
switching cpus
-info: Entering event queue @ 2293980313000. Starting simulation...
+info: Entering event queue @ 2293044163000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2294980313000. Starting simulation...
+info: Entering event queue @ 2294044163000. Starting simulation...
switching cpus
-info: Entering event queue @ 2294980366000. Starting simulation...
+info: Entering event queue @ 2294044227000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2295980366000. Starting simulation...
+info: Entering event queue @ 2295044227000. Starting simulation...
switching cpus
-info: Entering event queue @ 2295980491500. Starting simulation...
+info: Entering event queue @ 2295044273000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2296980491500. Starting simulation...
+info: Entering event queue @ 2296044273000. Starting simulation...
switching cpus
-info: Entering event queue @ 2296980655000. Starting simulation...
+info: Entering event queue @ 2296044353500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2297980655000. Starting simulation...
-info: Entering event queue @ 2297980854500. Starting simulation...
+info: Entering event queue @ 2297044353500. Starting simulation...
switching cpus
-info: Entering event queue @ 2297980855500. Starting simulation...
+info: Entering event queue @ 2297044376000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2298980855500. Starting simulation...
+info: Entering event queue @ 2298044376000. Starting simulation...
switching cpus
-info: Entering event queue @ 2298980896000. Starting simulation...
+info: Entering event queue @ 2298044505000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2299980896000. Starting simulation...
-info: Entering event queue @ 2299988769500. Starting simulation...
-info: Entering event queue @ 2299988774500. Starting simulation...
+info: Entering event queue @ 2299044505000. Starting simulation...
switching cpus
-info: Entering event queue @ 2299988779000. Starting simulation...
+info: Entering event queue @ 2299044591000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2300988779000. Starting simulation...
+info: Entering event queue @ 2300044591000. Starting simulation...
+info: Entering event queue @ 2300054074500. Starting simulation...
+info: Entering event queue @ 2300054079500. Starting simulation...
switching cpus
-info: Entering event queue @ 2300988932000. Starting simulation...
+info: Entering event queue @ 2300054084000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2301988932000. Starting simulation...
+info: Entering event queue @ 2301054084000. Starting simulation...
switching cpus
-info: Entering event queue @ 2301988991000. Starting simulation...
+info: Entering event queue @ 2301054216000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2302988991000. Starting simulation...
+info: Entering event queue @ 2302054216000. Starting simulation...
switching cpus
-info: Entering event queue @ 2302998893000. Starting simulation...
+info: Entering event queue @ 2302054252000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2303998893000. Starting simulation...
+info: Entering event queue @ 2303054252000. Starting simulation...
switching cpus
-info: Entering event queue @ 2303999033000. Starting simulation...
+info: Entering event queue @ 2303064199000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2304999033000. Starting simulation...
-info: Entering event queue @ 2306420845000. Starting simulation...
+info: Entering event queue @ 2304064199000. Starting simulation...
switching cpus
-info: Entering event queue @ 2306420847000. Starting simulation...
+info: Entering event queue @ 2304064238000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2307420847000. Starting simulation...
+info: Entering event queue @ 2305064238000. Starting simulation...
+info: Entering event queue @ 2306544922000. Starting simulation...
switching cpus
-info: Entering event queue @ 2307429463000. Starting simulation...
+info: Entering event queue @ 2306544924000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2308429463000. Starting simulation...
+info: Entering event queue @ 2307544924000. Starting simulation...
switching cpus
-info: Entering event queue @ 2308429518000. Starting simulation...
+info: Entering event queue @ 2307554441000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2309429518000. Starting simulation...
+info: Entering event queue @ 2308554441000. Starting simulation...
switching cpus
-info: Entering event queue @ 2309436929000. Starting simulation...
+info: Entering event queue @ 2308554462000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2310436929000. Starting simulation...
-info: Entering event queue @ 2310445490500. Starting simulation...
-info: Entering event queue @ 2310445497000. Starting simulation...
+info: Entering event queue @ 2309554462000. Starting simulation...
switching cpus
-info: Entering event queue @ 2310445501500. Starting simulation...
+info: Entering event queue @ 2309561672000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2311445501500. Starting simulation...
+info: Entering event queue @ 2310561672000. Starting simulation...
+info: Entering event queue @ 2310570028500. Starting simulation...
+info: Entering event queue @ 2310570035000. Starting simulation...
switching cpus
-info: Entering event queue @ 2311445524000. Starting simulation...
+info: Entering event queue @ 2310570039500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2312445524000. Starting simulation...
+info: Entering event queue @ 2311570039500. Starting simulation...
switching cpus
-info: Entering event queue @ 2312445649000. Starting simulation...
+info: Entering event queue @ 2311570139000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2313445649000. Starting simulation...
+info: Entering event queue @ 2312570139000. Starting simulation...
switching cpus
-info: Entering event queue @ 2313445802000. Starting simulation...
+info: Entering event queue @ 2312570195000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2314445802000. Starting simulation...
+info: Entering event queue @ 2313570195000. Starting simulation...
switching cpus
-info: Entering event queue @ 2314445861000. Starting simulation...
+info: Entering event queue @ 2313570285000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2315445861000. Starting simulation...
+info: Entering event queue @ 2314570285000. Starting simulation...
switching cpus
-info: Entering event queue @ 2315445973000. Starting simulation...
+info: Entering event queue @ 2314570324500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2316445973000. Starting simulation...
+info: Entering event queue @ 2315570324500. Starting simulation...
switching cpus
-info: Entering event queue @ 2316446034000. Starting simulation...
+info: Entering event queue @ 2315570361000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2317446034000. Starting simulation...
+info: Entering event queue @ 2316570361000. Starting simulation...
switching cpus
-info: Entering event queue @ 2317446194500. Starting simulation...
+info: Entering event queue @ 2316570403500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2318446194500. Starting simulation...
+info: Entering event queue @ 2317570403500. Starting simulation...
switching cpus
-info: Entering event queue @ 2318446348000. Starting simulation...
+info: Entering event queue @ 2317570429000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2319446348000. Starting simulation...
+info: Entering event queue @ 2318570429000. Starting simulation...
switching cpus
-info: Entering event queue @ 2319446393000. Starting simulation...
+info: Entering event queue @ 2318570448000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2320446393000. Starting simulation...
-info: Entering event queue @ 2320446744000. Starting simulation...
+info: Entering event queue @ 2319570448000. Starting simulation...
switching cpus
-info: Entering event queue @ 2320446745000. Starting simulation...
+info: Entering event queue @ 2319570560000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2321446745000. Starting simulation...
+info: Entering event queue @ 2320570560000. Starting simulation...
switching cpus
-info: Entering event queue @ 2321446843000. Starting simulation...
+info: Entering event queue @ 2320570567500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2322446843000. Starting simulation...
+info: Entering event queue @ 2321570567500. Starting simulation...
switching cpus
-info: Entering event queue @ 2322446904000. Starting simulation...
+info: Entering event queue @ 2321570700000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2323446904000. Starting simulation...
+info: Entering event queue @ 2322570700000. Starting simulation...
switching cpus
-info: Entering event queue @ 2323456659000. Starting simulation...
+info: Entering event queue @ 2322570838000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2324456659000. Starting simulation...
+info: Entering event queue @ 2323570838000. Starting simulation...
switching cpus
-info: Entering event queue @ 2324456757000. Starting simulation...
+info: Entering event queue @ 2323570953000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2325456757000. Starting simulation...
+info: Entering event queue @ 2324570953000. Starting simulation...
switching cpus
-info: Entering event queue @ 2325456829500. Starting simulation...
+info: Entering event queue @ 2324571046000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2326456829500. Starting simulation...
+info: Entering event queue @ 2325571046000. Starting simulation...
switching cpus
-info: Entering event queue @ 2326458375000. Starting simulation...
+info: Entering event queue @ 2325571075000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2327458375000. Starting simulation...
+info: Entering event queue @ 2326571075000. Starting simulation...
switching cpus
-info: Entering event queue @ 2327458422000. Starting simulation...
+info: Entering event queue @ 2326571130000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2328458422000. Starting simulation...
+info: Entering event queue @ 2327571130000. Starting simulation...
switching cpus
-info: Entering event queue @ 2328458566500. Starting simulation...
+info: Entering event queue @ 2327571202000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2329458566500. Starting simulation...
+info: Entering event queue @ 2328571202000. Starting simulation...
switching cpus
-info: Entering event queue @ 2329458584500. Starting simulation...
+info: Entering event queue @ 2328571330000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2330458584500. Starting simulation...
+info: Entering event queue @ 2329571330000. Starting simulation...
switching cpus
-info: Entering event queue @ 2330458701000. Starting simulation...
+info: Entering event queue @ 2329571413000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2331458701000. Starting simulation...
+info: Entering event queue @ 2330571413000. Starting simulation...
switching cpus
-info: Entering event queue @ 2331458728000. Starting simulation...
+info: Entering event queue @ 2330571445000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2332458728000. Starting simulation...
+info: Entering event queue @ 2331571445000. Starting simulation...
switching cpus
-info: Entering event queue @ 2332458887000. Starting simulation...
+info: Entering event queue @ 2331571479000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2333458887000. Starting simulation...
+info: Entering event queue @ 2332571479000. Starting simulation...
switching cpus
-info: Entering event queue @ 2333458927000. Starting simulation...
+info: Entering event queue @ 2332581124000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2334458927000. Starting simulation...
+info: Entering event queue @ 2333581124000. Starting simulation...
switching cpus
-info: Entering event queue @ 2334458930500. Starting simulation...
+info: Entering event queue @ 2333581247000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2335458930500. Starting simulation...
+info: Entering event queue @ 2334581247000. Starting simulation...
+info: Entering event queue @ 2334581254500. Starting simulation...
switching cpus
-info: Entering event queue @ 2335458946000. Starting simulation...
+info: Entering event queue @ 2334581257000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2336458946000. Starting simulation...
+info: Entering event queue @ 2335581257000. Starting simulation...
switching cpus
-info: Entering event queue @ 2336460942000. Starting simulation...
+info: Entering event queue @ 2335581419000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2337460942000. Starting simulation...
+info: Entering event queue @ 2336581419000. Starting simulation...
switching cpus
-info: Entering event queue @ 2337461094000. Starting simulation...
+info: Entering event queue @ 2336590347000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2338461094000. Starting simulation...
-info: Entering event queue @ 2339157445000. Starting simulation...
+info: Entering event queue @ 2337590347000. Starting simulation...
+info: Entering event queue @ 2339281522000. Starting simulation...
switching cpus
-info: Entering event queue @ 2339157447000. Starting simulation...
+info: Entering event queue @ 2339281524000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2340157447000. Starting simulation...
+info: Entering event queue @ 2340281524000. Starting simulation...
switching cpus
-info: Entering event queue @ 2340161367000. Starting simulation...
+info: Entering event queue @ 2340281630500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2341161367000. Starting simulation...
+info: Entering event queue @ 2341281630500. Starting simulation...
switching cpus
-info: Entering event queue @ 2341161393000. Starting simulation...
+info: Entering event queue @ 2341281710000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2342161393000. Starting simulation...
+info: Entering event queue @ 2342281710000. Starting simulation...
switching cpus
-info: Entering event queue @ 2342161440000. Starting simulation...
+info: Entering event queue @ 2342281728000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2343161440000. Starting simulation...
+info: Entering event queue @ 2343281728000. Starting simulation...
switching cpus
-info: Entering event queue @ 2343161538000. Starting simulation...
+info: Entering event queue @ 2343281745500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2344161538000. Starting simulation...
+info: Entering event queue @ 2344281745500. Starting simulation...
switching cpus
-info: Entering event queue @ 2344161625000. Starting simulation...
+info: Entering event queue @ 2344281816000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2345161625000. Starting simulation...
+info: Entering event queue @ 2345281816000. Starting simulation...
switching cpus
-info: Entering event queue @ 2345161713500. Starting simulation...
+info: Entering event queue @ 2345281843000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2346161713500. Starting simulation...
+info: Entering event queue @ 2346281843000. Starting simulation...
switching cpus
-info: Entering event queue @ 2346161788500. Starting simulation...
+info: Entering event queue @ 2346281957000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2347161788500. Starting simulation...
+info: Entering event queue @ 2347281957000. Starting simulation...
switching cpus
-info: Entering event queue @ 2347161936000. Starting simulation...
+info: Entering event queue @ 2347282029000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2348161936000. Starting simulation...
+info: Entering event queue @ 2348282029000. Starting simulation...
switching cpus
-info: Entering event queue @ 2348162002000. Starting simulation...
+info: Entering event queue @ 2348282128000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2349162002000. Starting simulation...
+info: Entering event queue @ 2349282128000. Starting simulation...
switching cpus
-info: Entering event queue @ 2349162065000. Starting simulation...
+info: Entering event queue @ 2349282215000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2350162065000. Starting simulation...
+info: Entering event queue @ 2350282215000. Starting simulation...
switching cpus
-info: Entering event queue @ 2350162134000. Starting simulation...
+info: Entering event queue @ 2350282373000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2351162134000. Starting simulation...
+info: Entering event queue @ 2351282373000. Starting simulation...
switching cpus
-info: Entering event queue @ 2351162263000. Starting simulation...
+info: Entering event queue @ 2351282490000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2352162263000. Starting simulation...
+info: Entering event queue @ 2352282490000. Starting simulation...
switching cpus
-info: Entering event queue @ 2352162285000. Starting simulation...
+info: Entering event queue @ 2352282616000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2353162285000. Starting simulation...
+info: Entering event queue @ 2353282616000. Starting simulation...
switching cpus
-info: Entering event queue @ 2353170607000. Starting simulation...
+info: Entering event queue @ 2353282704000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2354170607000. Starting simulation...
+info: Entering event queue @ 2354282704000. Starting simulation...
switching cpus
-info: Entering event queue @ 2354170736000. Starting simulation...
+info: Entering event queue @ 2354292637000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2355170736000. Starting simulation...
+info: Entering event queue @ 2355292637000. Starting simulation...
switching cpus
-info: Entering event queue @ 2355170892500. Starting simulation...
+info: Entering event queue @ 2355292752000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2356170892500. Starting simulation...
+info: Entering event queue @ 2356292752000. Starting simulation...
switching cpus
-info: Entering event queue @ 2356172531000. Starting simulation...
+info: Entering event queue @ 2356292829000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2357172531000. Starting simulation...
+info: Entering event queue @ 2357292829000. Starting simulation...
switching cpus
-info: Entering event queue @ 2357172559000. Starting simulation...
+info: Entering event queue @ 2357295010000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2358172559000. Starting simulation...
+info: Entering event queue @ 2358295010000. Starting simulation...
switching cpus
-info: Entering event queue @ 2358172614000. Starting simulation...
+info: Entering event queue @ 2358295060000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2359172614000. Starting simulation...
+info: Entering event queue @ 2359295060000. Starting simulation...
switching cpus
-info: Entering event queue @ 2359172646000. Starting simulation...
+info: Entering event queue @ 2359295117000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2360172646000. Starting simulation...
+info: Entering event queue @ 2360295117000. Starting simulation...
switching cpus
-info: Entering event queue @ 2360172678000. Starting simulation...
+info: Entering event queue @ 2360295201000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2361172678000. Starting simulation...
+info: Entering event queue @ 2361295201000. Starting simulation...
switching cpus
-info: Entering event queue @ 2361172808000. Starting simulation...
+info: Entering event queue @ 2361295232000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2362172808000. Starting simulation...
+info: Entering event queue @ 2362295232000. Starting simulation...
switching cpus
-info: Entering event queue @ 2362172960000. Starting simulation...
+info: Entering event queue @ 2362295364500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2363172960000. Starting simulation...
+info: Entering event queue @ 2363295364500. Starting simulation...
switching cpus
-info: Entering event queue @ 2363178221000. Starting simulation...
+info: Entering event queue @ 2363295520000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2364178221000. Starting simulation...
+info: Entering event queue @ 2364295520000. Starting simulation...
switching cpus
-info: Entering event queue @ 2364178280000. Starting simulation...
+info: Entering event queue @ 2364301747000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2365178280000. Starting simulation...
+info: Entering event queue @ 2365301747000. Starting simulation...
switching cpus
-info: Entering event queue @ 2365178287500. Starting simulation...
+info: Entering event queue @ 2365301807000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2366178287500. Starting simulation...
+info: Entering event queue @ 2366301807000. Starting simulation...
switching cpus
-info: Entering event queue @ 2366178360000. Starting simulation...
+info: Entering event queue @ 2366301912000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2367178360000. Starting simulation...
+info: Entering event queue @ 2367301912000. Starting simulation...
switching cpus
-info: Entering event queue @ 2367178437000. Starting simulation...
+info: Entering event queue @ 2367304066000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2368178437000. Starting simulation...
+info: Entering event queue @ 2368304066000. Starting simulation...
switching cpus
-info: Entering event queue @ 2368178488000. Starting simulation...
+info: Entering event queue @ 2368304184000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2369178488000. Starting simulation...
+info: Entering event queue @ 2369304184000. Starting simulation...
switching cpus
-info: Entering event queue @ 2369178596000. Starting simulation...
+info: Entering event queue @ 2369304297000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2370178596000. Starting simulation...
+info: Entering event queue @ 2370304297000. Starting simulation...
switching cpus
-info: Entering event queue @ 2370178656000. Starting simulation...
+info: Entering event queue @ 2370304370000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2371178656000. Starting simulation...
-info: Entering event queue @ 2371894045000. Starting simulation...
+info: Entering event queue @ 2371304370000. Starting simulation...
+info: Entering event queue @ 2372016955000. Starting simulation...
switching cpus
-info: Entering event queue @ 2371894047000. Starting simulation...
+info: Entering event queue @ 2372016957000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2372894047000. Starting simulation...
+info: Entering event queue @ 2373016957000. Starting simulation...
switching cpus
-info: Entering event queue @ 2372894102500. Starting simulation...
+info: Entering event queue @ 2373017069000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2373894102500. Starting simulation...
+info: Entering event queue @ 2374017069000. Starting simulation...
switching cpus
-info: Entering event queue @ 2373894137500. Starting simulation...
+info: Entering event queue @ 2374019359000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2374894137500. Starting simulation...
+info: Entering event queue @ 2375019359000. Starting simulation...
switching cpus
-info: Entering event queue @ 2374894259000. Starting simulation...
+info: Entering event queue @ 2375019391000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2375894259000. Starting simulation...
+info: Entering event queue @ 2376019391000. Starting simulation...
switching cpus
-info: Entering event queue @ 2375894306000. Starting simulation...
+info: Entering event queue @ 2376019468000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2376894306000. Starting simulation...
+info: Entering event queue @ 2377019468000. Starting simulation...
switching cpus
-info: Entering event queue @ 2376900398000. Starting simulation...
+info: Entering event queue @ 2377019493500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2377900398000. Starting simulation...
+info: Entering event queue @ 2378019493500. Starting simulation...
switching cpus
-info: Entering event queue @ 2377900421000. Starting simulation...
+info: Entering event queue @ 2378019501000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2378900421000. Starting simulation...
+info: Entering event queue @ 2379019501000. Starting simulation...
switching cpus
-info: Entering event queue @ 2378900488500. Starting simulation...
+info: Entering event queue @ 2379019576000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2379900488500. Starting simulation...
+info: Entering event queue @ 2380019576000. Starting simulation...
switching cpus
-info: Entering event queue @ 2379900521000. Starting simulation...
+info: Entering event queue @ 2380019732000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2380900521000. Starting simulation...
+info: Entering event queue @ 2381019732000. Starting simulation...
switching cpus
-info: Entering event queue @ 2380900624000. Starting simulation...
+info: Entering event queue @ 2381028816000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2381900624000. Starting simulation...
+info: Entering event queue @ 2382028816000. Starting simulation...
switching cpus
-info: Entering event queue @ 2381900718000. Starting simulation...
+info: Entering event queue @ 2382028916000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2382900718000. Starting simulation...
+info: Entering event queue @ 2383028916000. Starting simulation...
switching cpus
-info: Entering event queue @ 2382900790000. Starting simulation...
+info: Entering event queue @ 2383028989000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2383900790000. Starting simulation...
+info: Entering event queue @ 2384028989000. Starting simulation...
switching cpus
-info: Entering event queue @ 2383900839000. Starting simulation...
+info: Entering event queue @ 2384029150000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2384900839000. Starting simulation...
+info: Entering event queue @ 2385029150000. Starting simulation...
switching cpus
-info: Entering event queue @ 2384910381000. Starting simulation...
+info: Entering event queue @ 2385029168000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2385910381000. Starting simulation...
+info: Entering event queue @ 2386029168000. Starting simulation...
switching cpus
-info: Entering event queue @ 2385910485000. Starting simulation...
+info: Entering event queue @ 2386029178000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2386910485000. Starting simulation...
+info: Entering event queue @ 2387029178000. Starting simulation...
switching cpus
-info: Entering event queue @ 2386910628000. Starting simulation...
+info: Entering event queue @ 2387029238000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2387910628000. Starting simulation...
+info: Entering event queue @ 2388029238000. Starting simulation...
switching cpus
-info: Entering event queue @ 2387911152000. Starting simulation...
+info: Entering event queue @ 2388029333000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2388911152000. Starting simulation...
+info: Entering event queue @ 2389029333000. Starting simulation...
switching cpus
-info: Entering event queue @ 2388914114000. Starting simulation...
+info: Entering event queue @ 2389029370000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2389914114000. Starting simulation...
+info: Entering event queue @ 2390029370000. Starting simulation...
switching cpus
-info: Entering event queue @ 2389914243000. Starting simulation...
+info: Entering event queue @ 2390029405000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2390914243000. Starting simulation...
+info: Entering event queue @ 2391029405000. Starting simulation...
switching cpus
-info: Entering event queue @ 2390914368000. Starting simulation...
+info: Entering event queue @ 2391029529500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2391914368000. Starting simulation...
+info: Entering event queue @ 2392029529500. Starting simulation...
switching cpus
-info: Entering event queue @ 2391914402000. Starting simulation...
+info: Entering event queue @ 2392029617500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2392914402000. Starting simulation...
+info: Entering event queue @ 2393029617500. Starting simulation...
switching cpus
-info: Entering event queue @ 2392914536000. Starting simulation...
+info: Entering event queue @ 2393029685500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2393914536000. Starting simulation...
+info: Entering event queue @ 2394029685500. Starting simulation...
switching cpus
-info: Entering event queue @ 2393914563000. Starting simulation...
+info: Entering event queue @ 2394029788000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2394914563000. Starting simulation...
+info: Entering event queue @ 2395029788000. Starting simulation...
switching cpus
-info: Entering event queue @ 2394914712000. Starting simulation...
+info: Entering event queue @ 2395029853000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2395914712000. Starting simulation...
+info: Entering event queue @ 2396029853000. Starting simulation...
switching cpus
-info: Entering event queue @ 2395914740000. Starting simulation...
+info: Entering event queue @ 2396029864500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2396914740000. Starting simulation...
+info: Entering event queue @ 2397029864500. Starting simulation...
switching cpus
-info: Entering event queue @ 2396914806500. Starting simulation...
+info: Entering event queue @ 2397029943500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2397914806500. Starting simulation...
+info: Entering event queue @ 2398029943500. Starting simulation...
switching cpus
-info: Entering event queue @ 2397914904000. Starting simulation...
+info: Entering event queue @ 2398030031500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2398914904000. Starting simulation...
+info: Entering event queue @ 2399030031500. Starting simulation...
switching cpus
-info: Entering event queue @ 2398914957000. Starting simulation...
+info: Entering event queue @ 2399030085500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2399914957000. Starting simulation...
+info: Entering event queue @ 2400030085500. Starting simulation...
switching cpus
-info: Entering event queue @ 2399915059000. Starting simulation...
+info: Entering event queue @ 2400030175000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2400915059000. Starting simulation...
+info: Entering event queue @ 2401030175000. Starting simulation...
switching cpus
-info: Entering event queue @ 2400915130000. Starting simulation...
+info: Entering event queue @ 2401030308000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2401915130000. Starting simulation...
-info: Entering event queue @ 2401915136500. Starting simulation...
+info: Entering event queue @ 2402030308000. Starting simulation...
switching cpus
-info: Entering event queue @ 2401915141000. Starting simulation...
+info: Entering event queue @ 2402030463000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2402915141000. Starting simulation...
+info: Entering event queue @ 2403030463000. Starting simulation...
+info: Entering event queue @ 2403036923000. Starting simulation...
+info: Entering event queue @ 2403036924000. Starting simulation...
switching cpus
-info: Entering event queue @ 2402915191000. Starting simulation...
+info: Entering event queue @ 2403036928500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2403915191000. Starting simulation...
-info: Entering event queue @ 2404629421000. Starting simulation...
+info: Entering event queue @ 2404036928500. Starting simulation...
+info: Entering event queue @ 2404753534000. Starting simulation...
switching cpus
-info: Entering event queue @ 2404629423000. Starting simulation...
+info: Entering event queue @ 2404753536000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2405629423000. Starting simulation...
+info: Entering event queue @ 2405753536000. Starting simulation...
switching cpus
-info: Entering event queue @ 2405629508000. Starting simulation...
+info: Entering event queue @ 2405753688000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2406629508000. Starting simulation...
+info: Entering event queue @ 2406753688000. Starting simulation...
switching cpus
-info: Entering event queue @ 2406632022000. Starting simulation...
+info: Entering event queue @ 2406753797500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2407632022000. Starting simulation...
+info: Entering event queue @ 2407753797500. Starting simulation...
switching cpus
-info: Entering event queue @ 2407632051000. Starting simulation...
+info: Entering event queue @ 2407753845500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2408632051000. Starting simulation...
+info: Entering event queue @ 2408753845500. Starting simulation...
switching cpus
-info: Entering event queue @ 2408632082000. Starting simulation...
+info: Entering event queue @ 2408753915000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2409632082000. Starting simulation...
+info: Entering event queue @ 2409753915000. Starting simulation...
switching cpus
-info: Entering event queue @ 2409632155000. Starting simulation...
+info: Entering event queue @ 2409754052000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2410632155000. Starting simulation...
+info: Entering event queue @ 2410754052000. Starting simulation...
switching cpus
-info: Entering event queue @ 2410632268000. Starting simulation...
+info: Entering event queue @ 2410754121000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2411632268000. Starting simulation...
+info: Entering event queue @ 2411754121000. Starting simulation...
switching cpus
-info: Entering event queue @ 2411632347000. Starting simulation...
+info: Entering event queue @ 2411754241000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2412632347000. Starting simulation...
+info: Entering event queue @ 2412754241000. Starting simulation...
switching cpus
-info: Entering event queue @ 2412632398000. Starting simulation...
+info: Entering event queue @ 2412754335000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2413632398000. Starting simulation...
+info: Entering event queue @ 2413754335000. Starting simulation...
switching cpus
-info: Entering event queue @ 2413632529000. Starting simulation...
+info: Entering event queue @ 2413754496000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2414632529000. Starting simulation...
+info: Entering event queue @ 2414754496000. Starting simulation...
switching cpus
-info: Entering event queue @ 2414632639500. Starting simulation...
+info: Entering event queue @ 2414754503500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2415632639500. Starting simulation...
+info: Entering event queue @ 2415754503500. Starting simulation...
switching cpus
-info: Entering event queue @ 2415632664000. Starting simulation...
+info: Entering event queue @ 2415754548000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2416632664000. Starting simulation...
+info: Entering event queue @ 2416754548000. Starting simulation...
switching cpus
-info: Entering event queue @ 2416632740000. Starting simulation...
+info: Entering event queue @ 2416754666000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2417632740000. Starting simulation...
+info: Entering event queue @ 2417754666000. Starting simulation...
switching cpus
-info: Entering event queue @ 2417632859000. Starting simulation...
+info: Entering event queue @ 2417754746500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2418632859000. Starting simulation...
+info: Entering event queue @ 2418754746500. Starting simulation...
switching cpus
-info: Entering event queue @ 2418633034000. Starting simulation...
+info: Entering event queue @ 2418754759000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2419633034000. Starting simulation...
+info: Entering event queue @ 2419754759000. Starting simulation...
switching cpus
-info: Entering event queue @ 2419633059000. Starting simulation...
+info: Entering event queue @ 2419754791000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2420633059000. Starting simulation...
+info: Entering event queue @ 2420754791000. Starting simulation...
switching cpus
-info: Entering event queue @ 2420633160000. Starting simulation...
+info: Entering event queue @ 2420763573000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2421633160000. Starting simulation...
+info: Entering event queue @ 2421763573000. Starting simulation...
switching cpus
-info: Entering event queue @ 2421633208000. Starting simulation...
+info: Entering event queue @ 2421763627000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2422633208000. Starting simulation...
+info: Entering event queue @ 2422763627000. Starting simulation...
switching cpus
-info: Entering event queue @ 2422633239000. Starting simulation...
+info: Entering event queue @ 2422763683000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2423633239000. Starting simulation...
+info: Entering event queue @ 2423763683000. Starting simulation...
switching cpus
-info: Entering event queue @ 2423633384000. Starting simulation...
+info: Entering event queue @ 2423763816000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2424633384000. Starting simulation...
+info: Entering event queue @ 2424763816000. Starting simulation...
switching cpus
-info: Entering event queue @ 2424633545000. Starting simulation...
+info: Entering event queue @ 2424763896000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2425633545000. Starting simulation...
+info: Entering event queue @ 2425763896000. Starting simulation...
switching cpus
-info: Entering event queue @ 2425633690000. Starting simulation...
+info: Entering event queue @ 2425764024500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2426633690000. Starting simulation...
+info: Entering event queue @ 2426764024500. Starting simulation...
switching cpus
-info: Entering event queue @ 2426641613000. Starting simulation...
+info: Entering event queue @ 2426764049000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2427641613000. Starting simulation...
+info: Entering event queue @ 2427764049000. Starting simulation...
switching cpus
-info: Entering event queue @ 2427641770000. Starting simulation...
+info: Entering event queue @ 2427764185000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2428641770000. Starting simulation...
+info: Entering event queue @ 2428764185000. Starting simulation...
switching cpus
-info: Entering event queue @ 2428641908500. Starting simulation...
+info: Entering event queue @ 2428770274000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2429641908500. Starting simulation...
+info: Entering event queue @ 2429770274000. Starting simulation...
switching cpus
-info: Entering event queue @ 2429641980500. Starting simulation...
+info: Entering event queue @ 2429770406000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2430641980500. Starting simulation...
+info: Entering event queue @ 2430770406000. Starting simulation...
switching cpus
-info: Entering event queue @ 2430642039000. Starting simulation...
+info: Entering event queue @ 2430770512000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2431642039000. Starting simulation...
+info: Entering event queue @ 2431770512000. Starting simulation...
switching cpus
-info: Entering event queue @ 2431645440000. Starting simulation...
+info: Entering event queue @ 2431770631000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2432645440000. Starting simulation...
+info: Entering event queue @ 2432770631000. Starting simulation...
switching cpus
-info: Entering event queue @ 2432645529000. Starting simulation...
+info: Entering event queue @ 2432770756000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2433645529000. Starting simulation...
+info: Entering event queue @ 2433770756000. Starting simulation...
switching cpus
-info: Entering event queue @ 2433645687500. Starting simulation...
+info: Entering event queue @ 2433771542000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2434645687500. Starting simulation...
+info: Entering event queue @ 2434771542000. Starting simulation...
switching cpus
-info: Entering event queue @ 2434645756000. Starting simulation...
+info: Entering event queue @ 2434771640000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2435645756000. Starting simulation...
+info: Entering event queue @ 2435771640000. Starting simulation...
switching cpus
-info: Entering event queue @ 2435645838500. Starting simulation...
+info: Entering event queue @ 2435771648000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2436645838500. Starting simulation...
-info: Entering event queue @ 2437366021000. Starting simulation...
+info: Entering event queue @ 2436771648000. Starting simulation...
+info: Entering event queue @ 2437490134000. Starting simulation...
switching cpus
-info: Entering event queue @ 2437366023000. Starting simulation...
+info: Entering event queue @ 2437490136000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2438366023000. Starting simulation...
+info: Entering event queue @ 2438490136000. Starting simulation...
switching cpus
-info: Entering event queue @ 2438371168000. Starting simulation...
+info: Entering event queue @ 2438490158000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2439371168000. Starting simulation...
+info: Entering event queue @ 2439490158000. Starting simulation...
switching cpus
-info: Entering event queue @ 2439371194000. Starting simulation...
+info: Entering event queue @ 2439490217000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2440371194000. Starting simulation...
+info: Entering event queue @ 2440490217000. Starting simulation...
switching cpus
-info: Entering event queue @ 2440371226000. Starting simulation...
+info: Entering event queue @ 2440490335500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2441371226000. Starting simulation...
+info: Entering event queue @ 2441490335500. Starting simulation...
switching cpus
-info: Entering event queue @ 2441371358000. Starting simulation...
+info: Entering event queue @ 2441490449000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2442371358000. Starting simulation...
+info: Entering event queue @ 2442490449000. Starting simulation...
switching cpus
-info: Entering event queue @ 2442371517000. Starting simulation...
+info: Entering event queue @ 2442490551000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2443371517000. Starting simulation...
+info: Entering event queue @ 2443490551000. Starting simulation...
switching cpus
-info: Entering event queue @ 2443380978000. Starting simulation...
+info: Entering event queue @ 2443490670000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2444380978000. Starting simulation...
+info: Entering event queue @ 2444490670000. Starting simulation...
switching cpus
-info: Entering event queue @ 2444381084000. Starting simulation...
+info: Entering event queue @ 2444490744000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2445381084000. Starting simulation...
+info: Entering event queue @ 2445490744000. Starting simulation...
switching cpus
-info: Entering event queue @ 2445381144000. Starting simulation...
+info: Entering event queue @ 2445499008000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2446381144000. Starting simulation...
+info: Entering event queue @ 2446499008000. Starting simulation...
switching cpus
-info: Entering event queue @ 2446383015000. Starting simulation...
+info: Entering event queue @ 2446499143000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2447383015000. Starting simulation...
+info: Entering event queue @ 2447499143000. Starting simulation...
switching cpus
-info: Entering event queue @ 2447383090000. Starting simulation...
+info: Entering event queue @ 2447499251000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2448383090000. Starting simulation...
+info: Entering event queue @ 2448499251000. Starting simulation...
switching cpus
-info: Entering event queue @ 2448383163000. Starting simulation...
+info: Entering event queue @ 2448501472000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2449383163000. Starting simulation...
+info: Entering event queue @ 2449501472000. Starting simulation...
switching cpus
-info: Entering event queue @ 2449383307000. Starting simulation...
+info: Entering event queue @ 2449501552000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2450383307000. Starting simulation...
+info: Entering event queue @ 2450501552000. Starting simulation...
switching cpus
-info: Entering event queue @ 2450383397000. Starting simulation...
+info: Entering event queue @ 2450501708000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2451383397000. Starting simulation...
+info: Entering event queue @ 2451501708000. Starting simulation...
switching cpus
-info: Entering event queue @ 2451383538000. Starting simulation...
+info: Entering event queue @ 2451501752500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2452383538000. Starting simulation...
+info: Entering event queue @ 2452501752500. Starting simulation...
switching cpus
-info: Entering event queue @ 2452383697000. Starting simulation...
+info: Entering event queue @ 2452501854000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2453383697000. Starting simulation...
+info: Entering event queue @ 2453501854000. Starting simulation...
switching cpus
-info: Entering event queue @ 2453383787000. Starting simulation...
+info: Entering event queue @ 2453501960000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2454383787000. Starting simulation...
+info: Entering event queue @ 2454501960000. Starting simulation...
switching cpus
-info: Entering event queue @ 2454383902500. Starting simulation...
+info: Entering event queue @ 2454502105000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2455383902500. Starting simulation...
+info: Entering event queue @ 2455502105000. Starting simulation...
switching cpus
-info: Entering event queue @ 2455384008500. Starting simulation...
+info: Entering event queue @ 2455502233000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2456384008500. Starting simulation...
+info: Entering event queue @ 2456502233000. Starting simulation...
switching cpus
-info: Entering event queue @ 2456384150000. Starting simulation...
+info: Entering event queue @ 2456502345000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2457384150000. Starting simulation...
+info: Entering event queue @ 2457502345000. Starting simulation...
switching cpus
-info: Entering event queue @ 2457384245000. Starting simulation...
+info: Entering event queue @ 2457502439000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2458384245000. Starting simulation...
+info: Entering event queue @ 2458502439000. Starting simulation...
switching cpus
-info: Entering event queue @ 2458384323500. Starting simulation...
+info: Entering event queue @ 2458502524000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2459384323500. Starting simulation...
+info: Entering event queue @ 2459502524000. Starting simulation...
switching cpus
-info: Entering event queue @ 2459384411000. Starting simulation...
+info: Entering event queue @ 2459502597500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2460384411000. Starting simulation...
+info: Entering event queue @ 2460502597500. Starting simulation...
switching cpus
-info: Entering event queue @ 2460393475000. Starting simulation...
+info: Entering event queue @ 2460502627000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2461393475000. Starting simulation...
+info: Entering event queue @ 2461502627000. Starting simulation...
switching cpus
-info: Entering event queue @ 2461393549000. Starting simulation...
+info: Entering event queue @ 2461502675000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2462393549000. Starting simulation...
+info: Entering event queue @ 2462502675000. Starting simulation...
switching cpus
-info: Entering event queue @ 2462393584000. Starting simulation...
+info: Entering event queue @ 2462502774500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2463393584000. Starting simulation...
+info: Entering event queue @ 2463502774500. Starting simulation...
switching cpus
-info: Entering event queue @ 2463393618000. Starting simulation...
+info: Entering event queue @ 2463502818000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2464393618000. Starting simulation...
+info: Entering event queue @ 2464502818000. Starting simulation...
switching cpus
-info: Entering event queue @ 2464393740000. Starting simulation...
+info: Entering event queue @ 2464502945000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2465393740000. Starting simulation...
+info: Entering event queue @ 2465502945000. Starting simulation...
switching cpus
-info: Entering event queue @ 2465393843000. Starting simulation...
+info: Entering event queue @ 2465511849000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2466393843000. Starting simulation...
+info: Entering event queue @ 2466511849000. Starting simulation...
switching cpus
-info: Entering event queue @ 2466393993000. Starting simulation...
+info: Entering event queue @ 2466511856500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2467393993000. Starting simulation...
+info: Entering event queue @ 2467511856500. Starting simulation...
switching cpus
-info: Entering event queue @ 2467394007000. Starting simulation...
+info: Entering event queue @ 2467512001000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2468394007000. Starting simulation...
+info: Entering event queue @ 2468512001000. Starting simulation...
switching cpus
-info: Entering event queue @ 2468394131000. Starting simulation...
+info: Entering event queue @ 2468512063000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2469394131000. Starting simulation...
-info: Entering event queue @ 2470103845000. Starting simulation...
+info: Entering event queue @ 2469512063000. Starting simulation...
+info: Entering event queue @ 2470225739000. Starting simulation...
switching cpus
-info: Entering event queue @ 2470103847000. Starting simulation...
+info: Entering event queue @ 2470225741000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2471103847000. Starting simulation...
+info: Entering event queue @ 2471225741000. Starting simulation...
switching cpus
-info: Entering event queue @ 2471103944000. Starting simulation...
+info: Entering event queue @ 2471226221500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2472103944000. Starting simulation...
+info: Entering event queue @ 2472226221500. Starting simulation...
switching cpus
-info: Entering event queue @ 2472103960000. Starting simulation...
+info: Entering event queue @ 2472226357000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2473103960000. Starting simulation...
+info: Entering event queue @ 2473226357000. Starting simulation...
switching cpus
-info: Entering event queue @ 2473104036500. Starting simulation...
+info: Entering event queue @ 2473226411000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2474104036500. Starting simulation...
+info: Entering event queue @ 2474226411000. Starting simulation...
switching cpus
-info: Entering event queue @ 2474104223500. Starting simulation...
+info: Entering event queue @ 2474226515000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2475104223500. Starting simulation...
+info: Entering event queue @ 2475226515000. Starting simulation...
switching cpus
-info: Entering event queue @ 2475104380000. Starting simulation...
+info: Entering event queue @ 2475226537000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2476104380000. Starting simulation...
+info: Entering event queue @ 2476226537000. Starting simulation...
switching cpus
-info: Entering event queue @ 2476104409500. Starting simulation...
+info: Entering event queue @ 2476226570000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2477104409500. Starting simulation...
-info: Entering event queue @ 2477104413500. Starting simulation...
-info: Entering event queue @ 2477104421500. Starting simulation...
+info: Entering event queue @ 2477226570000. Starting simulation...
switching cpus
-info: Entering event queue @ 2477104426000. Starting simulation...
+info: Entering event queue @ 2477230887000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2478104426000. Starting simulation...
+info: Entering event queue @ 2478230887000. Starting simulation...
+info: Entering event queue @ 2478231272000. Starting simulation...
switching cpus
-info: Entering event queue @ 2478104963000. Starting simulation...
+info: Entering event queue @ 2478231279500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2479104963000. Starting simulation...
+info: Entering event queue @ 2479231279500. Starting simulation...
switching cpus
-info: Entering event queue @ 2479105061000. Starting simulation...
+info: Entering event queue @ 2479231321000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2480105061000. Starting simulation...
+info: Entering event queue @ 2480231321000. Starting simulation...
switching cpus
-info: Entering event queue @ 2480105119000. Starting simulation...
+info: Entering event queue @ 2480231467000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2481105119000. Starting simulation...
+info: Entering event queue @ 2481231467000. Starting simulation...
switching cpus
-info: Entering event queue @ 2481105221000. Starting simulation...
+info: Entering event queue @ 2481237971000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2482105221000. Starting simulation...
+info: Entering event queue @ 2482237971000. Starting simulation...
switching cpus
-info: Entering event queue @ 2482105269000. Starting simulation...
+info: Entering event queue @ 2482238135000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2483105269000. Starting simulation...
+info: Entering event queue @ 2483238135000. Starting simulation...
switching cpus
-info: Entering event queue @ 2483105409000. Starting simulation...
+info: Entering event queue @ 2483238269000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2484105409000. Starting simulation...
+info: Entering event queue @ 2484238269000. Starting simulation...
switching cpus
-info: Entering event queue @ 2484105474000. Starting simulation...
+info: Entering event queue @ 2484238311000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2485105474000. Starting simulation...
+info: Entering event queue @ 2485238311000. Starting simulation...
switching cpus
-info: Entering event queue @ 2485105631000. Starting simulation...
+info: Entering event queue @ 2485238411000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2486105631000. Starting simulation...
+info: Entering event queue @ 2486238411000. Starting simulation...
switching cpus
-info: Entering event queue @ 2486105717000. Starting simulation...
+info: Entering event queue @ 2486238487000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2487105717000. Starting simulation...
+info: Entering event queue @ 2487238487000. Starting simulation...
switching cpus
-info: Entering event queue @ 2487105777000. Starting simulation...
+info: Entering event queue @ 2487239689000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2488105777000. Starting simulation...
-info: Entering event queue @ 2488109208500. Starting simulation...
-info: Entering event queue @ 2488109213500. Starting simulation...
+info: Entering event queue @ 2488239689000. Starting simulation...
switching cpus
-info: Entering event queue @ 2488109218000. Starting simulation...
+info: Entering event queue @ 2488239724000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2489109218000. Starting simulation...
+info: Entering event queue @ 2489239724000. Starting simulation...
switching cpus
-info: Entering event queue @ 2489113875500. Starting simulation...
+info: Entering event queue @ 2489244495500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2490113875500. Starting simulation...
+info: Entering event queue @ 2490244495500. Starting simulation...
+info: Entering event queue @ 2490244503000. Starting simulation...
switching cpus
-info: Entering event queue @ 2490113878000. Starting simulation...
+info: Entering event queue @ 2490244507500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2491113878000. Starting simulation...
+info: Entering event queue @ 2491244507500. Starting simulation...
switching cpus
-info: Entering event queue @ 2491116979000. Starting simulation...
+info: Entering event queue @ 2491244516000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2492116979000. Starting simulation...
+info: Entering event queue @ 2492244516000. Starting simulation...
switching cpus
-info: Entering event queue @ 2492117002000. Starting simulation...
+info: Entering event queue @ 2492244536000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2493117002000. Starting simulation...
+info: Entering event queue @ 2493244536000. Starting simulation...
switching cpus
-info: Entering event queue @ 2493117162000. Starting simulation...
+info: Entering event queue @ 2493251837000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2494117162000. Starting simulation...
+info: Entering event queue @ 2494251837000. Starting simulation...
switching cpus
-info: Entering event queue @ 2494117254000. Starting simulation...
+info: Entering event queue @ 2494251954000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2495117254000. Starting simulation...
+info: Entering event queue @ 2495251954000. Starting simulation...
switching cpus
-info: Entering event queue @ 2495117340000. Starting simulation...
+info: Entering event queue @ 2495252012000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2496117340000. Starting simulation...
+info: Entering event queue @ 2496252012000. Starting simulation...
switching cpus
-info: Entering event queue @ 2496126635000. Starting simulation...
+info: Entering event queue @ 2496255849000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2497126635000. Starting simulation...
+info: Entering event queue @ 2497255849000. Starting simulation...
switching cpus
-info: Entering event queue @ 2497126690000. Starting simulation...
+info: Entering event queue @ 2497255860000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2498126690000. Starting simulation...
+info: Entering event queue @ 2498255860000. Starting simulation...
switching cpus
-info: Entering event queue @ 2498126787000. Starting simulation...
+info: Entering event queue @ 2498256024000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2499126787000. Starting simulation...
+info: Entering event queue @ 2499256024000. Starting simulation...
switching cpus
-info: Entering event queue @ 2499126938000. Starting simulation...
+info: Entering event queue @ 2499256176000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2500126938000. Starting simulation...
+info: Entering event queue @ 2500256176000. Starting simulation...
switching cpus
-info: Entering event queue @ 2500126982000. Starting simulation...
+info: Entering event queue @ 2500256276000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2501126982000. Starting simulation...
+info: Entering event queue @ 2501256276000. Starting simulation...
+info: Entering event queue @ 2502962318000. Starting simulation...
switching cpus
-info: Entering event queue @ 2501127036000. Starting simulation...
+info: Entering event queue @ 2502962320000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2502127036000. Starting simulation...
-info: Entering event queue @ 2502839680000. Starting simulation...
+info: Entering event queue @ 2503962320000. Starting simulation...
switching cpus
-info: Entering event queue @ 2502839682000. Starting simulation...
+info: Entering event queue @ 2503962362000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2503839682000. Starting simulation...
+info: Entering event queue @ 2504962362000. Starting simulation...
switching cpus
-info: Entering event queue @ 2503839688500. Starting simulation...
+info: Entering event queue @ 2504962512000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2504839688500. Starting simulation...
+info: Entering event queue @ 2505962512000. Starting simulation...
+info: Entering event queue @ 2505962525000. Starting simulation...
+info: Entering event queue @ 2505962534000. Starting simulation...
+info: Entering event queue @ 2505962538500. Starting simulation...
switching cpus
-info: Entering event queue @ 2504839737000. Starting simulation...
+info: Entering event queue @ 2505962539500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2505839737000. Starting simulation...
+info: Entering event queue @ 2506962539500. Starting simulation...
switching cpus
-info: Entering event queue @ 2505839779500. Starting simulation...
+info: Entering event queue @ 2506962568500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2506839779500. Starting simulation...
+info: Entering event queue @ 2507962568500. Starting simulation...
switching cpus
-info: Entering event queue @ 2506839943000. Starting simulation...
+info: Entering event queue @ 2507970193000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2507839943000. Starting simulation...
+info: Entering event queue @ 2508970193000. Starting simulation...
switching cpus
-info: Entering event queue @ 2507840084000. Starting simulation...
+info: Entering event queue @ 2508970326000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2508840084000. Starting simulation...
+info: Entering event queue @ 2509970326000. Starting simulation...
switching cpus
-info: Entering event queue @ 2508844290000. Starting simulation...
+info: Entering event queue @ 2509970419000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2509844290000. Starting simulation...
+info: Entering event queue @ 2510970419000. Starting simulation...
switching cpus
-info: Entering event queue @ 2509844368000. Starting simulation...
+info: Entering event queue @ 2510970429000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2510844368000. Starting simulation...
+info: Entering event queue @ 2511970429000. Starting simulation...
switching cpus
-info: Entering event queue @ 2510844455000. Starting simulation...
+info: Entering event queue @ 2511974054000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2511844455000. Starting simulation...
+info: Entering event queue @ 2512974054000. Starting simulation...
switching cpus
-info: Entering event queue @ 2511844611000. Starting simulation...
+info: Entering event queue @ 2512974121500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2512844611000. Starting simulation...
+info: Entering event queue @ 2513974121500. Starting simulation...
switching cpus
-info: Entering event queue @ 2512844690000. Starting simulation...
+info: Entering event queue @ 2513974129000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2513844690000. Starting simulation...
+info: Entering event queue @ 2514974129000. Starting simulation...
switching cpus
-info: Entering event queue @ 2513853962000. Starting simulation...
+info: Entering event queue @ 2514975356000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2514853962000. Starting simulation...
+info: Entering event queue @ 2515975356000. Starting simulation...
switching cpus
-info: Entering event queue @ 2514854068000. Starting simulation...
+info: Entering event queue @ 2515975454000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2515854068000. Starting simulation...
+info: Entering event queue @ 2516975454000. Starting simulation...
switching cpus
-info: Entering event queue @ 2515854102000. Starting simulation...
+info: Entering event queue @ 2516975552000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2516854102000. Starting simulation...
+info: Entering event queue @ 2517975552000. Starting simulation...
switching cpus
-info: Entering event queue @ 2516855790000. Starting simulation...
+info: Entering event queue @ 2517982622000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2517855790000. Starting simulation...
+info: Entering event queue @ 2518982622000. Starting simulation...
switching cpus
-info: Entering event queue @ 2517855884500. Starting simulation...
+info: Entering event queue @ 2518982687000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2518855884500. Starting simulation...
-info: Entering event queue @ 2518859439500. Starting simulation...
-info: Entering event queue @ 2518859449000. Starting simulation...
-info: Entering event queue @ 2518859453500. Starting simulation...
+info: Entering event queue @ 2519982687000. Starting simulation...
switching cpus
-info: Entering event queue @ 2518859454500. Starting simulation...
+info: Entering event queue @ 2519982786000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2519859454500. Starting simulation...
+info: Entering event queue @ 2520982786000. Starting simulation...
+info: Entering event queue @ 2520988988500. Starting simulation...
+info: Entering event queue @ 2520988994500. Starting simulation...
switching cpus
-info: Entering event queue @ 2519859612000. Starting simulation...
+info: Entering event queue @ 2520988999000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2520859612000. Starting simulation...
+info: Entering event queue @ 2521988999000. Starting simulation...
switching cpus
-info: Entering event queue @ 2520859743000. Starting simulation...
+info: Entering event queue @ 2521989071000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2521859743000. Starting simulation...
+info: Entering event queue @ 2522989071000. Starting simulation...
switching cpus
-info: Entering event queue @ 2521859796000. Starting simulation...
+info: Entering event queue @ 2522989085500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2522859796000. Starting simulation...
+info: Entering event queue @ 2523989085500. Starting simulation...
switching cpus
-info: Entering event queue @ 2522859820000. Starting simulation...
+info: Entering event queue @ 2523989143000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2523859820000. Starting simulation...
+info: Entering event queue @ 2524989143000. Starting simulation...
switching cpus
-info: Entering event queue @ 2523859876000. Starting simulation...
+info: Entering event queue @ 2524989219000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2524859876000. Starting simulation...
+info: Entering event queue @ 2525989219000. Starting simulation...
switching cpus
-info: Entering event queue @ 2524859972500. Starting simulation...
+info: Entering event queue @ 2525998131000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2525859972500. Starting simulation...
+info: Entering event queue @ 2526998131000. Starting simulation...
switching cpus
-info: Entering event queue @ 2525859990000. Starting simulation...
+info: Entering event queue @ 2527002132000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2526859990000. Starting simulation...
+info: Entering event queue @ 2528002132000. Starting simulation...
switching cpus
-info: Entering event queue @ 2526860000500. Starting simulation...
+info: Entering event queue @ 2528002139500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2527860000500. Starting simulation...
+info: Entering event queue @ 2529002139500. Starting simulation...
switching cpus
-info: Entering event queue @ 2527860004000. Starting simulation...
+info: Entering event queue @ 2529002278000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2528860004000. Starting simulation...
+info: Entering event queue @ 2530002278000. Starting simulation...
+info: Entering event queue @ 2530002328000. Starting simulation...
switching cpus
-info: Entering event queue @ 2528860008500. Starting simulation...
+info: Entering event queue @ 2530002335500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2529860008500. Starting simulation...
+info: Entering event queue @ 2531002335500. Starting simulation...
switching cpus
-info: Entering event queue @ 2529860052000. Starting simulation...
+info: Entering event queue @ 2531002354000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2530860052000. Starting simulation...
+info: Entering event queue @ 2532002354000. Starting simulation...
switching cpus
-info: Entering event queue @ 2530860057000. Starting simulation...
+info: Entering event queue @ 2532006673000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2531860057000. Starting simulation...
+info: Entering event queue @ 2533006673000. Starting simulation...
switching cpus
-info: Entering event queue @ 2531860059000. Starting simulation...
+info: Entering event queue @ 2533015860500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2532860059000. Starting simulation...
+info: Entering event queue @ 2534015860500. Starting simulation...
+info: Entering event queue @ 2535698918000. Starting simulation...
switching cpus
-info: Entering event queue @ 2532860067500. Starting simulation...
+info: Entering event queue @ 2535698920000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2533860067500. Starting simulation...
+info: Entering event queue @ 2536698920000. Starting simulation...
switching cpus
-info: Entering event queue @ 2533860795000. Starting simulation...
+info: Entering event queue @ 2536698927500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2534860795000. Starting simulation...
-info: Entering event queue @ 2535576589000. Starting simulation...
+info: Entering event queue @ 2537698927500. Starting simulation...
switching cpus
-info: Entering event queue @ 2535576591000. Starting simulation...
+info: Entering event queue @ 2537698997000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2536576591000. Starting simulation...
+info: Entering event queue @ 2538698997000. Starting simulation...
+info: Entering event queue @ 2538699007500. Starting simulation...
+info: Entering event queue @ 2538699018000. Starting simulation...
switching cpus
-info: Entering event queue @ 2536576653000. Starting simulation...
+info: Entering event queue @ 2538699018500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2537576653000. Starting simulation...
+info: Entering event queue @ 2539699018500. Starting simulation...
+info: Entering event queue @ 2539704793500. Starting simulation...
+info: Entering event queue @ 2539704800000. Starting simulation...
switching cpus
-info: Entering event queue @ 2537576734500. Starting simulation...
+info: Entering event queue @ 2539704804500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2538576734500. Starting simulation...
-info: Entering event queue @ 2538576753000. Starting simulation...
+info: Entering event queue @ 2540704804500. Starting simulation...
switching cpus
-info: Entering event queue @ 2538576817500. Starting simulation...
+info: Entering event queue @ 2540704925000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2539576817500. Starting simulation...
-info: Entering event queue @ 2539576829500. Starting simulation...
+info: Entering event queue @ 2541704925000. Starting simulation...
+info: Entering event queue @ 2541705319000. Starting simulation...
switching cpus
-info: Entering event queue @ 2539576834000. Starting simulation...
+info: Entering event queue @ 2541705326500. Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2542705326500. Starting simulation...
+switching cpus
+info: Entering event queue @ 2542705334000. Starting simulation...
---------- Begin Simulation Statistics ----------
-sim_seconds 2.541275 # Number of seconds simulated
-sim_ticks 2541275479000 # Number of ticks simulated
-final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.543226 # Number of seconds simulated
+sim_ticks 2543226083000 # Number of ticks simulated
+final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 58368 # Simulator instruction rate (inst/s)
-host_op_rate 75104 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2459458086 # Simulator tick rate (ticks/s)
-host_mem_usage 437960 # Number of bytes of host memory used
-host_seconds 1033.27 # Real time elapsed on the host
-sim_insts 60310144 # Number of instructions simulated
-sim_ops 77602537 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 24298 # Simulator instruction rate (inst/s)
+host_op_rate 31265 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1024641665 # Simulator tick rate (ticks/s)
+host_mem_usage 442376 # Number of bytes of host memory used
+host_seconds 2482.06 # Real time elapsed on the host
+sim_insts 60309820 # Number of instructions simulated
+sim_ops 77602107 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 511168 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4147472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 290304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4947228 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131010156 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 511168 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 290304 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 801472 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3787712 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6803824 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 7987 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 64838 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4536 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 77307 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293538 # Number of read requests responded to by this memory
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+system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813211 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293480 # Total number of read requests seen
-system.physmem.writeReqs 813178 # Total number of write requests seen
-system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 978782720 # Total number of bytes read from memory
-system.physmem.bytesWritten 52043392 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed
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-system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis
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+system.physmem.readReqs 15293538 # Total number of read requests seen
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+system.physmem.bytesConsumedWr 6803824 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed
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system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis
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-system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2541274319500 # Total gap between requests
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+system.physmem.totGap 2543224928500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 43 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154621 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754028 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59150 # Categorize write packet sizes
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system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see
-system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests
-system.physmem.totBusLat 76467350000 # Total cycles spent in databus access
-system.physmem.totBankLat 16704696250 # Total cycles spent in bank access
-system.physmem.avgQLat 22669.51 # Average queueing delay per request
-system.physmem.avgBankLat 1092.28 # Average bank access latency per request
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+system.physmem.wrQLenPdf::31 32479 # What write queue length does an incoming req see
+system.physmem.totQLat 346835420750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 440002912000 # Sum of mem lat for all requests
+system.physmem.totBusLat 76467635000 # Total cycles spent in databus access
+system.physmem.totBankLat 16699856250 # Total cycles spent in bank access
+system.physmem.avgQLat 22678.58 # Average queueing delay per request
+system.physmem.avgBankLat 1091.96 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28761.78 # Average memory access latency
-system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 28770.53 # Average memory access latency
+system.physmem.avgRdBW 384.86 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 1.12 # Average write queue length over time
-system.physmem.readRowHits 15218335 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794661 # Number of row buffer hits during writes
+system.physmem.readRowHits 15218407 # Number of row buffer hits during reads
+system.physmem.writeRowHits 794595 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes
-system.physmem.avgGap 157777.88 # Average gap between requests
-system.l2c.replacements 64389 # number of replacements
-system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use
-system.l2c.total_refs 1903765 # Total number of references to valid blocks.
-system.l2c.sampled_refs 129779 # Sample count of references to valid blocks.
-system.l2c.avg_refs 14.669284 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor
+system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes
+system.physmem.avgGap 157898.09 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 7621777 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits
+system.cpu0.branchPred.lookups 7719049 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 6144205 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 388400 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 5016002 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 4082948 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.398452 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 737953 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 39729 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 26065013 # DTB read hits
-system.cpu0.dtb.read_misses 39990 # DTB read misses
-system.cpu0.dtb.write_hits 5895229 # DTB write hits
-system.cpu0.dtb.write_misses 9395 # DTB write misses
+system.cpu0.dtb.read_hits 26145640 # DTB read hits
+system.cpu0.dtb.read_misses 41213 # DTB read misses
+system.cpu0.dtb.write_hits 5906110 # DTB write hits
+system.cpu0.dtb.write_misses 9202 # DTB write misses
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 5753 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1471 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 26105003 # DTB read accesses
-system.cpu0.dtb.write_accesses 5904624 # DTB write accesses
+system.cpu0.dtb.perms_faults 691 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 26186853 # DTB read accesses
+system.cpu0.dtb.write_accesses 5915312 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31960242 # DTB hits
-system.cpu0.dtb.misses 49385 # DTB misses
-system.cpu0.dtb.accesses 32009627 # DTB accesses
-system.cpu0.itb.inst_hits 6121620 # ITB inst hits
-system.cpu0.itb.inst_misses 7590 # ITB inst misses
+system.cpu0.dtb.hits 32051750 # DTB hits
+system.cpu0.dtb.misses 50415 # DTB misses
+system.cpu0.dtb.accesses 32102165 # DTB accesses
+system.cpu0.itb.inst_hits 6183534 # ITB inst hits
+system.cpu0.itb.inst_misses 7751 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2745 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses
-system.cpu0.itb.hits 6121620 # DTB hits
-system.cpu0.itb.misses 7590 # DTB misses
-system.cpu0.itb.accesses 6129210 # DTB accesses
-system.cpu0.numCycles 238950356 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 6191285 # ITB inst accesses
+system.cpu0.itb.hits 6183534 # DTB hits
+system.cpu0.itb.misses 7751 # DTB misses
+system.cpu0.itb.accesses 6191285 # DTB accesses
+system.cpu0.numCycles 239079415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15644570 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 48338125 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7719049 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4820901 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10703205 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2596540 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 94746 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 49591987 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1964 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 53331 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 101492 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6181495 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 400642 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3259 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77992242 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.765373 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.123716 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 67296980 86.29% 86.29% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 702662 0.90% 87.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 892389 1.14% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1243235 1.59% 89.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1139067 1.46% 91.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 581520 0.75% 92.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1338462 1.72% 93.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 402047 0.52% 94.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4395880 5.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77992242 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.032287 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.202184 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16701716 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49328258 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9693840 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 556609 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1709696 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1049154 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 91765 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 56812427 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 306906 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1709696 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17642458 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 18978880 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 27077809 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9239108 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3342271 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 53967560 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 13437 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 629408 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2165949 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 513 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 56184131 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 245540949 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 245492809 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 48140 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 40778039 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 15406092 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 434005 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 385260 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6805574 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10494917 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6795022 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1080492 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1313371 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 50078322 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1031134 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 63522685 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 99823 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10628436 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26923896 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 250828 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77992242 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.814474 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.519995 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 55011307 70.53% 70.53% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 7277871 9.33% 79.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3728534 4.78% 84.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3132981 4.02% 88.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6315907 8.10% 96.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1400012 1.80% 98.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 822343 1.05% 99.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 235239 0.30% 99.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 68048 0.09% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77992242 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 33040 0.74% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 3 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4225834 94.61% 95.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 207543 4.65% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 193689 0.30% 0.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 30176884 47.51% 47.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 47977 0.08% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1219 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26869653 42.30% 90.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6233244 9.81% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued
-system.cpu0.iq.rate 0.264557 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 63522685 # Type of FU issued
+system.cpu0.iq.rate 0.265697 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4466420 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.070312 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 209641938 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 61746831 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 44505201 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12130 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6615 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5501 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 67789033 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6383 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 329345 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2321629 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3668 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16120 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 899548 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17127140 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 367757 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1709696 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 14213295 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 236264 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 51235944 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 105063 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10494917 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6795022 # Number of dispatched store instructions
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+system.cpu0.iew.iewIQFullEvents 58301 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3691 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16120 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 190260 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 151203 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 341463 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 62339008 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26506413 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1183677 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 117042 # number of nop insts executed
-system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 6029174 # Number of branches executed
-system.cpu0.iew.exec_stores 6166956 # Number of stores executed
-system.cpu0.iew.exec_rate 0.259636 # Inst execution rate
-system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24341972 # num instructions producing a value
-system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value
+system.cpu0.iew.exec_nop 126488 # number of nop insts executed
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+system.cpu0.iew.exec_branches 6088882 # Number of branches executed
+system.cpu0.iew.exec_stores 6176077 # Number of stores executed
+system.cpu0.iew.exec_rate 0.260746 # Inst execution rate
+system.cpu0.iew.wb_sent 61801058 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 44510702 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24520944 # num instructions producing a value
+system.cpu0.iew.wb_consumers 44899908 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.186175 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.546125 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 10516243 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 780306 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 297973 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 76282546 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.527732 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.509463 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 61930092 81.19% 81.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6958991 9.12% 90.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2075873 2.72% 93.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1156776 1.52% 94.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1044437 1.37% 95.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 552027 0.72% 96.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 702446 0.92% 97.56% # Number of insts commited each cycle
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system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13560.452775 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13571.458702 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13565.254696 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33092.358985 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34643.924773 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33901.937429 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.836585 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.417227 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11942.613543 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7016100 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits
+system.cpu1.branchPred.lookups 6924581 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5562771 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 336228 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4476731 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3769892 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 84.210823 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 665809 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 34604 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25297638 # DTB read hits
-system.cpu1.dtb.read_misses 36209 # DTB read misses
-system.cpu1.dtb.write_hits 5817747 # DTB write hits
-system.cpu1.dtb.write_misses 9250 # DTB write misses
+system.cpu1.dtb.read_hits 25217799 # DTB read hits
+system.cpu1.dtb.read_misses 35648 # DTB read misses
+system.cpu1.dtb.write_hits 5810779 # DTB write hits
+system.cpu1.dtb.write_misses 9529 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 5398 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1388 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25333847 # DTB read accesses
-system.cpu1.dtb.write_accesses 5826997 # DTB write accesses
+system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25253447 # DTB read accesses
+system.cpu1.dtb.write_accesses 5820308 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31115385 # DTB hits
-system.cpu1.dtb.misses 45459 # DTB misses
-system.cpu1.dtb.accesses 31160844 # DTB accesses
-system.cpu1.itb.inst_hits 5983825 # ITB inst hits
-system.cpu1.itb.inst_misses 6876 # ITB inst misses
+system.cpu1.dtb.hits 31028578 # DTB hits
+system.cpu1.dtb.misses 45177 # DTB misses
+system.cpu1.dtb.accesses 31073755 # DTB accesses
+system.cpu1.itb.inst_hits 5925943 # ITB inst hits
+system.cpu1.itb.inst_misses 6573 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2476 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1382 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses
-system.cpu1.itb.hits 5983825 # DTB hits
-system.cpu1.itb.misses 6876 # DTB misses
-system.cpu1.itb.accesses 5990701 # DTB accesses
-system.cpu1.numCycles 234271094 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5932516 # ITB inst accesses
+system.cpu1.itb.hits 5925943 # DTB hits
+system.cpu1.itb.misses 6573 # DTB misses
+system.cpu1.itb.accesses 5932516 # DTB accesses
+system.cpu1.numCycles 234244847 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 15045426 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 46051404 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 6924581 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4435701 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10180178 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2576164 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 79323 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 47488838 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 962 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 40665 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 94257 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 230 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5924019 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 441347 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 74691954 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.768024 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.131487 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 64519001 86.38% 86.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 606919 0.81% 87.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 824654 1.10% 88.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1190723 1.59% 89.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1057088 1.42% 91.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 528345 0.71% 92.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1354186 1.81% 93.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 346670 0.46% 94.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4264368 5.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 74691954 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.029561 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.196595 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 16048040 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 47278235 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9237318 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 448383 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1677844 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 921418 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 84751 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 54328734 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 282420 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1677844 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 16980429 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 18581446 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 25685933 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8674589 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3089642 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51185611 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 7172 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 483859 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2112197 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 97 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 53156547 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 235159359 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 235117285 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 42074 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 37614805 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15541741 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 399062 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 353498 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6213195 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9696990 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6683769 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 865241 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1058674 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47161259 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 954916 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 60450494 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 77232 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10409443 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 27466585 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 252722 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 74691954 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.809331 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.520957 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 53120438 71.12% 71.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6581682 8.81% 79.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3495899 4.68% 84.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2849080 3.81% 88.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6224305 8.33% 96.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1417719 1.90% 98.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 735156 0.98% 99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 208377 0.28% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 59298 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 74691954 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 25658 0.59% 0.59% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.59% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.59% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4148051 94.78% 95.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 202723 4.63% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 169977 0.28% 0.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 28184247 46.62% 46.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45636 0.08% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 892 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 25945360 42.92% 89.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6104366 10.10% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued
-system.cpu1.iq.rate 0.259266 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 60450494 # Type of FU issued
+system.cpu1.iq.rate 0.258065 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4376432 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.072397 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 200080953 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 58533998 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 41393677 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 10638 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 5781 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4780 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 64651317 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 5632 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 296486 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2215043 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3144 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 14677 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 846684 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16976661 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 457892 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1677844 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 14002380 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 233104 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48212114 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 96608 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9696990 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6683769 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 685390 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 50588 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3685 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 14677 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 163070 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 129112 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 292182 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59083319 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25544592 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1367175 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105670 # number of nop insts executed
-system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5509079 # Number of branches executed
-system.cpu1.iew.exec_stores 6058244 # Number of stores executed
-system.cpu1.iew.exec_rate 0.253403 # Inst execution rate
-system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 22722145 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value
+system.cpu1.iew.exec_nop 95939 # number of nop insts executed
+system.cpu1.iew.exec_refs 31597721 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5452623 # Number of branches executed
+system.cpu1.iew.exec_stores 6053129 # Number of stores executed
+system.cpu1.iew.exec_rate 0.252229 # Inst execution rate
+system.cpu1.iew.wb_sent 58512296 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41398457 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 22553116 # num instructions producing a value
+system.cpu1.iew.wb_consumers 41520902 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.176732 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.543175 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 10281991 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 702194 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 252752 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 73014110 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.513541 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.493879 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 59627220 81.67% 81.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6596697 9.03% 90.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1882997 2.58% 93.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 995941 1.36% 94.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 953813 1.31% 95.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 518436 0.71% 96.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 701051 0.96% 97.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 372117 0.51% 98.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1365838 1.87% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 29131232 # Number of instructions committed
-system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 73014110 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 28855252 # Number of instructions committed
+system.cpu1.commit.committedOps 37495775 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13400454 # Number of memory references committed
-system.cpu1.commit.loads 7561112 # Number of loads committed
-system.cpu1.commit.membars 191037 # Number of memory barriers committed
-system.cpu1.commit.branches 4747981 # Number of branches committed
-system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 476457 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 13319032 # Number of memory references committed
+system.cpu1.commit.loads 7481947 # Number of loads committed
+system.cpu1.commit.membars 189014 # Number of memory barriers committed
+system.cpu1.commit.branches 4694468 # Number of branches committed
+system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33309565 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 473164 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1365838 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 119155388 # The number of ROB reads
-system.cpu1.rob.rob_writes 98129561 # The number of ROB writes
-system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 29060294 # Number of Instructions Simulated
-system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated
-system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads
-system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes
+system.cpu1.rob.rob_reads 118557028 # The number of ROB reads
+system.cpu1.rob.rob_writes 97285221 # The number of ROB writes
+system.cpu1.timesIdled 872406 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 159552893 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2285658129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 28790724 # Number of Instructions Simulated
+system.cpu1.committedOps 37431247 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 28790724 # Number of Instructions Simulated
+system.cpu1.cpi 8.136122 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 8.136122 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.122909 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.122909 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 267548470 # number of integer regfile reads
+system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 14600078 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1192831582801 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1192831582801 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
-dtb_filename=
+dtb_filename=False
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 22:22:22
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:56:16
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second
Next CPU: TimingSimpleCPU
info: Entering event queue @ 1000000000. Starting simulation...
switching cpus
-info: Entering event queue @ 1000161000. Starting simulation...
+info: Entering event queue @ 1000020000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2000161000. Starting simulation...
+info: Entering event queue @ 2000020000. Starting simulation...
switching cpus
-info: Entering event queue @ 2000162000. Starting simulation...
+info: Entering event queue @ 2000027500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3000162000. Starting simulation...
+info: Entering event queue @ 3000027500. Starting simulation...
switching cpus
-info: Entering event queue @ 3000209500. Starting simulation...
+info: Entering event queue @ 3000051500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 4000209500. Starting simulation...
+info: Entering event queue @ 4000051500. Starting simulation...
switching cpus
-info: Entering event queue @ 4000253500. Starting simulation...
+info: Entering event queue @ 4000072500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5000253500. Starting simulation...
+info: Entering event queue @ 5000072500. Starting simulation...
switching cpus
-info: Entering event queue @ 5000254500. Starting simulation...
+info: Entering event queue @ 5000073000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 6000254500. Starting simulation...
+info: Entering event queue @ 6000073000. Starting simulation...
switching cpus
-info: Entering event queue @ 6000255500. Starting simulation...
+info: Entering event queue @ 6000074000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 7000255500. Starting simulation...
+info: Entering event queue @ 7000074000. Starting simulation...
switching cpus
-info: Entering event queue @ 7000257500. Starting simulation...
+info: Entering event queue @ 7000075000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 8000257500. Starting simulation...
+info: Entering event queue @ 8000075000. Starting simulation...
switching cpus
-info: Entering event queue @ 8000258500. Starting simulation...
+info: Entering event queue @ 8000075500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 9000258500. Starting simulation...
+info: Entering event queue @ 9000075500. Starting simulation...
switching cpus
-info: Entering event queue @ 9000473000. Starting simulation...
+info: Entering event queue @ 9000211000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 10000473000. Starting simulation...
+info: Entering event queue @ 10000211000. Starting simulation...
switching cpus
-info: Entering event queue @ 10000475000. Starting simulation...
+info: Entering event queue @ 10000212000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 11000475000. Starting simulation...
+info: Entering event queue @ 11000212000. Starting simulation...
switching cpus
-info: Entering event queue @ 11000476000. Starting simulation...
+info: Entering event queue @ 11000212500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 12000476000. Starting simulation...
+info: Entering event queue @ 12000212500. Starting simulation...
switching cpus
-info: Entering event queue @ 12000477500. Starting simulation...
+info: Entering event queue @ 12000213500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 13000477500. Starting simulation...
+info: Entering event queue @ 13000213500. Starting simulation...
switching cpus
-info: Entering event queue @ 13000479500. Starting simulation...
+info: Entering event queue @ 13000214500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 14000479500. Starting simulation...
+info: Entering event queue @ 14000214500. Starting simulation...
+info: Entering event queue @ 14000227000. Starting simulation...
switching cpus
-info: Entering event queue @ 14000481500. Starting simulation...
+info: Entering event queue @ 14000228500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 15000481500. Starting simulation...
+info: Entering event queue @ 15000228500. Starting simulation...
switching cpus
-info: Entering event queue @ 15000483500. Starting simulation...
+info: Entering event queue @ 15000236000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 16000483500. Starting simulation...
+info: Entering event queue @ 16000236000. Starting simulation...
+info: Entering event queue @ 16000253000. Starting simulation...
switching cpus
-info: Entering event queue @ 16000485500. Starting simulation...
+info: Entering event queue @ 16000256500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 17000485500. Starting simulation...
+info: Entering event queue @ 17000256500. Starting simulation...
switching cpus
-info: Entering event queue @ 17000486500. Starting simulation...
+info: Entering event queue @ 17000257000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 18000486500. Starting simulation...
-info: Entering event queue @ 18000493500. Starting simulation...
+info: Entering event queue @ 18000257000. Starting simulation...
switching cpus
-info: Entering event queue @ 18000496000. Starting simulation...
+info: Entering event queue @ 18000264500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 19000496000. Starting simulation...
+info: Entering event queue @ 19000264500. Starting simulation...
+info: Entering event queue @ 19000274500. Starting simulation...
switching cpus
-info: Entering event queue @ 19000497000. Starting simulation...
+info: Entering event queue @ 19000277000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 20000497000. Starting simulation...
+info: Entering event queue @ 20000277000. Starting simulation...
switching cpus
-info: Entering event queue @ 20000498000. Starting simulation...
+info: Entering event queue @ 20000284500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 21000498000. Starting simulation...
-info: Entering event queue @ 21000511500. Starting simulation...
+info: Entering event queue @ 21000284500. Starting simulation...
switching cpus
-info: Entering event queue @ 21000513000. Starting simulation...
+info: Entering event queue @ 21000285500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 22000513000. Starting simulation...
-info: Entering event queue @ 22000516500. Starting simulation...
+info: Entering event queue @ 22000285500. Starting simulation...
switching cpus
-info: Entering event queue @ 22000518000. Starting simulation...
+info: Entering event queue @ 22000293000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 23000518000. Starting simulation...
+info: Entering event queue @ 23000293000. Starting simulation...
+info: Entering event queue @ 23000303000. Starting simulation...
switching cpus
-info: Entering event queue @ 23000519000. Starting simulation...
+info: Entering event queue @ 23000304500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 24000519000. Starting simulation...
+info: Entering event queue @ 24000304500. Starting simulation...
switching cpus
-info: Entering event queue @ 24000634000. Starting simulation...
+info: Entering event queue @ 24000312000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 25000634000. Starting simulation...
-info: Entering event queue @ 25000647000. Starting simulation...
+info: Entering event queue @ 25000312000. Starting simulation...
switching cpus
-info: Entering event queue @ 25000650500. Starting simulation...
+info: Entering event queue @ 25000319500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 26000650500. Starting simulation...
-info: Entering event queue @ 26000657000. Starting simulation...
+info: Entering event queue @ 26000319500. Starting simulation...
switching cpus
-info: Entering event queue @ 26000658500. Starting simulation...
+info: Entering event queue @ 26000327000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 27000658500. Starting simulation...
-info: Entering event queue @ 27000664500. Starting simulation...
+info: Entering event queue @ 27000327000. Starting simulation...
switching cpus
-info: Entering event queue @ 27000667000. Starting simulation...
+info: Entering event queue @ 27000334500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 28000667000. Starting simulation...
+info: Entering event queue @ 28000334500. Starting simulation...
switching cpus
-info: Entering event queue @ 28000668000. Starting simulation...
+info: Entering event queue @ 28000342000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 29000668000. Starting simulation...
+info: Entering event queue @ 29000342000. Starting simulation...
+info: Entering event queue @ 29000349500. Starting simulation...
switching cpus
-info: Entering event queue @ 29000669000. Starting simulation...
+info: Entering event queue @ 29000351500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 30000669000. Starting simulation...
+info: Entering event queue @ 30000351500. Starting simulation...
switching cpus
-info: Entering event queue @ 30000671000. Starting simulation...
+info: Entering event queue @ 30000359000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 31000671000. Starting simulation...
-info: Entering event queue @ 31000679500. Starting simulation...
+info: Entering event queue @ 31000359000. Starting simulation...
switching cpus
-info: Entering event queue @ 31000682000. Starting simulation...
+info: Entering event queue @ 31000366500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 32000682000. Starting simulation...
+info: Entering event queue @ 32000366500. Starting simulation...
switching cpus
-info: Entering event queue @ 32000683000. Starting simulation...
+info: Entering event queue @ 32000374000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 33000683000. Starting simulation...
+info: Entering event queue @ 33000374000. Starting simulation...
switching cpus
-info: Entering event queue @ 33000684000. Starting simulation...
+info: Entering event queue @ 33000406500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 34000684000. Starting simulation...
+info: Entering event queue @ 34000406500. Starting simulation...
switching cpus
-info: Entering event queue @ 34000685000. Starting simulation...
+info: Entering event queue @ 34000414000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 35000685000. Starting simulation...
-info: Entering event queue @ 35000871500. Starting simulation...
+info: Entering event queue @ 35000414000. Starting simulation...
+info: Entering event queue @ 35000437500. Starting simulation...
switching cpus
-info: Entering event queue @ 35000872500. Starting simulation...
+info: Entering event queue @ 35000654750. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 36000872500. Starting simulation...
+info: Entering event queue @ 36000654750. Starting simulation...
switching cpus
-info: Entering event queue @ 36000875000. Starting simulation...
+info: Entering event queue @ 36000663500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37000875000. Starting simulation...
+info: Entering event queue @ 37000663500. Starting simulation...
switching cpus
-info: Entering event queue @ 37001097000. Starting simulation...
+info: Entering event queue @ 37000671000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 38001097000. Starting simulation...
+info: Entering event queue @ 38000671000. Starting simulation...
switching cpus
-info: Entering event queue @ 38001098000. Starting simulation...
+info: Entering event queue @ 38000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 39001098000. Starting simulation...
+info: Entering event queue @ 39000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 40001098000. Starting simulation...
+info: Entering event queue @ 40000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 41001098000. Starting simulation...
+info: Entering event queue @ 41000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 42001098000. Starting simulation...
+info: Entering event queue @ 42000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 43001098000. Starting simulation...
+info: Entering event queue @ 43000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 44001098000. Starting simulation...
+info: Entering event queue @ 44000678500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 45001098000. Starting simulation...
+info: Entering event queue @ 45000678500. Starting simulation...
switching cpus
-info: Entering event queue @ 45001099000. Starting simulation...
+info: Entering event queue @ 45000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 46001099000. Starting simulation...
+info: Entering event queue @ 46000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 47001099000. Starting simulation...
+info: Entering event queue @ 47000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 48001099000. Starting simulation...
+info: Entering event queue @ 48000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 49001099000. Starting simulation...
+info: Entering event queue @ 49000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 50001099000. Starting simulation...
+info: Entering event queue @ 50000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 51001099000. Starting simulation...
+info: Entering event queue @ 51000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 52001099000. Starting simulation...
+info: Entering event queue @ 52000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 53001099000. Starting simulation...
+info: Entering event queue @ 53000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 54001099000. Starting simulation...
+info: Entering event queue @ 54000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 55001099000. Starting simulation...
+info: Entering event queue @ 55000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 56001099000. Starting simulation...
+info: Entering event queue @ 56000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 57001099000. Starting simulation...
+info: Entering event queue @ 57000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 58001099000. Starting simulation...
+info: Entering event queue @ 58000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 59001099000. Starting simulation...
+info: Entering event queue @ 59000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 60001099000. Starting simulation...
+info: Entering event queue @ 60000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 61001099000. Starting simulation...
+info: Entering event queue @ 61000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 62001099000. Starting simulation...
+info: Entering event queue @ 62000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 63001099000. Starting simulation...
+info: Entering event queue @ 63000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 64001099000. Starting simulation...
+info: Entering event queue @ 64000686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 65001099000. Starting simulation...
-info: Entering event queue @ 66306421000. Starting simulation...
+info: Entering event queue @ 65000686000. Starting simulation...
+info: Entering event queue @ 66499718000. Starting simulation...
switching cpus
-info: Entering event queue @ 66306423000. Starting simulation...
+info: Entering event queue @ 66499720000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 67306423000. Starting simulation...
+info: Entering event queue @ 67499720000. Starting simulation...
switching cpus
-info: Entering event queue @ 67306432500. Starting simulation...
+info: Entering event queue @ 67499727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 68306432500. Starting simulation...
+info: Entering event queue @ 68499727500. Starting simulation...
switching cpus
-info: Entering event queue @ 68306442500. Starting simulation...
+info: Entering event queue @ 68499737500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 69306442500. Starting simulation...
+info: Entering event queue @ 69499737500. Starting simulation...
switching cpus
-info: Entering event queue @ 69306452500. Starting simulation...
+info: Entering event queue @ 69499745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 70306452500. Starting simulation...
+info: Entering event queue @ 70499745000. Starting simulation...
switching cpus
-info: Entering event queue @ 70306453500. Starting simulation...
+info: Entering event queue @ 70499751500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 71306453500. Starting simulation...
+info: Entering event queue @ 71499751500. Starting simulation...
+info: Entering event queue @ 71499768500. Starting simulation...
switching cpus
-info: Entering event queue @ 71306514500. Starting simulation...
+info: Entering event queue @ 71499859000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 72306514500. Starting simulation...
+info: Entering event queue @ 72499859000. Starting simulation...
+info: Entering event queue @ 72499881500. Starting simulation...
switching cpus
-info: Entering event queue @ 72306516500. Starting simulation...
+info: Entering event queue @ 72499991500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 73306516500. Starting simulation...
+info: Entering event queue @ 73499991500. Starting simulation...
switching cpus
-info: Entering event queue @ 73306518500. Starting simulation...
+info: Entering event queue @ 73500001500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 74306518500. Starting simulation...
+info: Entering event queue @ 74500001500. Starting simulation...
+info: Entering event queue @ 74500025500. Starting simulation...
switching cpus
-info: Entering event queue @ 74306519500. Starting simulation...
+info: Entering event queue @ 74500109000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 75306519500. Starting simulation...
+info: Entering event queue @ 75500109000. Starting simulation...
switching cpus
-info: Entering event queue @ 75306520500. Starting simulation...
+info: Entering event queue @ 75500119500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 76306520500. Starting simulation...
-info: Entering event queue @ 76306542500. Starting simulation...
+info: Entering event queue @ 76500119500. Starting simulation...
switching cpus
-info: Entering event queue @ 76306583500. Starting simulation...
+info: Entering event queue @ 76500120500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 77306583500. Starting simulation...
+info: Entering event queue @ 77500120500. Starting simulation...
switching cpus
-info: Entering event queue @ 77306585500. Starting simulation...
+info: Entering event queue @ 77500128000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 78306585500. Starting simulation...
+info: Entering event queue @ 78500128000. Starting simulation...
switching cpus
-info: Entering event queue @ 78306586500. Starting simulation...
+info: Entering event queue @ 78500135500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 79306586500. Starting simulation...
+info: Entering event queue @ 79500135500. Starting simulation...
switching cpus
-info: Entering event queue @ 79306587500. Starting simulation...
+info: Entering event queue @ 79500143000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 80306587500. Starting simulation...
+info: Entering event queue @ 80500143000. Starting simulation...
switching cpus
-info: Entering event queue @ 80306589500. Starting simulation...
+info: Entering event queue @ 80500143500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 81306589500. Starting simulation...
-info: Entering event queue @ 81306614500. Starting simulation...
+info: Entering event queue @ 81500143500. Starting simulation...
switching cpus
-info: Entering event queue @ 81306676500. Starting simulation...
+info: Entering event queue @ 81500151000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 82306676500. Starting simulation...
-info: Entering event queue @ 82306698500. Starting simulation...
+info: Entering event queue @ 82500151000. Starting simulation...
switching cpus
-info: Entering event queue @ 82306739500. Starting simulation...
+info: Entering event queue @ 82500158500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 83306739500. Starting simulation...
+info: Entering event queue @ 83500158500. Starting simulation...
switching cpus
-info: Entering event queue @ 83306740500. Starting simulation...
+info: Entering event queue @ 83500166000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 84306740500. Starting simulation...
+info: Entering event queue @ 84500166000. Starting simulation...
switching cpus
-info: Entering event queue @ 84306741500. Starting simulation...
+info: Entering event queue @ 84500180500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 85306741500. Starting simulation...
+info: Entering event queue @ 85500180500. Starting simulation...
switching cpus
-info: Entering event queue @ 85306742500. Starting simulation...
+info: Entering event queue @ 85500229000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 86306742500. Starting simulation...
+info: Entering event queue @ 86500229000. Starting simulation...
switching cpus
-info: Entering event queue @ 86306743500. Starting simulation...
+info: Entering event queue @ 86500236500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 87306743500. Starting simulation...
-info: Entering event queue @ 87306763500. Starting simulation...
+info: Entering event queue @ 87500236500. Starting simulation...
switching cpus
-info: Entering event queue @ 87306822500. Starting simulation...
+info: Entering event queue @ 87500244000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 88306822500. Starting simulation...
+info: Entering event queue @ 88500244000. Starting simulation...
switching cpus
-info: Entering event queue @ 88306823500. Starting simulation...
+info: Entering event queue @ 88500251500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 89306823500. Starting simulation...
+info: Entering event queue @ 89500251500. Starting simulation...
switching cpus
-info: Entering event queue @ 89306824500. Starting simulation...
+info: Entering event queue @ 89500259000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 90306824500. Starting simulation...
-info: Entering event queue @ 90306840500. Starting simulation...
+info: Entering event queue @ 90500259000. Starting simulation...
switching cpus
-info: Entering event queue @ 90306899500. Starting simulation...
+info: Entering event queue @ 90500266500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 91306899500. Starting simulation...
+info: Entering event queue @ 91500266500. Starting simulation...
switching cpus
-info: Entering event queue @ 91306906500. Starting simulation...
+info: Entering event queue @ 91500274000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 92306906500. Starting simulation...
+info: Entering event queue @ 92500274000. Starting simulation...
switching cpus
-info: Entering event queue @ 92306907500. Starting simulation...
+info: Entering event queue @ 92500281500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 93306907500. Starting simulation...
+info: Entering event queue @ 93500281500. Starting simulation...
switching cpus
-info: Entering event queue @ 93306908500. Starting simulation...
+info: Entering event queue @ 93500292500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 94306908500. Starting simulation...
+info: Entering event queue @ 94500292500. Starting simulation...
+info: Entering event queue @ 94500313500. Starting simulation...
switching cpus
-info: Entering event queue @ 94306931500. Starting simulation...
+info: Entering event queue @ 94500420000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 95306931500. Starting simulation...
+info: Entering event queue @ 95500420000. Starting simulation...
switching cpus
-info: Entering event queue @ 95306933500. Starting simulation...
+info: Entering event queue @ 95500427500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 96306933500. Starting simulation...
+info: Entering event queue @ 96500427500. Starting simulation...
switching cpus
-info: Entering event queue @ 96307006500. Starting simulation...
+info: Entering event queue @ 96500441500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 97307006500. Starting simulation...
-info: Entering event queue @ 97307011500. Starting simulation...
+info: Entering event queue @ 97500441500. Starting simulation...
+info: Entering event queue @ 97500449000. Starting simulation...
switching cpus
-info: Entering event queue @ 97307013000. Starting simulation...
+info: Entering event queue @ 97500450000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 98307013000. Starting simulation...
-info: Entering event queue @ 99022063000. Starting simulation...
+info: Entering event queue @ 98500450000. Starting simulation...
+info: Entering event queue @ 99219551000. Starting simulation...
switching cpus
-info: Entering event queue @ 99022065000. Starting simulation...
+info: Entering event queue @ 99219553000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 100022065000. Starting simulation...
+info: Entering event queue @ 100219553000. Starting simulation...
switching cpus
-info: Entering event queue @ 100022065500. Starting simulation...
+info: Entering event queue @ 100219553500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 101022065500. Starting simulation...
+info: Entering event queue @ 101219553500. Starting simulation...
switching cpus
-info: Entering event queue @ 101022067500. Starting simulation...
+info: Entering event queue @ 101219554000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 102022067500. Starting simulation...
+info: Entering event queue @ 102219554000. Starting simulation...
switching cpus
-info: Entering event queue @ 102022068500. Starting simulation...
+info: Entering event queue @ 102219560000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 103022068500. Starting simulation...
+info: Entering event queue @ 103219560000. Starting simulation...
switching cpus
-info: Entering event queue @ 103022072000. Starting simulation...
+info: Entering event queue @ 103219562000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 104022072000. Starting simulation...
+info: Entering event queue @ 104219562000. Starting simulation...
switching cpus
-info: Entering event queue @ 104022073000. Starting simulation...
+info: Entering event queue @ 104219563000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 105022073000. Starting simulation...
+info: Entering event queue @ 105219563000. Starting simulation...
switching cpus
-info: Entering event queue @ 105022074500. Starting simulation...
+info: Entering event queue @ 105219565000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 106022074500. Starting simulation...
+info: Entering event queue @ 106219565000. Starting simulation...
switching cpus
-info: Entering event queue @ 106022075000. Starting simulation...
+info: Entering event queue @ 106219567000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 107022075000. Starting simulation...
-info: Entering event queue @ 107022087500. Starting simulation...
+info: Entering event queue @ 107219567000. Starting simulation...
switching cpus
-info: Entering event queue @ 107022090000. Starting simulation...
+info: Entering event queue @ 107219568000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 108022090000. Starting simulation...
+info: Entering event queue @ 108219568000. Starting simulation...
switching cpus
-info: Entering event queue @ 108022090500. Starting simulation...
+info: Entering event queue @ 108219614500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 109022090500. Starting simulation...
+info: Entering event queue @ 109219614500. Starting simulation...
switching cpus
-info: Entering event queue @ 109022092500. Starting simulation...
+info: Entering event queue @ 109219615500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 110022092500. Starting simulation...
-info: Entering event queue @ 110022099500. Starting simulation...
+info: Entering event queue @ 110219615500. Starting simulation...
+info: Entering event queue @ 110219625000. Starting simulation...
switching cpus
-info: Entering event queue @ 110022103000. Starting simulation...
+info: Entering event queue @ 110219627500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 111022103000. Starting simulation...
+info: Entering event queue @ 111219627500. Starting simulation...
switching cpus
-info: Entering event queue @ 111022104000. Starting simulation...
+info: Entering event queue @ 111219635000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 112219635000. Starting simulation...
switching cpus
-info: Entering event queue @ 112022104000. Starting simulation...
+info: Entering event queue @ 112219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 113022104000. Starting simulation...
+info: Entering event queue @ 113219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 114022104000. Starting simulation...
+info: Entering event queue @ 114219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 115022104000. Starting simulation...
+info: Entering event queue @ 115219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 116022104000. Starting simulation...
+info: Entering event queue @ 116219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 117022104000. Starting simulation...
+info: Entering event queue @ 117219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 118022104000. Starting simulation...
+info: Entering event queue @ 118219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 119022104000. Starting simulation...
+info: Entering event queue @ 119219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 120022104000. Starting simulation...
+info: Entering event queue @ 120219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 121022104000. Starting simulation...
+info: Entering event queue @ 121219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 122022104000. Starting simulation...
+info: Entering event queue @ 122219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 123022104000. Starting simulation...
+info: Entering event queue @ 123219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 124022104000. Starting simulation...
+info: Entering event queue @ 124219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 125022104000. Starting simulation...
+info: Entering event queue @ 125219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 126022104000. Starting simulation...
+info: Entering event queue @ 126219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 127022104000. Starting simulation...
+info: Entering event queue @ 127219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 128022104000. Starting simulation...
+info: Entering event queue @ 128219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 129022104000. Starting simulation...
+info: Entering event queue @ 129219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 130022104000. Starting simulation...
+info: Entering event queue @ 130219642500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 131022104000. Starting simulation...
-info: Entering event queue @ 131758663000. Starting simulation...
+info: Entering event queue @ 131219642500. Starting simulation...
+info: Entering event queue @ 131956130000. Starting simulation...
switching cpus
-info: Entering event queue @ 131758665000. Starting simulation...
+info: Entering event queue @ 131956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 132758665000. Starting simulation...
+info: Entering event queue @ 132956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 133758665000. Starting simulation...
+info: Entering event queue @ 133956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 134758665000. Starting simulation...
+info: Entering event queue @ 134956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 135758665000. Starting simulation...
+info: Entering event queue @ 135956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 136758665000. Starting simulation...
+info: Entering event queue @ 136956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 137758665000. Starting simulation...
+info: Entering event queue @ 137956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 138758665000. Starting simulation...
+info: Entering event queue @ 138956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 139758665000. Starting simulation...
+info: Entering event queue @ 139956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 140758665000. Starting simulation...
+info: Entering event queue @ 140956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 141758665000. Starting simulation...
+info: Entering event queue @ 141956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 142758665000. Starting simulation...
+info: Entering event queue @ 142956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 143758665000. Starting simulation...
+info: Entering event queue @ 143956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 144758665000. Starting simulation...
+info: Entering event queue @ 144956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 145758665000. Starting simulation...
+info: Entering event queue @ 145956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 146758665000. Starting simulation...
+info: Entering event queue @ 146956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 147758665000. Starting simulation...
+info: Entering event queue @ 147956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 148758665000. Starting simulation...
+info: Entering event queue @ 148956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 149758665000. Starting simulation...
+info: Entering event queue @ 149956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 150758665000. Starting simulation...
+info: Entering event queue @ 150956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 151758665000. Starting simulation...
+info: Entering event queue @ 151956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 152758665000. Starting simulation...
+info: Entering event queue @ 152956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 153758665000. Starting simulation...
+info: Entering event queue @ 153956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 154758665000. Starting simulation...
+info: Entering event queue @ 154956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 155758665000. Starting simulation...
+info: Entering event queue @ 155956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 156758665000. Starting simulation...
+info: Entering event queue @ 156956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 157758665000. Starting simulation...
+info: Entering event queue @ 157956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 158758665000. Starting simulation...
+info: Entering event queue @ 158956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 159758665000. Starting simulation...
+info: Entering event queue @ 159956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 160758665000. Starting simulation...
+info: Entering event queue @ 160956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 161758665000. Starting simulation...
+info: Entering event queue @ 161956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 162758665000. Starting simulation...
+info: Entering event queue @ 162956132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 163758665000. Starting simulation...
-info: Entering event queue @ 164494807000. Starting simulation...
+info: Entering event queue @ 163956132000. Starting simulation...
+info: Entering event queue @ 164692730000. Starting simulation...
switching cpus
-info: Entering event queue @ 164494809000. Starting simulation...
+info: Entering event queue @ 164692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 165494809000. Starting simulation...
+info: Entering event queue @ 165692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 166494809000. Starting simulation...
+info: Entering event queue @ 166692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 167494809000. Starting simulation...
+info: Entering event queue @ 167692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 168494809000. Starting simulation...
+info: Entering event queue @ 168692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 169494809000. Starting simulation...
+info: Entering event queue @ 169692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 170494809000. Starting simulation...
+info: Entering event queue @ 170692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 171494809000. Starting simulation...
+info: Entering event queue @ 171692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 172494809000. Starting simulation...
+info: Entering event queue @ 172692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 173494809000. Starting simulation...
+info: Entering event queue @ 173692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 174494809000. Starting simulation...
+info: Entering event queue @ 174692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 175494809000. Starting simulation...
+info: Entering event queue @ 175692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 176494809000. Starting simulation...
+info: Entering event queue @ 176692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 177494809000. Starting simulation...
+info: Entering event queue @ 177692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 178494809000. Starting simulation...
+info: Entering event queue @ 178692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 179494809000. Starting simulation...
+info: Entering event queue @ 179692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 180494809000. Starting simulation...
+info: Entering event queue @ 180692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 181494809000. Starting simulation...
+info: Entering event queue @ 181692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 182494809000. Starting simulation...
+info: Entering event queue @ 182692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 183494809000. Starting simulation...
+info: Entering event queue @ 183692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 184494809000. Starting simulation...
+info: Entering event queue @ 184692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 185494809000. Starting simulation...
+info: Entering event queue @ 185692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 186494809000. Starting simulation...
+info: Entering event queue @ 186692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 187494809000. Starting simulation...
+info: Entering event queue @ 187692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 188494809000. Starting simulation...
+info: Entering event queue @ 188692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 189494809000. Starting simulation...
+info: Entering event queue @ 189692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 190494809000. Starting simulation...
+info: Entering event queue @ 190692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 191494809000. Starting simulation...
+info: Entering event queue @ 191692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 192494809000. Starting simulation...
+info: Entering event queue @ 192692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 193494809000. Starting simulation...
+info: Entering event queue @ 193692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 194494809000. Starting simulation...
+info: Entering event queue @ 194692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 195494809000. Starting simulation...
+info: Entering event queue @ 195692732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 196494809000. Starting simulation...
-info: Entering event queue @ 197230954000. Starting simulation...
+info: Entering event queue @ 196692732000. Starting simulation...
+info: Entering event queue @ 197429351000. Starting simulation...
switching cpus
-info: Entering event queue @ 197230956000. Starting simulation...
+info: Entering event queue @ 197429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 198230956000. Starting simulation...
+info: Entering event queue @ 198429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 199230956000. Starting simulation...
+info: Entering event queue @ 199429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 200230956000. Starting simulation...
+info: Entering event queue @ 200429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 201230956000. Starting simulation...
+info: Entering event queue @ 201429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 202230956000. Starting simulation...
+info: Entering event queue @ 202429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 203230956000. Starting simulation...
+info: Entering event queue @ 203429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 204230956000. Starting simulation...
+info: Entering event queue @ 204429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 205230956000. Starting simulation...
+info: Entering event queue @ 205429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 206230956000. Starting simulation...
+info: Entering event queue @ 206429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 207230956000. Starting simulation...
+info: Entering event queue @ 207429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 208230956000. Starting simulation...
+info: Entering event queue @ 208429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 209230956000. Starting simulation...
+info: Entering event queue @ 209429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 210230956000. Starting simulation...
+info: Entering event queue @ 210429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 211230956000. Starting simulation...
+info: Entering event queue @ 211429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 212230956000. Starting simulation...
+info: Entering event queue @ 212429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 213230956000. Starting simulation...
+info: Entering event queue @ 213429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 214230956000. Starting simulation...
+info: Entering event queue @ 214429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 215230956000. Starting simulation...
+info: Entering event queue @ 215429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 216230956000. Starting simulation...
+info: Entering event queue @ 216429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 217230956000. Starting simulation...
+info: Entering event queue @ 217429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 218230956000. Starting simulation...
+info: Entering event queue @ 218429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 219230956000. Starting simulation...
+info: Entering event queue @ 219429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 220230956000. Starting simulation...
+info: Entering event queue @ 220429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 221230956000. Starting simulation...
+info: Entering event queue @ 221429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 222230956000. Starting simulation...
+info: Entering event queue @ 222429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 223230956000. Starting simulation...
+info: Entering event queue @ 223429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 224230956000. Starting simulation...
+info: Entering event queue @ 224429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 225230956000. Starting simulation...
+info: Entering event queue @ 225429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 226230956000. Starting simulation...
+info: Entering event queue @ 226429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 227230956000. Starting simulation...
+info: Entering event queue @ 227429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 228230956000. Starting simulation...
+info: Entering event queue @ 228429353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 229230956000. Starting simulation...
-info: Entering event queue @ 229967245000. Starting simulation...
+info: Entering event queue @ 229429353000. Starting simulation...
+info: Entering event queue @ 230164914000. Starting simulation...
switching cpus
-info: Entering event queue @ 229967247000. Starting simulation...
+info: Entering event queue @ 230164916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 230967247000. Starting simulation...
+info: Entering event queue @ 231164916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 231967247000. Starting simulation...
+info: Entering event queue @ 232164916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 232967247000. Starting simulation...
+info: Entering event queue @ 233164916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 233967247000. Starting simulation...
+info: Entering event queue @ 234164916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 234967247000. Starting simulation...
+info: Entering event queue @ 235164916000. Starting simulation...
switching cpus
-info: Entering event queue @ 234967248000. Starting simulation...
+info: Entering event queue @ 235164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 235967248000. Starting simulation...
+info: Entering event queue @ 236164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 236967248000. Starting simulation...
+info: Entering event queue @ 237164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 237967248000. Starting simulation...
+info: Entering event queue @ 238164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 238967248000. Starting simulation...
+info: Entering event queue @ 239164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 239967248000. Starting simulation...
+info: Entering event queue @ 240164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 240967248000. Starting simulation...
+info: Entering event queue @ 241164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 241967248000. Starting simulation...
+info: Entering event queue @ 242164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 242967248000. Starting simulation...
+info: Entering event queue @ 243164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 243967248000. Starting simulation...
+info: Entering event queue @ 244164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 244967248000. Starting simulation...
+info: Entering event queue @ 245164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 245967248000. Starting simulation...
+info: Entering event queue @ 246164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 246967248000. Starting simulation...
+info: Entering event queue @ 247164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 247967248000. Starting simulation...
+info: Entering event queue @ 248164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 248967248000. Starting simulation...
+info: Entering event queue @ 249164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 249967248000. Starting simulation...
+info: Entering event queue @ 250164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 250967248000. Starting simulation...
+info: Entering event queue @ 251164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 251967248000. Starting simulation...
+info: Entering event queue @ 252164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 252967248000. Starting simulation...
+info: Entering event queue @ 253164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 253967248000. Starting simulation...
+info: Entering event queue @ 254164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 254967248000. Starting simulation...
+info: Entering event queue @ 255164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 255967248000. Starting simulation...
+info: Entering event queue @ 256164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 256967248000. Starting simulation...
+info: Entering event queue @ 257164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 257967248000. Starting simulation...
+info: Entering event queue @ 258164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 258967248000. Starting simulation...
+info: Entering event queue @ 259164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 259967248000. Starting simulation...
+info: Entering event queue @ 260164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 260967248000. Starting simulation...
+info: Entering event queue @ 261164923500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 261967248000. Starting simulation...
-info: Entering event queue @ 262703389000. Starting simulation...
+info: Entering event queue @ 262164923500. Starting simulation...
+info: Entering event queue @ 262901514000. Starting simulation...
switching cpus
-info: Entering event queue @ 262703391000. Starting simulation...
+info: Entering event queue @ 262901516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 263703391000. Starting simulation...
+info: Entering event queue @ 263901516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 264901516000. Starting simulation...
switching cpus
-info: Entering event queue @ 264703391000. Starting simulation...
+info: Entering event queue @ 264901593000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 265703391000. Starting simulation...
-info: Entering event queue @ 265703411000. Starting simulation...
+info: Entering event queue @ 265901593000. Starting simulation...
switching cpus
-info: Entering event queue @ 265703413500. Starting simulation...
+info: Entering event queue @ 265901798500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 266703413500. Starting simulation...
+info: Entering event queue @ 266901798500. Starting simulation...
switching cpus
-info: Entering event queue @ 266703416000. Starting simulation...
+info: Entering event queue @ 266901833000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 267703416000. Starting simulation...
+info: Entering event queue @ 267901833000. Starting simulation...
switching cpus
-info: Entering event queue @ 267703417000. Starting simulation...
+info: Entering event queue @ 267901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 268703417000. Starting simulation...
+info: Entering event queue @ 268901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 269703417000. Starting simulation...
+info: Entering event queue @ 269901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 270703417000. Starting simulation...
+info: Entering event queue @ 270901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 271703417000. Starting simulation...
+info: Entering event queue @ 271901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 272703417000. Starting simulation...
+info: Entering event queue @ 272901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 273703417000. Starting simulation...
+info: Entering event queue @ 273901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 274703417000. Starting simulation...
+info: Entering event queue @ 274901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 275703417000. Starting simulation...
+info: Entering event queue @ 275901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 276703417000. Starting simulation...
+info: Entering event queue @ 276901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 277703417000. Starting simulation...
+info: Entering event queue @ 277901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 278703417000. Starting simulation...
+info: Entering event queue @ 278901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 279703417000. Starting simulation...
+info: Entering event queue @ 279901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 280703417000. Starting simulation...
+info: Entering event queue @ 280901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 281703417000. Starting simulation...
+info: Entering event queue @ 281901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 282703417000. Starting simulation...
+info: Entering event queue @ 282901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 283703417000. Starting simulation...
+info: Entering event queue @ 283901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 284703417000. Starting simulation...
+info: Entering event queue @ 284901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 285703417000. Starting simulation...
+info: Entering event queue @ 285901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 286703417000. Starting simulation...
+info: Entering event queue @ 286901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 287703417000. Starting simulation...
+info: Entering event queue @ 287901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 288703417000. Starting simulation...
+info: Entering event queue @ 288901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 289703417000. Starting simulation...
+info: Entering event queue @ 289901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 290703417000. Starting simulation...
+info: Entering event queue @ 290901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 291703417000. Starting simulation...
+info: Entering event queue @ 291901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 292703417000. Starting simulation...
+info: Entering event queue @ 292901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 293703417000. Starting simulation...
+info: Entering event queue @ 293901840500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 294703417000. Starting simulation...
-info: Entering event queue @ 295439680000. Starting simulation...
+info: Entering event queue @ 294901840500. Starting simulation...
+info: Entering event queue @ 295638135000. Starting simulation...
switching cpus
-info: Entering event queue @ 295439682000. Starting simulation...
+info: Entering event queue @ 295638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 296439682000. Starting simulation...
+info: Entering event queue @ 296638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 297439682000. Starting simulation...
+info: Entering event queue @ 297638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 298439682000. Starting simulation...
+info: Entering event queue @ 298638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 299439682000. Starting simulation...
+info: Entering event queue @ 299638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 300439682000. Starting simulation...
+info: Entering event queue @ 300638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 301439682000. Starting simulation...
+info: Entering event queue @ 301638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 302439682000. Starting simulation...
+info: Entering event queue @ 302638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 303439682000. Starting simulation...
+info: Entering event queue @ 303638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 304439682000. Starting simulation...
+info: Entering event queue @ 304638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 305439682000. Starting simulation...
+info: Entering event queue @ 305638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 306439682000. Starting simulation...
+info: Entering event queue @ 306638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 307439682000. Starting simulation...
+info: Entering event queue @ 307638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 308439682000. Starting simulation...
+info: Entering event queue @ 308638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 309439682000. Starting simulation...
+info: Entering event queue @ 309638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 310439682000. Starting simulation...
+info: Entering event queue @ 310638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 311439682000. Starting simulation...
+info: Entering event queue @ 311638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 312439682000. Starting simulation...
+info: Entering event queue @ 312638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 313439682000. Starting simulation...
+info: Entering event queue @ 313638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 314439682000. Starting simulation...
+info: Entering event queue @ 314638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 315439682000. Starting simulation...
+info: Entering event queue @ 315638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 316439682000. Starting simulation...
+info: Entering event queue @ 316638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 317439682000. Starting simulation...
+info: Entering event queue @ 317638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 318439682000. Starting simulation...
+info: Entering event queue @ 318638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 319439682000. Starting simulation...
+info: Entering event queue @ 319638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 320439682000. Starting simulation...
+info: Entering event queue @ 320638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 321439682000. Starting simulation...
+info: Entering event queue @ 321638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 322439682000. Starting simulation...
+info: Entering event queue @ 322638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 323439682000. Starting simulation...
+info: Entering event queue @ 323638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 324439682000. Starting simulation...
+info: Entering event queue @ 324638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 325439682000. Starting simulation...
+info: Entering event queue @ 325638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 326439682000. Starting simulation...
+info: Entering event queue @ 326638137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 327439682000. Starting simulation...
-info: Entering event queue @ 328175821000. Starting simulation...
+info: Entering event queue @ 327638137000. Starting simulation...
+info: Entering event queue @ 328373547000. Starting simulation...
switching cpus
-info: Entering event queue @ 328175823000. Starting simulation...
+info: Entering event queue @ 328373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 329175823000. Starting simulation...
+info: Entering event queue @ 329373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 330175823000. Starting simulation...
+info: Entering event queue @ 330373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 331175823000. Starting simulation...
+info: Entering event queue @ 331373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 332175823000. Starting simulation...
+info: Entering event queue @ 332373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 333175823000. Starting simulation...
+info: Entering event queue @ 333373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 334175823000. Starting simulation...
+info: Entering event queue @ 334373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 335175823000. Starting simulation...
+info: Entering event queue @ 335373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 336175823000. Starting simulation...
+info: Entering event queue @ 336373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 337175823000. Starting simulation...
+info: Entering event queue @ 337373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 338175823000. Starting simulation...
+info: Entering event queue @ 338373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 339175823000. Starting simulation...
+info: Entering event queue @ 339373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 340175823000. Starting simulation...
+info: Entering event queue @ 340373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 341175823000. Starting simulation...
+info: Entering event queue @ 341373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 342175823000. Starting simulation...
+info: Entering event queue @ 342373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 343175823000. Starting simulation...
+info: Entering event queue @ 343373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 344175823000. Starting simulation...
+info: Entering event queue @ 344373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 345175823000. Starting simulation...
+info: Entering event queue @ 345373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 346175823000. Starting simulation...
+info: Entering event queue @ 346373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 347175823000. Starting simulation...
+info: Entering event queue @ 347373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 348175823000. Starting simulation...
+info: Entering event queue @ 348373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 349175823000. Starting simulation...
+info: Entering event queue @ 349373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 350175823000. Starting simulation...
+info: Entering event queue @ 350373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 351175823000. Starting simulation...
+info: Entering event queue @ 351373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 352175823000. Starting simulation...
+info: Entering event queue @ 352373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 353175823000. Starting simulation...
+info: Entering event queue @ 353373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 354175823000. Starting simulation...
+info: Entering event queue @ 354373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 355175823000. Starting simulation...
+info: Entering event queue @ 355373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 356175823000. Starting simulation...
+info: Entering event queue @ 356373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 357175823000. Starting simulation...
+info: Entering event queue @ 357373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 358175823000. Starting simulation...
+info: Entering event queue @ 358373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 359175823000. Starting simulation...
+info: Entering event queue @ 359373549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 360175823000. Starting simulation...
-info: Entering event queue @ 360912115000. Starting simulation...
+info: Entering event queue @ 360373549000. Starting simulation...
+info: Entering event queue @ 361110147000. Starting simulation...
switching cpus
-info: Entering event queue @ 360912117000. Starting simulation...
+info: Entering event queue @ 361110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 361912117000. Starting simulation...
+info: Entering event queue @ 362110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 362912117000. Starting simulation...
+info: Entering event queue @ 363110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 363912117000. Starting simulation...
+info: Entering event queue @ 364110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 364912117000. Starting simulation...
+info: Entering event queue @ 365110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 365912117000. Starting simulation...
+info: Entering event queue @ 366110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 366912117000. Starting simulation...
+info: Entering event queue @ 367110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 367912117000. Starting simulation...
+info: Entering event queue @ 368110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 368912117000. Starting simulation...
+info: Entering event queue @ 369110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 369912117000. Starting simulation...
+info: Entering event queue @ 370110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 370912117000. Starting simulation...
+info: Entering event queue @ 371110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 371912117000. Starting simulation...
+info: Entering event queue @ 372110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 372912117000. Starting simulation...
+info: Entering event queue @ 373110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 373912117000. Starting simulation...
+info: Entering event queue @ 374110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 374912117000. Starting simulation...
+info: Entering event queue @ 375110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 375912117000. Starting simulation...
+info: Entering event queue @ 376110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 376912117000. Starting simulation...
+info: Entering event queue @ 377110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 377912117000. Starting simulation...
+info: Entering event queue @ 378110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 378912117000. Starting simulation...
+info: Entering event queue @ 379110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 379912117000. Starting simulation...
+info: Entering event queue @ 380110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 380912117000. Starting simulation...
+info: Entering event queue @ 381110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 381912117000. Starting simulation...
+info: Entering event queue @ 382110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 382912117000. Starting simulation...
+info: Entering event queue @ 383110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 383912117000. Starting simulation...
+info: Entering event queue @ 384110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 384912117000. Starting simulation...
+info: Entering event queue @ 385110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 385912117000. Starting simulation...
+info: Entering event queue @ 386110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 386912117000. Starting simulation...
+info: Entering event queue @ 387110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 387912117000. Starting simulation...
+info: Entering event queue @ 388110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 388912117000. Starting simulation...
+info: Entering event queue @ 389110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 389912117000. Starting simulation...
+info: Entering event queue @ 390110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 390912117000. Starting simulation...
+info: Entering event queue @ 391110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 391912117000. Starting simulation...
+info: Entering event queue @ 392110149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 392912117000. Starting simulation...
-info: Entering event queue @ 393648256000. Starting simulation...
+info: Entering event queue @ 393110149000. Starting simulation...
+info: Entering event queue @ 393846726000. Starting simulation...
switching cpus
-info: Entering event queue @ 393648258000. Starting simulation...
+info: Entering event queue @ 393846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 394648258000. Starting simulation...
+info: Entering event queue @ 394846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 395648258000. Starting simulation...
+info: Entering event queue @ 395846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 396648258000. Starting simulation...
+info: Entering event queue @ 396846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 397648258000. Starting simulation...
+info: Entering event queue @ 397846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 398648258000. Starting simulation...
+info: Entering event queue @ 398846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 399648258000. Starting simulation...
+info: Entering event queue @ 399846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 400648258000. Starting simulation...
+info: Entering event queue @ 400846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 401648258000. Starting simulation...
+info: Entering event queue @ 401846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 402648258000. Starting simulation...
+info: Entering event queue @ 402846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 403648258000. Starting simulation...
+info: Entering event queue @ 403846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 404648258000. Starting simulation...
+info: Entering event queue @ 404846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 405648258000. Starting simulation...
+info: Entering event queue @ 405846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 406648258000. Starting simulation...
+info: Entering event queue @ 406846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 407648258000. Starting simulation...
+info: Entering event queue @ 407846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 408648258000. Starting simulation...
+info: Entering event queue @ 408846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 409648258000. Starting simulation...
+info: Entering event queue @ 409846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 410648258000. Starting simulation...
+info: Entering event queue @ 410846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 411648258000. Starting simulation...
+info: Entering event queue @ 411846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 412648258000. Starting simulation...
+info: Entering event queue @ 412846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 413648258000. Starting simulation...
+info: Entering event queue @ 413846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 414648258000. Starting simulation...
+info: Entering event queue @ 414846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 415648258000. Starting simulation...
+info: Entering event queue @ 415846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 416648258000. Starting simulation...
+info: Entering event queue @ 416846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 417648258000. Starting simulation...
+info: Entering event queue @ 417846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 418648258000. Starting simulation...
+info: Entering event queue @ 418846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 419648258000. Starting simulation...
+info: Entering event queue @ 419846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 420648258000. Starting simulation...
+info: Entering event queue @ 420846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 421648258000. Starting simulation...
+info: Entering event queue @ 421846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 422648258000. Starting simulation...
+info: Entering event queue @ 422846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 423648258000. Starting simulation...
+info: Entering event queue @ 423846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 424648258000. Starting simulation...
+info: Entering event queue @ 424846728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 425648258000. Starting simulation...
-info: Entering event queue @ 426384856000. Starting simulation...
+info: Entering event queue @ 425846728000. Starting simulation...
+info: Entering event queue @ 426582138000. Starting simulation...
switching cpus
-info: Entering event queue @ 426384858000. Starting simulation...
+info: Entering event queue @ 426582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 427384858000. Starting simulation...
+info: Entering event queue @ 427582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 428384858000. Starting simulation...
+info: Entering event queue @ 428582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 429384858000. Starting simulation...
+info: Entering event queue @ 429582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 430384858000. Starting simulation...
+info: Entering event queue @ 430582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 431384858000. Starting simulation...
+info: Entering event queue @ 431582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 432384858000. Starting simulation...
+info: Entering event queue @ 432582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 433384858000. Starting simulation...
+info: Entering event queue @ 433582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 434384858000. Starting simulation...
+info: Entering event queue @ 434582140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 435384858000. Starting simulation...
+info: Entering event queue @ 435582140000. Starting simulation...
switching cpus
-info: Entering event queue @ 435384859000. Starting simulation...
+info: Entering event queue @ 435582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 436384859000. Starting simulation...
+info: Entering event queue @ 436582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 437384859000. Starting simulation...
+info: Entering event queue @ 437582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 438384859000. Starting simulation...
+info: Entering event queue @ 438582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 439384859000. Starting simulation...
+info: Entering event queue @ 439582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 440384859000. Starting simulation...
+info: Entering event queue @ 440582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 441384859000. Starting simulation...
+info: Entering event queue @ 441582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 442384859000. Starting simulation...
+info: Entering event queue @ 442582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 443384859000. Starting simulation...
+info: Entering event queue @ 443582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 444384859000. Starting simulation...
+info: Entering event queue @ 444582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 445384859000. Starting simulation...
+info: Entering event queue @ 445582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 446384859000. Starting simulation...
+info: Entering event queue @ 446582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 447384859000. Starting simulation...
+info: Entering event queue @ 447582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 448384859000. Starting simulation...
+info: Entering event queue @ 448582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 449384859000. Starting simulation...
+info: Entering event queue @ 449582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 450384859000. Starting simulation...
+info: Entering event queue @ 450582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 451384859000. Starting simulation...
+info: Entering event queue @ 451582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 452384859000. Starting simulation...
+info: Entering event queue @ 452582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 453384859000. Starting simulation...
+info: Entering event queue @ 453582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 454384859000. Starting simulation...
+info: Entering event queue @ 454582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 455384859000. Starting simulation...
+info: Entering event queue @ 455582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 456384859000. Starting simulation...
+info: Entering event queue @ 456582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 457384859000. Starting simulation...
+info: Entering event queue @ 457582147500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 458384859000. Starting simulation...
-info: Entering event queue @ 459121147000. Starting simulation...
+info: Entering event queue @ 458582147500. Starting simulation...
+info: Entering event queue @ 459318738000. Starting simulation...
switching cpus
-info: Entering event queue @ 459121149000. Starting simulation...
+info: Entering event queue @ 459318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 460121149000. Starting simulation...
+info: Entering event queue @ 460318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 461121149000. Starting simulation...
+info: Entering event queue @ 461318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 462121149000. Starting simulation...
+info: Entering event queue @ 462318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 463121149000. Starting simulation...
+info: Entering event queue @ 463318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 464121149000. Starting simulation...
+info: Entering event queue @ 464318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 465121149000. Starting simulation...
+info: Entering event queue @ 465318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 466121149000. Starting simulation...
+info: Entering event queue @ 466318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 467121149000. Starting simulation...
+info: Entering event queue @ 467318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 468121149000. Starting simulation...
+info: Entering event queue @ 468318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 469121149000. Starting simulation...
+info: Entering event queue @ 469318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 470121149000. Starting simulation...
+info: Entering event queue @ 470318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 471121149000. Starting simulation...
+info: Entering event queue @ 471318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 472121149000. Starting simulation...
+info: Entering event queue @ 472318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 473121149000. Starting simulation...
+info: Entering event queue @ 473318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 474121149000. Starting simulation...
+info: Entering event queue @ 474318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 475121149000. Starting simulation...
+info: Entering event queue @ 475318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 476121149000. Starting simulation...
+info: Entering event queue @ 476318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 477121149000. Starting simulation...
+info: Entering event queue @ 477318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 478121149000. Starting simulation...
+info: Entering event queue @ 478318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 479121149000. Starting simulation...
+info: Entering event queue @ 479318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 480121149000. Starting simulation...
+info: Entering event queue @ 480318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 481121149000. Starting simulation...
+info: Entering event queue @ 481318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 482121149000. Starting simulation...
+info: Entering event queue @ 482318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 483121149000. Starting simulation...
+info: Entering event queue @ 483318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 484121149000. Starting simulation...
+info: Entering event queue @ 484318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 485121149000. Starting simulation...
+info: Entering event queue @ 485318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 486121149000. Starting simulation...
+info: Entering event queue @ 486318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 487121149000. Starting simulation...
+info: Entering event queue @ 487318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 488121149000. Starting simulation...
+info: Entering event queue @ 488318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 489121149000. Starting simulation...
+info: Entering event queue @ 489318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 490121149000. Starting simulation...
+info: Entering event queue @ 490318740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 491121149000. Starting simulation...
-info: Entering event queue @ 491857291000. Starting simulation...
+info: Entering event queue @ 491318740000. Starting simulation...
+info: Entering event queue @ 492055355000. Starting simulation...
switching cpus
-info: Entering event queue @ 491857293000. Starting simulation...
+info: Entering event queue @ 492055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 492857293000. Starting simulation...
+info: Entering event queue @ 493055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 493857293000. Starting simulation...
+info: Entering event queue @ 494055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 494857293000. Starting simulation...
+info: Entering event queue @ 495055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 495857293000. Starting simulation...
+info: Entering event queue @ 496055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 496857293000. Starting simulation...
+info: Entering event queue @ 497055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 497857293000. Starting simulation...
+info: Entering event queue @ 498055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 498857293000. Starting simulation...
+info: Entering event queue @ 499055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 499857293000. Starting simulation...
+info: Entering event queue @ 500055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 500857293000. Starting simulation...
+info: Entering event queue @ 501055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 501857293000. Starting simulation...
+info: Entering event queue @ 502055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 502857293000. Starting simulation...
+info: Entering event queue @ 503055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 503857293000. Starting simulation...
+info: Entering event queue @ 504055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 504857293000. Starting simulation...
+info: Entering event queue @ 505055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 505857293000. Starting simulation...
+info: Entering event queue @ 506055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 506857293000. Starting simulation...
+info: Entering event queue @ 507055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 507857293000. Starting simulation...
+info: Entering event queue @ 508055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 508857293000. Starting simulation...
+info: Entering event queue @ 509055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 509857293000. Starting simulation...
+info: Entering event queue @ 510055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 510857293000. Starting simulation...
+info: Entering event queue @ 511055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 511857293000. Starting simulation...
+info: Entering event queue @ 512055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 512857293000. Starting simulation...
+info: Entering event queue @ 513055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 513857293000. Starting simulation...
+info: Entering event queue @ 514055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 514857293000. Starting simulation...
+info: Entering event queue @ 515055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 515857293000. Starting simulation...
+info: Entering event queue @ 516055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 516857293000. Starting simulation...
+info: Entering event queue @ 517055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 517857293000. Starting simulation...
+info: Entering event queue @ 518055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 518857293000. Starting simulation...
+info: Entering event queue @ 519055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 519857293000. Starting simulation...
+info: Entering event queue @ 520055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 520857293000. Starting simulation...
+info: Entering event queue @ 521055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 521857293000. Starting simulation...
+info: Entering event queue @ 522055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 522857293000. Starting simulation...
+info: Entering event queue @ 523055357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 523857293000. Starting simulation...
-info: Entering event queue @ 524593582000. Starting simulation...
+info: Entering event queue @ 524055357000. Starting simulation...
+info: Entering event queue @ 524790922000. Starting simulation...
switching cpus
-info: Entering event queue @ 524593584000. Starting simulation...
+info: Entering event queue @ 524790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 525593584000. Starting simulation...
+info: Entering event queue @ 525790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 526593584000. Starting simulation...
+info: Entering event queue @ 526790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 527593584000. Starting simulation...
+info: Entering event queue @ 527790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 528593584000. Starting simulation...
+info: Entering event queue @ 528790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 529593584000. Starting simulation...
+info: Entering event queue @ 529790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 530593584000. Starting simulation...
+info: Entering event queue @ 530790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 531593584000. Starting simulation...
+info: Entering event queue @ 531790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 532593584000. Starting simulation...
+info: Entering event queue @ 532790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 533593584000. Starting simulation...
+info: Entering event queue @ 533790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 534593584000. Starting simulation...
+info: Entering event queue @ 534790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 535593584000. Starting simulation...
+info: Entering event queue @ 535790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 536593584000. Starting simulation...
+info: Entering event queue @ 536790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 537593584000. Starting simulation...
+info: Entering event queue @ 537790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 538593584000. Starting simulation...
+info: Entering event queue @ 538790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 539593584000. Starting simulation...
+info: Entering event queue @ 539790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 540593584000. Starting simulation...
+info: Entering event queue @ 540790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 541593584000. Starting simulation...
+info: Entering event queue @ 541790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 542593584000. Starting simulation...
+info: Entering event queue @ 542790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 543593584000. Starting simulation...
+info: Entering event queue @ 543790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 544593584000. Starting simulation...
+info: Entering event queue @ 544790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 545593584000. Starting simulation...
+info: Entering event queue @ 545790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 546593584000. Starting simulation...
+info: Entering event queue @ 546790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 547593584000. Starting simulation...
+info: Entering event queue @ 547790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 548593584000. Starting simulation...
+info: Entering event queue @ 548790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 549593584000. Starting simulation...
+info: Entering event queue @ 549790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 550593584000. Starting simulation...
+info: Entering event queue @ 550790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 551593584000. Starting simulation...
+info: Entering event queue @ 551790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 552593584000. Starting simulation...
+info: Entering event queue @ 552790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 553593584000. Starting simulation...
+info: Entering event queue @ 553790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 554593584000. Starting simulation...
+info: Entering event queue @ 554790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 555593584000. Starting simulation...
+info: Entering event queue @ 555790924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 556593584000. Starting simulation...
-info: Entering event queue @ 557329726000. Starting simulation...
+info: Entering event queue @ 556790924000. Starting simulation...
+info: Entering event queue @ 557527522000. Starting simulation...
switching cpus
-info: Entering event queue @ 557329728000. Starting simulation...
+info: Entering event queue @ 557527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 558329728000. Starting simulation...
+info: Entering event queue @ 558527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 559329728000. Starting simulation...
+info: Entering event queue @ 559527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 560329728000. Starting simulation...
+info: Entering event queue @ 560527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 561329728000. Starting simulation...
+info: Entering event queue @ 561527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 562329728000. Starting simulation...
+info: Entering event queue @ 562527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 563329728000. Starting simulation...
+info: Entering event queue @ 563527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 564329728000. Starting simulation...
+info: Entering event queue @ 564527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 565329728000. Starting simulation...
+info: Entering event queue @ 565527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 566329728000. Starting simulation...
+info: Entering event queue @ 566527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 567329728000. Starting simulation...
+info: Entering event queue @ 567527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 568329728000. Starting simulation...
+info: Entering event queue @ 568527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 569329728000. Starting simulation...
+info: Entering event queue @ 569527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 570329728000. Starting simulation...
+info: Entering event queue @ 570527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 571329728000. Starting simulation...
+info: Entering event queue @ 571527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 572329728000. Starting simulation...
+info: Entering event queue @ 572527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 573329728000. Starting simulation...
+info: Entering event queue @ 573527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 574329728000. Starting simulation...
+info: Entering event queue @ 574527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 575329728000. Starting simulation...
+info: Entering event queue @ 575527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 576329728000. Starting simulation...
+info: Entering event queue @ 576527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 577329728000. Starting simulation...
+info: Entering event queue @ 577527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 578329728000. Starting simulation...
+info: Entering event queue @ 578527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 579329728000. Starting simulation...
+info: Entering event queue @ 579527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 580329728000. Starting simulation...
+info: Entering event queue @ 580527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 581329728000. Starting simulation...
+info: Entering event queue @ 581527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 582329728000. Starting simulation...
+info: Entering event queue @ 582527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 583329728000. Starting simulation...
+info: Entering event queue @ 583527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 584329728000. Starting simulation...
+info: Entering event queue @ 584527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 585329728000. Starting simulation...
+info: Entering event queue @ 585527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 586329728000. Starting simulation...
+info: Entering event queue @ 586527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 587329728000. Starting simulation...
+info: Entering event queue @ 587527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 588329728000. Starting simulation...
+info: Entering event queue @ 588527524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 589329728000. Starting simulation...
-info: Entering event queue @ 590065873000. Starting simulation...
+info: Entering event queue @ 589527524000. Starting simulation...
+info: Entering event queue @ 590264122000. Starting simulation...
switching cpus
-info: Entering event queue @ 590065875000. Starting simulation...
+info: Entering event queue @ 590264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 591065875000. Starting simulation...
+info: Entering event queue @ 591264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 592065875000. Starting simulation...
+info: Entering event queue @ 592264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 593065875000. Starting simulation...
+info: Entering event queue @ 593264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 594065875000. Starting simulation...
+info: Entering event queue @ 594264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 595065875000. Starting simulation...
+info: Entering event queue @ 595264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 596065875000. Starting simulation...
+info: Entering event queue @ 596264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 597065875000. Starting simulation...
+info: Entering event queue @ 597264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 598065875000. Starting simulation...
+info: Entering event queue @ 598264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 599065875000. Starting simulation...
+info: Entering event queue @ 599264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 600065875000. Starting simulation...
+info: Entering event queue @ 600264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 601065875000. Starting simulation...
+info: Entering event queue @ 601264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 602065875000. Starting simulation...
+info: Entering event queue @ 602264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 603065875000. Starting simulation...
+info: Entering event queue @ 603264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 604065875000. Starting simulation...
+info: Entering event queue @ 604264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 605065875000. Starting simulation...
+info: Entering event queue @ 605264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 606065875000. Starting simulation...
+info: Entering event queue @ 606264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 607065875000. Starting simulation...
+info: Entering event queue @ 607264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 608065875000. Starting simulation...
+info: Entering event queue @ 608264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 609065875000. Starting simulation...
+info: Entering event queue @ 609264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 610065875000. Starting simulation...
+info: Entering event queue @ 610264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 611065875000. Starting simulation...
+info: Entering event queue @ 611264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 612065875000. Starting simulation...
+info: Entering event queue @ 612264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 613065875000. Starting simulation...
+info: Entering event queue @ 613264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 614065875000. Starting simulation...
+info: Entering event queue @ 614264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 615065875000. Starting simulation...
+info: Entering event queue @ 615264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 616065875000. Starting simulation...
+info: Entering event queue @ 616264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 617065875000. Starting simulation...
+info: Entering event queue @ 617264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 618065875000. Starting simulation...
+info: Entering event queue @ 618264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 619065875000. Starting simulation...
+info: Entering event queue @ 619264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 620065875000. Starting simulation...
+info: Entering event queue @ 620264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 621065875000. Starting simulation...
+info: Entering event queue @ 621264124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 622065875000. Starting simulation...
-info: Entering event queue @ 622802473000. Starting simulation...
+info: Entering event queue @ 622264124000. Starting simulation...
+info: Entering event queue @ 623000743000. Starting simulation...
switching cpus
-info: Entering event queue @ 622802475000. Starting simulation...
+info: Entering event queue @ 623000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 623802475000. Starting simulation...
+info: Entering event queue @ 624000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 624802475000. Starting simulation...
+info: Entering event queue @ 625000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 625802475000. Starting simulation...
+info: Entering event queue @ 626000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 626802475000. Starting simulation...
+info: Entering event queue @ 627000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 627802475000. Starting simulation...
+info: Entering event queue @ 628000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 628802475000. Starting simulation...
+info: Entering event queue @ 629000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 629802475000. Starting simulation...
+info: Entering event queue @ 630000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 630802475000. Starting simulation...
+info: Entering event queue @ 631000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 631802475000. Starting simulation...
+info: Entering event queue @ 632000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 632802475000. Starting simulation...
+info: Entering event queue @ 633000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 633802475000. Starting simulation...
+info: Entering event queue @ 634000745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 634802475000. Starting simulation...
+info: Entering event queue @ 635000745000. Starting simulation...
switching cpus
-info: Entering event queue @ 634802476000. Starting simulation...
+info: Entering event queue @ 635000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 635802476000. Starting simulation...
+info: Entering event queue @ 636000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 636802476000. Starting simulation...
+info: Entering event queue @ 637000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 637802476000. Starting simulation...
+info: Entering event queue @ 638000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 638802476000. Starting simulation...
+info: Entering event queue @ 639000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 639802476000. Starting simulation...
+info: Entering event queue @ 640000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 640802476000. Starting simulation...
+info: Entering event queue @ 641000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 641802476000. Starting simulation...
+info: Entering event queue @ 642000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 642802476000. Starting simulation...
+info: Entering event queue @ 643000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 643802476000. Starting simulation...
+info: Entering event queue @ 644000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 644802476000. Starting simulation...
+info: Entering event queue @ 645000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 645802476000. Starting simulation...
+info: Entering event queue @ 646000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 646802476000. Starting simulation...
+info: Entering event queue @ 647000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 647802476000. Starting simulation...
+info: Entering event queue @ 648000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 648802476000. Starting simulation...
+info: Entering event queue @ 649000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 649802476000. Starting simulation...
+info: Entering event queue @ 650000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 650802476000. Starting simulation...
+info: Entering event queue @ 651000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 651802476000. Starting simulation...
+info: Entering event queue @ 652000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 652802476000. Starting simulation...
+info: Entering event queue @ 653000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 653802476000. Starting simulation...
+info: Entering event queue @ 654000752500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 654802476000. Starting simulation...
-info: Entering event queue @ 655538305000. Starting simulation...
+info: Entering event queue @ 655000752500. Starting simulation...
+info: Entering event queue @ 655736155000. Starting simulation...
switching cpus
-info: Entering event queue @ 655538307000. Starting simulation...
+info: Entering event queue @ 655736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 656538307000. Starting simulation...
+info: Entering event queue @ 656736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 657538307000. Starting simulation...
+info: Entering event queue @ 657736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 658538307000. Starting simulation...
+info: Entering event queue @ 658736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 659538307000. Starting simulation...
+info: Entering event queue @ 659736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 660538307000. Starting simulation...
+info: Entering event queue @ 660736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 661538307000. Starting simulation...
+info: Entering event queue @ 661736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 662538307000. Starting simulation...
+info: Entering event queue @ 662736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 663538307000. Starting simulation...
+info: Entering event queue @ 663736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 664538307000. Starting simulation...
+info: Entering event queue @ 664736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 665538307000. Starting simulation...
+info: Entering event queue @ 665736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 666538307000. Starting simulation...
+info: Entering event queue @ 666736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 667538307000. Starting simulation...
+info: Entering event queue @ 667736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 668538307000. Starting simulation...
+info: Entering event queue @ 668736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 669538307000. Starting simulation...
+info: Entering event queue @ 669736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 670538307000. Starting simulation...
+info: Entering event queue @ 670736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 671538307000. Starting simulation...
+info: Entering event queue @ 671736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 672538307000. Starting simulation...
+info: Entering event queue @ 672736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 673538307000. Starting simulation...
+info: Entering event queue @ 673736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 674538307000. Starting simulation...
+info: Entering event queue @ 674736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 675538307000. Starting simulation...
+info: Entering event queue @ 675736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 676538307000. Starting simulation...
+info: Entering event queue @ 676736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 677538307000. Starting simulation...
+info: Entering event queue @ 677736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 678538307000. Starting simulation...
+info: Entering event queue @ 678736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 679538307000. Starting simulation...
+info: Entering event queue @ 679736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 680538307000. Starting simulation...
+info: Entering event queue @ 680736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 681538307000. Starting simulation...
+info: Entering event queue @ 681736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 682538307000. Starting simulation...
+info: Entering event queue @ 682736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 683538307000. Starting simulation...
+info: Entering event queue @ 683736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 684538307000. Starting simulation...
+info: Entering event queue @ 684736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 685538307000. Starting simulation...
+info: Entering event queue @ 685736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 686538307000. Starting simulation...
+info: Entering event queue @ 686736157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 687538307000. Starting simulation...
-info: Entering event queue @ 688274905000. Starting simulation...
+info: Entering event queue @ 687736157000. Starting simulation...
+info: Entering event queue @ 688472755000. Starting simulation...
switching cpus
-info: Entering event queue @ 688274907000. Starting simulation...
+info: Entering event queue @ 688472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 689274907000. Starting simulation...
+info: Entering event queue @ 689472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 690274907000. Starting simulation...
+info: Entering event queue @ 690472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 691274907000. Starting simulation...
+info: Entering event queue @ 691472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 692274907000. Starting simulation...
+info: Entering event queue @ 692472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 693274907000. Starting simulation...
+info: Entering event queue @ 693472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 694274907000. Starting simulation...
+info: Entering event queue @ 694472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 695274907000. Starting simulation...
+info: Entering event queue @ 695472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 696274907000. Starting simulation...
+info: Entering event queue @ 696472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 697274907000. Starting simulation...
+info: Entering event queue @ 697472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 698274907000. Starting simulation...
+info: Entering event queue @ 698472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 699274907000. Starting simulation...
+info: Entering event queue @ 699472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 700274907000. Starting simulation...
+info: Entering event queue @ 700472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 701274907000. Starting simulation...
+info: Entering event queue @ 701472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 702274907000. Starting simulation...
+info: Entering event queue @ 702472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 703274907000. Starting simulation...
+info: Entering event queue @ 703472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 704274907000. Starting simulation...
+info: Entering event queue @ 704472757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 705274907000. Starting simulation...
+info: Entering event queue @ 705472757000. Starting simulation...
switching cpus
-info: Entering event queue @ 705274908000. Starting simulation...
+info: Entering event queue @ 705472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 706274908000. Starting simulation...
+info: Entering event queue @ 706472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 707274908000. Starting simulation...
+info: Entering event queue @ 707472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 708274908000. Starting simulation...
+info: Entering event queue @ 708472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 709274908000. Starting simulation...
+info: Entering event queue @ 709472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 710274908000. Starting simulation...
+info: Entering event queue @ 710472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 711274908000. Starting simulation...
+info: Entering event queue @ 711472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 712274908000. Starting simulation...
+info: Entering event queue @ 712472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 713274908000. Starting simulation...
+info: Entering event queue @ 713472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 714274908000. Starting simulation...
+info: Entering event queue @ 714472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 715274908000. Starting simulation...
+info: Entering event queue @ 715472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 716274908000. Starting simulation...
+info: Entering event queue @ 716472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 717274908000. Starting simulation...
+info: Entering event queue @ 717472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 718274908000. Starting simulation...
+info: Entering event queue @ 718472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 719274908000. Starting simulation...
+info: Entering event queue @ 719472764500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 720274908000. Starting simulation...
-info: Entering event queue @ 721011196000. Starting simulation...
+info: Entering event queue @ 720472764500. Starting simulation...
+info: Entering event queue @ 721209334000. Starting simulation...
switching cpus
-info: Entering event queue @ 721011198000. Starting simulation...
+info: Entering event queue @ 721209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 722011198000. Starting simulation...
+info: Entering event queue @ 722209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 723011198000. Starting simulation...
+info: Entering event queue @ 723209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 724011198000. Starting simulation...
+info: Entering event queue @ 724209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 725011198000. Starting simulation...
+info: Entering event queue @ 725209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 726011198000. Starting simulation...
+info: Entering event queue @ 726209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 727011198000. Starting simulation...
+info: Entering event queue @ 727209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 728011198000. Starting simulation...
+info: Entering event queue @ 728209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 729011198000. Starting simulation...
+info: Entering event queue @ 729209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 730011198000. Starting simulation...
+info: Entering event queue @ 730209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 731011198000. Starting simulation...
+info: Entering event queue @ 731209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 732011198000. Starting simulation...
+info: Entering event queue @ 732209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 733011198000. Starting simulation...
+info: Entering event queue @ 733209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 734011198000. Starting simulation...
+info: Entering event queue @ 734209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 735011198000. Starting simulation...
+info: Entering event queue @ 735209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 736011198000. Starting simulation...
+info: Entering event queue @ 736209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 737011198000. Starting simulation...
+info: Entering event queue @ 737209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 738011198000. Starting simulation...
+info: Entering event queue @ 738209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 739011198000. Starting simulation...
+info: Entering event queue @ 739209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 740011198000. Starting simulation...
+info: Entering event queue @ 740209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 741011198000. Starting simulation...
+info: Entering event queue @ 741209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 742011198000. Starting simulation...
+info: Entering event queue @ 742209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 743011198000. Starting simulation...
+info: Entering event queue @ 743209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 744011198000. Starting simulation...
+info: Entering event queue @ 744209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 745011198000. Starting simulation...
+info: Entering event queue @ 745209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 746011198000. Starting simulation...
+info: Entering event queue @ 746209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 747011198000. Starting simulation...
+info: Entering event queue @ 747209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 748011198000. Starting simulation...
+info: Entering event queue @ 748209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 749011198000. Starting simulation...
+info: Entering event queue @ 749209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 750011198000. Starting simulation...
+info: Entering event queue @ 750209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 751011198000. Starting simulation...
+info: Entering event queue @ 751209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 752011198000. Starting simulation...
+info: Entering event queue @ 752209336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 753011198000. Starting simulation...
-info: Entering event queue @ 753747337000. Starting simulation...
+info: Entering event queue @ 753209336000. Starting simulation...
+info: Entering event queue @ 753944939000. Starting simulation...
switching cpus
-info: Entering event queue @ 753747339000. Starting simulation...
+info: Entering event queue @ 753944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 754747339000. Starting simulation...
+info: Entering event queue @ 754944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 755747339000. Starting simulation...
+info: Entering event queue @ 755944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 756747339000. Starting simulation...
+info: Entering event queue @ 756944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 757747339000. Starting simulation...
+info: Entering event queue @ 757944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 758747339000. Starting simulation...
+info: Entering event queue @ 758944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 759747339000. Starting simulation...
+info: Entering event queue @ 759944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 760747339000. Starting simulation...
+info: Entering event queue @ 760944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 761747339000. Starting simulation...
+info: Entering event queue @ 761944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 762747339000. Starting simulation...
+info: Entering event queue @ 762944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 763747339000. Starting simulation...
+info: Entering event queue @ 763944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 764747339000. Starting simulation...
+info: Entering event queue @ 764944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 765747339000. Starting simulation...
+info: Entering event queue @ 765944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 766747339000. Starting simulation...
+info: Entering event queue @ 766944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 767747339000. Starting simulation...
+info: Entering event queue @ 767944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 768747339000. Starting simulation...
+info: Entering event queue @ 768944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 769747339000. Starting simulation...
+info: Entering event queue @ 769944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 770747339000. Starting simulation...
+info: Entering event queue @ 770944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 771747339000. Starting simulation...
+info: Entering event queue @ 771944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 772747339000. Starting simulation...
+info: Entering event queue @ 772944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 773747339000. Starting simulation...
+info: Entering event queue @ 773944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 774747339000. Starting simulation...
+info: Entering event queue @ 774944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 775747339000. Starting simulation...
+info: Entering event queue @ 775944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 776747339000. Starting simulation...
+info: Entering event queue @ 776944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 777747339000. Starting simulation...
+info: Entering event queue @ 777944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 778747339000. Starting simulation...
+info: Entering event queue @ 778944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 779747339000. Starting simulation...
+info: Entering event queue @ 779944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 780747339000. Starting simulation...
+info: Entering event queue @ 780944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 781747339000. Starting simulation...
+info: Entering event queue @ 781944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 782747339000. Starting simulation...
+info: Entering event queue @ 782944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 783747339000. Starting simulation...
+info: Entering event queue @ 783944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 784747339000. Starting simulation...
+info: Entering event queue @ 784944941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 785747339000. Starting simulation...
-info: Entering event queue @ 786483631000. Starting simulation...
+info: Entering event queue @ 785944941000. Starting simulation...
+info: Entering event queue @ 786681539000. Starting simulation...
switching cpus
-info: Entering event queue @ 786483633000. Starting simulation...
+info: Entering event queue @ 786681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 787483633000. Starting simulation...
+info: Entering event queue @ 787681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 788483633000. Starting simulation...
+info: Entering event queue @ 788681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 789483633000. Starting simulation...
+info: Entering event queue @ 789681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 790483633000. Starting simulation...
+info: Entering event queue @ 790681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 791483633000. Starting simulation...
+info: Entering event queue @ 791681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 792483633000. Starting simulation...
+info: Entering event queue @ 792681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 793483633000. Starting simulation...
+info: Entering event queue @ 793681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 794483633000. Starting simulation...
+info: Entering event queue @ 794681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 795483633000. Starting simulation...
+info: Entering event queue @ 795681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 796483633000. Starting simulation...
+info: Entering event queue @ 796681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 797483633000. Starting simulation...
+info: Entering event queue @ 797681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 798483633000. Starting simulation...
+info: Entering event queue @ 798681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 799483633000. Starting simulation...
+info: Entering event queue @ 799681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 800483633000. Starting simulation...
+info: Entering event queue @ 800681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 801483633000. Starting simulation...
+info: Entering event queue @ 801681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 802483633000. Starting simulation...
+info: Entering event queue @ 802681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 803483633000. Starting simulation...
+info: Entering event queue @ 803681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 804483633000. Starting simulation...
+info: Entering event queue @ 804681541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 805483633000. Starting simulation...
+info: Entering event queue @ 805681541000. Starting simulation...
switching cpus
-info: Entering event queue @ 805483634000. Starting simulation...
+info: Entering event queue @ 805681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 806483634000. Starting simulation...
+info: Entering event queue @ 806681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 807483634000. Starting simulation...
+info: Entering event queue @ 807681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 808483634000. Starting simulation...
+info: Entering event queue @ 808681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 809483634000. Starting simulation...
+info: Entering event queue @ 809681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 810483634000. Starting simulation...
+info: Entering event queue @ 810681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 811483634000. Starting simulation...
+info: Entering event queue @ 811681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 812483634000. Starting simulation...
+info: Entering event queue @ 812681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 813483634000. Starting simulation...
+info: Entering event queue @ 813681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 814483634000. Starting simulation...
+info: Entering event queue @ 814681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 815483634000. Starting simulation...
+info: Entering event queue @ 815681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 816483634000. Starting simulation...
+info: Entering event queue @ 816681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 817483634000. Starting simulation...
+info: Entering event queue @ 817681548500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 818483634000. Starting simulation...
-info: Entering event queue @ 819219772000. Starting simulation...
+info: Entering event queue @ 818681548500. Starting simulation...
+info: Entering event queue @ 819418118000. Starting simulation...
switching cpus
-info: Entering event queue @ 819219774000. Starting simulation...
+info: Entering event queue @ 819418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 820219774000. Starting simulation...
+info: Entering event queue @ 820418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 821219774000. Starting simulation...
+info: Entering event queue @ 821418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 822219774000. Starting simulation...
+info: Entering event queue @ 822418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 823219774000. Starting simulation...
+info: Entering event queue @ 823418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 824219774000. Starting simulation...
+info: Entering event queue @ 824418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 825219774000. Starting simulation...
+info: Entering event queue @ 825418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 826219774000. Starting simulation...
+info: Entering event queue @ 826418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 827219774000. Starting simulation...
+info: Entering event queue @ 827418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 828219774000. Starting simulation...
+info: Entering event queue @ 828418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 829219774000. Starting simulation...
+info: Entering event queue @ 829418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 830219774000. Starting simulation...
+info: Entering event queue @ 830418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 831219774000. Starting simulation...
+info: Entering event queue @ 831418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 832219774000. Starting simulation...
+info: Entering event queue @ 832418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 833219774000. Starting simulation...
+info: Entering event queue @ 833418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 834219774000. Starting simulation...
+info: Entering event queue @ 834418120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 835219774000. Starting simulation...
+info: Entering event queue @ 835418120000. Starting simulation...
switching cpus
-info: Entering event queue @ 835219775000. Starting simulation...
+info: Entering event queue @ 835418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 836219775000. Starting simulation...
+info: Entering event queue @ 836418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 837219775000. Starting simulation...
+info: Entering event queue @ 837418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 838219775000. Starting simulation...
+info: Entering event queue @ 838418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 839219775000. Starting simulation...
+info: Entering event queue @ 839418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 840219775000. Starting simulation...
+info: Entering event queue @ 840418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 841219775000. Starting simulation...
+info: Entering event queue @ 841418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 842219775000. Starting simulation...
+info: Entering event queue @ 842418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 843219775000. Starting simulation...
+info: Entering event queue @ 843418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 844219775000. Starting simulation...
+info: Entering event queue @ 844418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 845219775000. Starting simulation...
+info: Entering event queue @ 845418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 846219775000. Starting simulation...
+info: Entering event queue @ 846418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 847219775000. Starting simulation...
+info: Entering event queue @ 847418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 848219775000. Starting simulation...
+info: Entering event queue @ 848418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 849219775000. Starting simulation...
+info: Entering event queue @ 849418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 850219775000. Starting simulation...
+info: Entering event queue @ 850418127500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 851219775000. Starting simulation...
-info: Entering event queue @ 851956063000. Starting simulation...
+info: Entering event queue @ 851418127500. Starting simulation...
+info: Entering event queue @ 852153530000. Starting simulation...
switching cpus
-info: Entering event queue @ 851956065000. Starting simulation...
+info: Entering event queue @ 852153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 852956065000. Starting simulation...
+info: Entering event queue @ 853153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 853956065000. Starting simulation...
+info: Entering event queue @ 854153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 854956065000. Starting simulation...
+info: Entering event queue @ 855153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 855956065000. Starting simulation...
+info: Entering event queue @ 856153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 856956065000. Starting simulation...
+info: Entering event queue @ 857153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 857956065000. Starting simulation...
+info: Entering event queue @ 858153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 858956065000. Starting simulation...
+info: Entering event queue @ 859153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 859956065000. Starting simulation...
+info: Entering event queue @ 860153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 860956065000. Starting simulation...
+info: Entering event queue @ 861153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 861956065000. Starting simulation...
+info: Entering event queue @ 862153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 862956065000. Starting simulation...
+info: Entering event queue @ 863153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 863956065000. Starting simulation...
+info: Entering event queue @ 864153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 864956065000. Starting simulation...
+info: Entering event queue @ 865153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 865956065000. Starting simulation...
+info: Entering event queue @ 866153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 866956065000. Starting simulation...
+info: Entering event queue @ 867153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 867956065000. Starting simulation...
+info: Entering event queue @ 868153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 868956065000. Starting simulation...
+info: Entering event queue @ 869153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 869956065000. Starting simulation...
+info: Entering event queue @ 870153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 870956065000. Starting simulation...
+info: Entering event queue @ 871153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 871956065000. Starting simulation...
+info: Entering event queue @ 872153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 872956065000. Starting simulation...
+info: Entering event queue @ 873153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 873956065000. Starting simulation...
+info: Entering event queue @ 874153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 874956065000. Starting simulation...
+info: Entering event queue @ 875153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 875956065000. Starting simulation...
+info: Entering event queue @ 876153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 876956065000. Starting simulation...
+info: Entering event queue @ 877153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 877956065000. Starting simulation...
+info: Entering event queue @ 878153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 878956065000. Starting simulation...
+info: Entering event queue @ 879153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 879956065000. Starting simulation...
+info: Entering event queue @ 880153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 880956065000. Starting simulation...
+info: Entering event queue @ 881153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 881956065000. Starting simulation...
+info: Entering event queue @ 882153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 882956065000. Starting simulation...
+info: Entering event queue @ 883153532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 883956065000. Starting simulation...
-info: Entering event queue @ 884692663000. Starting simulation...
+info: Entering event queue @ 884153532000. Starting simulation...
+info: Entering event queue @ 884890130000. Starting simulation...
switching cpus
-info: Entering event queue @ 884692665000. Starting simulation...
+info: Entering event queue @ 884890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 885692665000. Starting simulation...
+info: Entering event queue @ 885890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 886692665000. Starting simulation...
+info: Entering event queue @ 886890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 887692665000. Starting simulation...
+info: Entering event queue @ 887890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 888692665000. Starting simulation...
+info: Entering event queue @ 888890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 889692665000. Starting simulation...
+info: Entering event queue @ 889890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 890692665000. Starting simulation...
+info: Entering event queue @ 890890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 891692665000. Starting simulation...
+info: Entering event queue @ 891890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 892692665000. Starting simulation...
+info: Entering event queue @ 892890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 893692665000. Starting simulation...
+info: Entering event queue @ 893890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 894692665000. Starting simulation...
+info: Entering event queue @ 894890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 895692665000. Starting simulation...
+info: Entering event queue @ 895890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 896692665000. Starting simulation...
+info: Entering event queue @ 896890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 897692665000. Starting simulation...
+info: Entering event queue @ 897890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 898692665000. Starting simulation...
+info: Entering event queue @ 898890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 899692665000. Starting simulation...
+info: Entering event queue @ 899890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 900692665000. Starting simulation...
+info: Entering event queue @ 900890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 901692665000. Starting simulation...
+info: Entering event queue @ 901890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 902692665000. Starting simulation...
+info: Entering event queue @ 902890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 903692665000. Starting simulation...
+info: Entering event queue @ 903890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 904692665000. Starting simulation...
+info: Entering event queue @ 904890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 905692665000. Starting simulation...
+info: Entering event queue @ 905890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 906692665000. Starting simulation...
+info: Entering event queue @ 906890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 907692665000. Starting simulation...
+info: Entering event queue @ 907890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 908692665000. Starting simulation...
+info: Entering event queue @ 908890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 909692665000. Starting simulation...
+info: Entering event queue @ 909890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 910692665000. Starting simulation...
+info: Entering event queue @ 910890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 911692665000. Starting simulation...
+info: Entering event queue @ 911890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 912692665000. Starting simulation...
+info: Entering event queue @ 912890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 913692665000. Starting simulation...
+info: Entering event queue @ 913890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 914692665000. Starting simulation...
+info: Entering event queue @ 914890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 915692665000. Starting simulation...
+info: Entering event queue @ 915890132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 916692665000. Starting simulation...
-info: Entering event queue @ 917428807000. Starting simulation...
+info: Entering event queue @ 916890132000. Starting simulation...
+info: Entering event queue @ 917626751000. Starting simulation...
switching cpus
-info: Entering event queue @ 917428809000. Starting simulation...
+info: Entering event queue @ 917626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 918428809000. Starting simulation...
+info: Entering event queue @ 918626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 919428809000. Starting simulation...
+info: Entering event queue @ 919626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 920428809000. Starting simulation...
+info: Entering event queue @ 920626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 921428809000. Starting simulation...
+info: Entering event queue @ 921626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 922428809000. Starting simulation...
+info: Entering event queue @ 922626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 923428809000. Starting simulation...
+info: Entering event queue @ 923626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 924428809000. Starting simulation...
+info: Entering event queue @ 924626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 925428809000. Starting simulation...
+info: Entering event queue @ 925626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 926428809000. Starting simulation...
+info: Entering event queue @ 926626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 927428809000. Starting simulation...
+info: Entering event queue @ 927626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 928428809000. Starting simulation...
+info: Entering event queue @ 928626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 929428809000. Starting simulation...
+info: Entering event queue @ 929626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 930428809000. Starting simulation...
+info: Entering event queue @ 930626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 931428809000. Starting simulation...
+info: Entering event queue @ 931626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 932428809000. Starting simulation...
+info: Entering event queue @ 932626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 933428809000. Starting simulation...
+info: Entering event queue @ 933626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 934428809000. Starting simulation...
+info: Entering event queue @ 934626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 935428809000. Starting simulation...
+info: Entering event queue @ 935626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 936428809000. Starting simulation...
+info: Entering event queue @ 936626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 937428809000. Starting simulation...
+info: Entering event queue @ 937626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 938428809000. Starting simulation...
+info: Entering event queue @ 938626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 939428809000. Starting simulation...
+info: Entering event queue @ 939626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 940428809000. Starting simulation...
+info: Entering event queue @ 940626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 941428809000. Starting simulation...
+info: Entering event queue @ 941626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 942428809000. Starting simulation...
+info: Entering event queue @ 942626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 943428809000. Starting simulation...
+info: Entering event queue @ 943626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 944428809000. Starting simulation...
+info: Entering event queue @ 944626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 945428809000. Starting simulation...
+info: Entering event queue @ 945626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 946428809000. Starting simulation...
+info: Entering event queue @ 946626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 947428809000. Starting simulation...
+info: Entering event queue @ 947626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 948428809000. Starting simulation...
+info: Entering event queue @ 948626753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 949428809000. Starting simulation...
-info: Entering event queue @ 950164954000. Starting simulation...
+info: Entering event queue @ 949626753000. Starting simulation...
+info: Entering event queue @ 950363351000. Starting simulation...
switching cpus
-info: Entering event queue @ 950164956000. Starting simulation...
+info: Entering event queue @ 950363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 951164956000. Starting simulation...
+info: Entering event queue @ 951363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 952164956000. Starting simulation...
+info: Entering event queue @ 952363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 953164956000. Starting simulation...
+info: Entering event queue @ 953363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 954164956000. Starting simulation...
+info: Entering event queue @ 954363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 955164956000. Starting simulation...
+info: Entering event queue @ 955363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 956164956000. Starting simulation...
+info: Entering event queue @ 956363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 957164956000. Starting simulation...
+info: Entering event queue @ 957363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 958164956000. Starting simulation...
+info: Entering event queue @ 958363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 959164956000. Starting simulation...
+info: Entering event queue @ 959363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 960164956000. Starting simulation...
+info: Entering event queue @ 960363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 961164956000. Starting simulation...
+info: Entering event queue @ 961363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 962164956000. Starting simulation...
+info: Entering event queue @ 962363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 963164956000. Starting simulation...
+info: Entering event queue @ 963363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 964164956000. Starting simulation...
+info: Entering event queue @ 964363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 965164956000. Starting simulation...
+info: Entering event queue @ 965363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 966164956000. Starting simulation...
+info: Entering event queue @ 966363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 967164956000. Starting simulation...
+info: Entering event queue @ 967363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 968164956000. Starting simulation...
+info: Entering event queue @ 968363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 969164956000. Starting simulation...
+info: Entering event queue @ 969363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 970164956000. Starting simulation...
+info: Entering event queue @ 970363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 971164956000. Starting simulation...
+info: Entering event queue @ 971363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 972164956000. Starting simulation...
+info: Entering event queue @ 972363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 973164956000. Starting simulation...
+info: Entering event queue @ 973363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 974164956000. Starting simulation...
+info: Entering event queue @ 974363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 975164956000. Starting simulation...
+info: Entering event queue @ 975363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 976164956000. Starting simulation...
+info: Entering event queue @ 976363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 977164956000. Starting simulation...
+info: Entering event queue @ 977363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 978164956000. Starting simulation...
+info: Entering event queue @ 978363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 979164956000. Starting simulation...
+info: Entering event queue @ 979363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 980164956000. Starting simulation...
+info: Entering event queue @ 980363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 981164956000. Starting simulation...
+info: Entering event queue @ 981363353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 982164956000. Starting simulation...
-info: Entering event queue @ 982901245000. Starting simulation...
+info: Entering event queue @ 982363353000. Starting simulation...
+info: Entering event queue @ 983098914000. Starting simulation...
switching cpus
-info: Entering event queue @ 982901247000. Starting simulation...
+info: Entering event queue @ 983098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 983901247000. Starting simulation...
+info: Entering event queue @ 984098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 984901247000. Starting simulation...
+info: Entering event queue @ 985098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 985901247000. Starting simulation...
+info: Entering event queue @ 986098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 986901247000. Starting simulation...
+info: Entering event queue @ 987098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 987901247000. Starting simulation...
+info: Entering event queue @ 988098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 988901247000. Starting simulation...
+info: Entering event queue @ 989098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 989901247000. Starting simulation...
+info: Entering event queue @ 990098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 990901247000. Starting simulation...
+info: Entering event queue @ 991098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 991901247000. Starting simulation...
+info: Entering event queue @ 992098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 992901247000. Starting simulation...
+info: Entering event queue @ 993098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 993901247000. Starting simulation...
+info: Entering event queue @ 994098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 994901247000. Starting simulation...
+info: Entering event queue @ 995098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 995901247000. Starting simulation...
+info: Entering event queue @ 996098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 996901247000. Starting simulation...
+info: Entering event queue @ 997098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 997901247000. Starting simulation...
+info: Entering event queue @ 998098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 998901247000. Starting simulation...
+info: Entering event queue @ 999098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 999901247000. Starting simulation...
+info: Entering event queue @ 1000098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1000901247000. Starting simulation...
+info: Entering event queue @ 1001098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1001901247000. Starting simulation...
+info: Entering event queue @ 1002098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1002901247000. Starting simulation...
+info: Entering event queue @ 1003098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1003901247000. Starting simulation...
+info: Entering event queue @ 1004098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1004901247000. Starting simulation...
+info: Entering event queue @ 1005098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1005901247000. Starting simulation...
+info: Entering event queue @ 1006098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1006901247000. Starting simulation...
+info: Entering event queue @ 1007098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1007901247000. Starting simulation...
+info: Entering event queue @ 1008098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1008901247000. Starting simulation...
+info: Entering event queue @ 1009098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1009901247000. Starting simulation...
+info: Entering event queue @ 1010098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1010901247000. Starting simulation...
+info: Entering event queue @ 1011098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1011901247000. Starting simulation...
+info: Entering event queue @ 1012098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1012901247000. Starting simulation...
+info: Entering event queue @ 1013098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1013901247000. Starting simulation...
+info: Entering event queue @ 1014098916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1014901247000. Starting simulation...
-info: Entering event queue @ 1015637389000. Starting simulation...
+info: Entering event queue @ 1015098916000. Starting simulation...
+info: Entering event queue @ 1015835514000. Starting simulation...
switching cpus
-info: Entering event queue @ 1015637391000. Starting simulation...
+info: Entering event queue @ 1015835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1016637391000. Starting simulation...
+info: Entering event queue @ 1016835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1017637391000. Starting simulation...
+info: Entering event queue @ 1017835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1018637391000. Starting simulation...
+info: Entering event queue @ 1018835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1019637391000. Starting simulation...
+info: Entering event queue @ 1019835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1020637391000. Starting simulation...
+info: Entering event queue @ 1020835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1021637391000. Starting simulation...
+info: Entering event queue @ 1021835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1022637391000. Starting simulation...
+info: Entering event queue @ 1022835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1023637391000. Starting simulation...
+info: Entering event queue @ 1023835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1024637391000. Starting simulation...
+info: Entering event queue @ 1024835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1025637391000. Starting simulation...
+info: Entering event queue @ 1025835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1026637391000. Starting simulation...
+info: Entering event queue @ 1026835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1027637391000. Starting simulation...
+info: Entering event queue @ 1027835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1028637391000. Starting simulation...
+info: Entering event queue @ 1028835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1029637391000. Starting simulation...
+info: Entering event queue @ 1029835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1030637391000. Starting simulation...
+info: Entering event queue @ 1030835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1031637391000. Starting simulation...
+info: Entering event queue @ 1031835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1032637391000. Starting simulation...
+info: Entering event queue @ 1032835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1033637391000. Starting simulation...
+info: Entering event queue @ 1033835516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1034637391000. Starting simulation...
+info: Entering event queue @ 1034835516000. Starting simulation...
switching cpus
-info: Entering event queue @ 1034637391500. Starting simulation...
+info: Entering event queue @ 1034835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1035637391500. Starting simulation...
switching cpus
-info: Entering event queue @ 1035637392500. Starting simulation...
+info: Entering event queue @ 1035835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1036637392500. Starting simulation...
+info: Entering event queue @ 1036835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1037637392500. Starting simulation...
+info: Entering event queue @ 1037835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1038637392500. Starting simulation...
+info: Entering event queue @ 1038835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1039637392500. Starting simulation...
+info: Entering event queue @ 1039835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1040637392500. Starting simulation...
+info: Entering event queue @ 1040835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1041637392500. Starting simulation...
+info: Entering event queue @ 1041835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1042637392500. Starting simulation...
+info: Entering event queue @ 1042835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1043637392500. Starting simulation...
+info: Entering event queue @ 1043835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1044637392500. Starting simulation...
+info: Entering event queue @ 1044835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1045637392500. Starting simulation...
+info: Entering event queue @ 1045835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1046637392500. Starting simulation...
+info: Entering event queue @ 1046835523500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1047637392500. Starting simulation...
-info: Entering event queue @ 1048373680000. Starting simulation...
+info: Entering event queue @ 1047835523500. Starting simulation...
+info: Entering event queue @ 1048572135000. Starting simulation...
switching cpus
-info: Entering event queue @ 1048373682000. Starting simulation...
+info: Entering event queue @ 1048572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1049373682000. Starting simulation...
+info: Entering event queue @ 1049572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1050373682000. Starting simulation...
+info: Entering event queue @ 1050572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1051373682000. Starting simulation...
+info: Entering event queue @ 1051572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1052373682000. Starting simulation...
+info: Entering event queue @ 1052572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1053373682000. Starting simulation...
+info: Entering event queue @ 1053572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1054373682000. Starting simulation...
+info: Entering event queue @ 1054572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1055373682000. Starting simulation...
+info: Entering event queue @ 1055572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1056373682000. Starting simulation...
+info: Entering event queue @ 1056572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1057373682000. Starting simulation...
+info: Entering event queue @ 1057572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1058373682000. Starting simulation...
+info: Entering event queue @ 1058572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1059373682000. Starting simulation...
+info: Entering event queue @ 1059572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1060373682000. Starting simulation...
+info: Entering event queue @ 1060572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1061373682000. Starting simulation...
+info: Entering event queue @ 1061572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1062373682000. Starting simulation...
+info: Entering event queue @ 1062572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1063373682000. Starting simulation...
+info: Entering event queue @ 1063572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1064373682000. Starting simulation...
+info: Entering event queue @ 1064572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1065373682000. Starting simulation...
+info: Entering event queue @ 1065572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1066373682000. Starting simulation...
+info: Entering event queue @ 1066572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1067373682000. Starting simulation...
+info: Entering event queue @ 1067572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1068373682000. Starting simulation...
+info: Entering event queue @ 1068572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1069373682000. Starting simulation...
+info: Entering event queue @ 1069572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1070373682000. Starting simulation...
+info: Entering event queue @ 1070572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1071373682000. Starting simulation...
+info: Entering event queue @ 1071572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1072373682000. Starting simulation...
+info: Entering event queue @ 1072572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1073373682000. Starting simulation...
+info: Entering event queue @ 1073572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1074373682000. Starting simulation...
+info: Entering event queue @ 1074572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1075373682000. Starting simulation...
+info: Entering event queue @ 1075572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1076373682000. Starting simulation...
+info: Entering event queue @ 1076572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1077373682000. Starting simulation...
+info: Entering event queue @ 1077572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1078373682000. Starting simulation...
+info: Entering event queue @ 1078572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1079373682000. Starting simulation...
+info: Entering event queue @ 1079572137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1080373682000. Starting simulation...
-info: Entering event queue @ 1081109821000. Starting simulation...
+info: Entering event queue @ 1080572137000. Starting simulation...
+info: Entering event queue @ 1081307547000. Starting simulation...
switching cpus
-info: Entering event queue @ 1081109823000. Starting simulation...
+info: Entering event queue @ 1081307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1082109823000. Starting simulation...
+info: Entering event queue @ 1082307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1083109823000. Starting simulation...
+info: Entering event queue @ 1083307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1084109823000. Starting simulation...
+info: Entering event queue @ 1084307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1085109823000. Starting simulation...
+info: Entering event queue @ 1085307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1086109823000. Starting simulation...
+info: Entering event queue @ 1086307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1087109823000. Starting simulation...
+info: Entering event queue @ 1087307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1088109823000. Starting simulation...
+info: Entering event queue @ 1088307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1089109823000. Starting simulation...
+info: Entering event queue @ 1089307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1090109823000. Starting simulation...
+info: Entering event queue @ 1090307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1091109823000. Starting simulation...
+info: Entering event queue @ 1091307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1092109823000. Starting simulation...
+info: Entering event queue @ 1092307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1093109823000. Starting simulation...
+info: Entering event queue @ 1093307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1094109823000. Starting simulation...
+info: Entering event queue @ 1094307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1095109823000. Starting simulation...
+info: Entering event queue @ 1095307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1096109823000. Starting simulation...
+info: Entering event queue @ 1096307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1097109823000. Starting simulation...
+info: Entering event queue @ 1097307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1098109823000. Starting simulation...
+info: Entering event queue @ 1098307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1099109823000. Starting simulation...
+info: Entering event queue @ 1099307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1100109823000. Starting simulation...
+info: Entering event queue @ 1100307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1101109823000. Starting simulation...
+info: Entering event queue @ 1101307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1102109823000. Starting simulation...
+info: Entering event queue @ 1102307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1103109823000. Starting simulation...
+info: Entering event queue @ 1103307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1104109823000. Starting simulation...
+info: Entering event queue @ 1104307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1105109823000. Starting simulation...
+info: Entering event queue @ 1105307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1106109823000. Starting simulation...
+info: Entering event queue @ 1106307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1107109823000. Starting simulation...
+info: Entering event queue @ 1107307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1108109823000. Starting simulation...
+info: Entering event queue @ 1108307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1109109823000. Starting simulation...
+info: Entering event queue @ 1109307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1110109823000. Starting simulation...
+info: Entering event queue @ 1110307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1111109823000. Starting simulation...
+info: Entering event queue @ 1111307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1112109823000. Starting simulation...
+info: Entering event queue @ 1112307549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1113109823000. Starting simulation...
-info: Entering event queue @ 1113846115000. Starting simulation...
+info: Entering event queue @ 1113307549000. Starting simulation...
+info: Entering event queue @ 1114044147000. Starting simulation...
switching cpus
-info: Entering event queue @ 1113846117000. Starting simulation...
+info: Entering event queue @ 1114044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1114846117000. Starting simulation...
+info: Entering event queue @ 1115044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1115846117000. Starting simulation...
+info: Entering event queue @ 1116044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1116846117000. Starting simulation...
+info: Entering event queue @ 1117044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1117846117000. Starting simulation...
+info: Entering event queue @ 1118044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1118846117000. Starting simulation...
+info: Entering event queue @ 1119044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1119846117000. Starting simulation...
+info: Entering event queue @ 1120044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1120846117000. Starting simulation...
+info: Entering event queue @ 1121044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1121846117000. Starting simulation...
+info: Entering event queue @ 1122044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1122846117000. Starting simulation...
+info: Entering event queue @ 1123044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1123846117000. Starting simulation...
+info: Entering event queue @ 1124044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1124846117000. Starting simulation...
+info: Entering event queue @ 1125044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1125846117000. Starting simulation...
+info: Entering event queue @ 1126044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1126846117000. Starting simulation...
+info: Entering event queue @ 1127044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1127846117000. Starting simulation...
+info: Entering event queue @ 1128044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1128846117000. Starting simulation...
+info: Entering event queue @ 1129044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1129846117000. Starting simulation...
+info: Entering event queue @ 1130044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1130846117000. Starting simulation...
+info: Entering event queue @ 1131044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1131846117000. Starting simulation...
+info: Entering event queue @ 1132044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1132846117000. Starting simulation...
+info: Entering event queue @ 1133044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1133846117000. Starting simulation...
+info: Entering event queue @ 1134044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1134846117000. Starting simulation...
+info: Entering event queue @ 1135044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1135846117000. Starting simulation...
+info: Entering event queue @ 1136044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1136846117000. Starting simulation...
+info: Entering event queue @ 1137044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1137846117000. Starting simulation...
+info: Entering event queue @ 1138044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1138846117000. Starting simulation...
+info: Entering event queue @ 1139044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1139846117000. Starting simulation...
+info: Entering event queue @ 1140044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1140846117000. Starting simulation...
+info: Entering event queue @ 1141044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1141846117000. Starting simulation...
+info: Entering event queue @ 1142044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1142846117000. Starting simulation...
+info: Entering event queue @ 1143044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1143846117000. Starting simulation...
+info: Entering event queue @ 1144044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1144846117000. Starting simulation...
+info: Entering event queue @ 1145044149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1145846117000. Starting simulation...
-info: Entering event queue @ 1146582256000. Starting simulation...
+info: Entering event queue @ 1146044149000. Starting simulation...
+info: Entering event queue @ 1146780726000. Starting simulation...
switching cpus
-info: Entering event queue @ 1146582258000. Starting simulation...
+info: Entering event queue @ 1146780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1147582258000. Starting simulation...
+info: Entering event queue @ 1147780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1148582258000. Starting simulation...
+info: Entering event queue @ 1148780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1149582258000. Starting simulation...
+info: Entering event queue @ 1149780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1150582258000. Starting simulation...
+info: Entering event queue @ 1150780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1151582258000. Starting simulation...
+info: Entering event queue @ 1151780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1152582258000. Starting simulation...
+info: Entering event queue @ 1152780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1153582258000. Starting simulation...
+info: Entering event queue @ 1153780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1154582258000. Starting simulation...
+info: Entering event queue @ 1154780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1155582258000. Starting simulation...
+info: Entering event queue @ 1155780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1156582258000. Starting simulation...
+info: Entering event queue @ 1156780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1157582258000. Starting simulation...
+info: Entering event queue @ 1157780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1158582258000. Starting simulation...
+info: Entering event queue @ 1158780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1159582258000. Starting simulation...
+info: Entering event queue @ 1159780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1160582258000. Starting simulation...
+info: Entering event queue @ 1160780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1161582258000. Starting simulation...
+info: Entering event queue @ 1161780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1162582258000. Starting simulation...
+info: Entering event queue @ 1162780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1163582258000. Starting simulation...
+info: Entering event queue @ 1163780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1164582258000. Starting simulation...
+info: Entering event queue @ 1164780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1165582258000. Starting simulation...
+info: Entering event queue @ 1165780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1166582258000. Starting simulation...
+info: Entering event queue @ 1166780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1167582258000. Starting simulation...
+info: Entering event queue @ 1167780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1168582258000. Starting simulation...
+info: Entering event queue @ 1168780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1169582258000. Starting simulation...
+info: Entering event queue @ 1169780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1170582258000. Starting simulation...
+info: Entering event queue @ 1170780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1171582258000. Starting simulation...
+info: Entering event queue @ 1171780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1172582258000. Starting simulation...
+info: Entering event queue @ 1172780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1173582258000. Starting simulation...
+info: Entering event queue @ 1173780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1174582258000. Starting simulation...
+info: Entering event queue @ 1174780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1175582258000. Starting simulation...
+info: Entering event queue @ 1175780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1176582258000. Starting simulation...
+info: Entering event queue @ 1176780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1177582258000. Starting simulation...
+info: Entering event queue @ 1177780728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1178582258000. Starting simulation...
-info: Entering event queue @ 1179318856000. Starting simulation...
+info: Entering event queue @ 1178780728000. Starting simulation...
+info: Entering event queue @ 1179516138000. Starting simulation...
switching cpus
-info: Entering event queue @ 1179318858000. Starting simulation...
+info: Entering event queue @ 1179516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1180318858000. Starting simulation...
+info: Entering event queue @ 1180516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1181318858000. Starting simulation...
+info: Entering event queue @ 1181516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1182318858000. Starting simulation...
+info: Entering event queue @ 1182516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1183318858000. Starting simulation...
+info: Entering event queue @ 1183516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1184318858000. Starting simulation...
+info: Entering event queue @ 1184516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1185318858000. Starting simulation...
+info: Entering event queue @ 1185516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1186318858000. Starting simulation...
+info: Entering event queue @ 1186516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1187318858000. Starting simulation...
+info: Entering event queue @ 1187516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1188318858000. Starting simulation...
+info: Entering event queue @ 1188516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1189318858000. Starting simulation...
+info: Entering event queue @ 1189516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1190318858000. Starting simulation...
+info: Entering event queue @ 1190516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1191318858000. Starting simulation...
+info: Entering event queue @ 1191516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1192318858000. Starting simulation...
+info: Entering event queue @ 1192516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1193318858000. Starting simulation...
+info: Entering event queue @ 1193516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1194318858000. Starting simulation...
+info: Entering event queue @ 1194516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1195318858000. Starting simulation...
+info: Entering event queue @ 1195516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1196318858000. Starting simulation...
+info: Entering event queue @ 1196516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1197318858000. Starting simulation...
+info: Entering event queue @ 1197516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1198318858000. Starting simulation...
+info: Entering event queue @ 1198516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1199318858000. Starting simulation...
+info: Entering event queue @ 1199516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1200318858000. Starting simulation...
+info: Entering event queue @ 1200516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1201318858000. Starting simulation...
+info: Entering event queue @ 1201516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1202318858000. Starting simulation...
+info: Entering event queue @ 1202516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1203318858000. Starting simulation...
+info: Entering event queue @ 1203516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1204318858000. Starting simulation...
+info: Entering event queue @ 1204516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1205318858000. Starting simulation...
+info: Entering event queue @ 1205516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1206318858000. Starting simulation...
+info: Entering event queue @ 1206516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1207318858000. Starting simulation...
+info: Entering event queue @ 1207516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1208318858000. Starting simulation...
+info: Entering event queue @ 1208516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1209318858000. Starting simulation...
+info: Entering event queue @ 1209516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1210318858000. Starting simulation...
+info: Entering event queue @ 1210516140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1211318858000. Starting simulation...
-info: Entering event queue @ 1212055147000. Starting simulation...
+info: Entering event queue @ 1211516140000. Starting simulation...
+info: Entering event queue @ 1212252738000. Starting simulation...
switching cpus
-info: Entering event queue @ 1212055149000. Starting simulation...
+info: Entering event queue @ 1212252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1213055149000. Starting simulation...
+info: Entering event queue @ 1213252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1214055149000. Starting simulation...
+info: Entering event queue @ 1214252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1215055149000. Starting simulation...
+info: Entering event queue @ 1215252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1216055149000. Starting simulation...
+info: Entering event queue @ 1216252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1217055149000. Starting simulation...
+info: Entering event queue @ 1217252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1218055149000. Starting simulation...
+info: Entering event queue @ 1218252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1219055149000. Starting simulation...
+info: Entering event queue @ 1219252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1220055149000. Starting simulation...
+info: Entering event queue @ 1220252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1221055149000. Starting simulation...
+info: Entering event queue @ 1221252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1222055149000. Starting simulation...
+info: Entering event queue @ 1222252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1223055149000. Starting simulation...
+info: Entering event queue @ 1223252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1224055149000. Starting simulation...
+info: Entering event queue @ 1224252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1225055149000. Starting simulation...
+info: Entering event queue @ 1225252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1226055149000. Starting simulation...
+info: Entering event queue @ 1226252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1227055149000. Starting simulation...
+info: Entering event queue @ 1227252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1228055149000. Starting simulation...
+info: Entering event queue @ 1228252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1229055149000. Starting simulation...
+info: Entering event queue @ 1229252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1230055149000. Starting simulation...
+info: Entering event queue @ 1230252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1231055149000. Starting simulation...
+info: Entering event queue @ 1231252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1232055149000. Starting simulation...
+info: Entering event queue @ 1232252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1233055149000. Starting simulation...
+info: Entering event queue @ 1233252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1234055149000. Starting simulation...
+info: Entering event queue @ 1234252740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1235055149000. Starting simulation...
+info: Entering event queue @ 1235252740000. Starting simulation...
switching cpus
-info: Entering event queue @ 1235055150000. Starting simulation...
+info: Entering event queue @ 1235252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1236055150000. Starting simulation...
+info: Entering event queue @ 1236252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1237055150000. Starting simulation...
+info: Entering event queue @ 1237252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1238055150000. Starting simulation...
+info: Entering event queue @ 1238252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1239055150000. Starting simulation...
+info: Entering event queue @ 1239252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1240055150000. Starting simulation...
+info: Entering event queue @ 1240252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1241055150000. Starting simulation...
+info: Entering event queue @ 1241252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1242055150000. Starting simulation...
+info: Entering event queue @ 1242252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1243055150000. Starting simulation...
+info: Entering event queue @ 1243252747500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1244055150000. Starting simulation...
-info: Entering event queue @ 1244791291000. Starting simulation...
+info: Entering event queue @ 1244252747500. Starting simulation...
+info: Entering event queue @ 1244989355000. Starting simulation...
switching cpus
-info: Entering event queue @ 1244791293000. Starting simulation...
+info: Entering event queue @ 1244989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1245791293000. Starting simulation...
+info: Entering event queue @ 1245989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1246791293000. Starting simulation...
+info: Entering event queue @ 1246989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1247791293000. Starting simulation...
+info: Entering event queue @ 1247989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1248791293000. Starting simulation...
+info: Entering event queue @ 1248989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1249791293000. Starting simulation...
+info: Entering event queue @ 1249989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1250791293000. Starting simulation...
+info: Entering event queue @ 1250989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1251791293000. Starting simulation...
+info: Entering event queue @ 1251989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1252791293000. Starting simulation...
+info: Entering event queue @ 1252989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1253791293000. Starting simulation...
+info: Entering event queue @ 1253989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1254791293000. Starting simulation...
+info: Entering event queue @ 1254989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1255791293000. Starting simulation...
+info: Entering event queue @ 1255989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1256791293000. Starting simulation...
+info: Entering event queue @ 1256989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1257791293000. Starting simulation...
+info: Entering event queue @ 1257989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1258791293000. Starting simulation...
+info: Entering event queue @ 1258989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1259791293000. Starting simulation...
+info: Entering event queue @ 1259989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1260791293000. Starting simulation...
+info: Entering event queue @ 1260989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1261791293000. Starting simulation...
+info: Entering event queue @ 1261989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1262791293000. Starting simulation...
+info: Entering event queue @ 1262989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1263791293000. Starting simulation...
+info: Entering event queue @ 1263989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1264791293000. Starting simulation...
+info: Entering event queue @ 1264989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1265791293000. Starting simulation...
+info: Entering event queue @ 1265989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1266791293000. Starting simulation...
+info: Entering event queue @ 1266989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1267791293000. Starting simulation...
+info: Entering event queue @ 1267989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1268791293000. Starting simulation...
+info: Entering event queue @ 1268989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1269791293000. Starting simulation...
+info: Entering event queue @ 1269989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1270791293000. Starting simulation...
+info: Entering event queue @ 1270989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1271791293000. Starting simulation...
+info: Entering event queue @ 1271989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1272791293000. Starting simulation...
+info: Entering event queue @ 1272989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1273791293000. Starting simulation...
+info: Entering event queue @ 1273989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1274791293000. Starting simulation...
+info: Entering event queue @ 1274989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1275791293000. Starting simulation...
+info: Entering event queue @ 1275989357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1276791293000. Starting simulation...
-info: Entering event queue @ 1277527582000. Starting simulation...
+info: Entering event queue @ 1276989357000. Starting simulation...
+info: Entering event queue @ 1277724922000. Starting simulation...
switching cpus
-info: Entering event queue @ 1277527584000. Starting simulation...
+info: Entering event queue @ 1277724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1278527584000. Starting simulation...
+info: Entering event queue @ 1278724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1279527584000. Starting simulation...
+info: Entering event queue @ 1279724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1280527584000. Starting simulation...
+info: Entering event queue @ 1280724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1281527584000. Starting simulation...
+info: Entering event queue @ 1281724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1282527584000. Starting simulation...
+info: Entering event queue @ 1282724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1283527584000. Starting simulation...
+info: Entering event queue @ 1283724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1284527584000. Starting simulation...
+info: Entering event queue @ 1284724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1285527584000. Starting simulation...
+info: Entering event queue @ 1285724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1286527584000. Starting simulation...
+info: Entering event queue @ 1286724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1287527584000. Starting simulation...
+info: Entering event queue @ 1287724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1288527584000. Starting simulation...
+info: Entering event queue @ 1288724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1289527584000. Starting simulation...
+info: Entering event queue @ 1289724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1290527584000. Starting simulation...
+info: Entering event queue @ 1290724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1291527584000. Starting simulation...
+info: Entering event queue @ 1291724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1292527584000. Starting simulation...
+info: Entering event queue @ 1292724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1293527584000. Starting simulation...
+info: Entering event queue @ 1293724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1294527584000. Starting simulation...
+info: Entering event queue @ 1294724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1295527584000. Starting simulation...
+info: Entering event queue @ 1295724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1296527584000. Starting simulation...
+info: Entering event queue @ 1296724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1297527584000. Starting simulation...
+info: Entering event queue @ 1297724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1298527584000. Starting simulation...
+info: Entering event queue @ 1298724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1299527584000. Starting simulation...
+info: Entering event queue @ 1299724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1300527584000. Starting simulation...
+info: Entering event queue @ 1300724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1301527584000. Starting simulation...
+info: Entering event queue @ 1301724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1302527584000. Starting simulation...
+info: Entering event queue @ 1302724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1303527584000. Starting simulation...
+info: Entering event queue @ 1303724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1304527584000. Starting simulation...
+info: Entering event queue @ 1304724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1305527584000. Starting simulation...
+info: Entering event queue @ 1305724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1306527584000. Starting simulation...
+info: Entering event queue @ 1306724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1307527584000. Starting simulation...
+info: Entering event queue @ 1307724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1308527584000. Starting simulation...
+info: Entering event queue @ 1308724924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1309527584000. Starting simulation...
-info: Entering event queue @ 1310263726000. Starting simulation...
+info: Entering event queue @ 1309724924000. Starting simulation...
+info: Entering event queue @ 1310461522000. Starting simulation...
switching cpus
-info: Entering event queue @ 1310263728000. Starting simulation...
+info: Entering event queue @ 1310461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1311263728000. Starting simulation...
+info: Entering event queue @ 1311461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1312263728000. Starting simulation...
+info: Entering event queue @ 1312461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1313263728000. Starting simulation...
+info: Entering event queue @ 1313461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1314263728000. Starting simulation...
+info: Entering event queue @ 1314461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1315263728000. Starting simulation...
+info: Entering event queue @ 1315461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1316263728000. Starting simulation...
+info: Entering event queue @ 1316461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1317263728000. Starting simulation...
+info: Entering event queue @ 1317461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1318263728000. Starting simulation...
+info: Entering event queue @ 1318461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1319263728000. Starting simulation...
+info: Entering event queue @ 1319461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1320263728000. Starting simulation...
+info: Entering event queue @ 1320461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1321263728000. Starting simulation...
+info: Entering event queue @ 1321461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1322263728000. Starting simulation...
+info: Entering event queue @ 1322461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1323263728000. Starting simulation...
+info: Entering event queue @ 1323461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1324263728000. Starting simulation...
+info: Entering event queue @ 1324461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1325263728000. Starting simulation...
+info: Entering event queue @ 1325461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1326263728000. Starting simulation...
+info: Entering event queue @ 1326461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1327263728000. Starting simulation...
+info: Entering event queue @ 1327461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1328263728000. Starting simulation...
+info: Entering event queue @ 1328461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1329263728000. Starting simulation...
+info: Entering event queue @ 1329461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1330263728000. Starting simulation...
+info: Entering event queue @ 1330461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1331263728000. Starting simulation...
+info: Entering event queue @ 1331461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1332263728000. Starting simulation...
+info: Entering event queue @ 1332461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1333263728000. Starting simulation...
+info: Entering event queue @ 1333461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1334263728000. Starting simulation...
+info: Entering event queue @ 1334461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1335263728000. Starting simulation...
+info: Entering event queue @ 1335461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1336263728000. Starting simulation...
+info: Entering event queue @ 1336461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1337263728000. Starting simulation...
+info: Entering event queue @ 1337461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1338263728000. Starting simulation...
+info: Entering event queue @ 1338461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1339263728000. Starting simulation...
+info: Entering event queue @ 1339461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1340263728000. Starting simulation...
+info: Entering event queue @ 1340461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1341263728000. Starting simulation...
+info: Entering event queue @ 1341461524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1342263728000. Starting simulation...
-info: Entering event queue @ 1342999873000. Starting simulation...
+info: Entering event queue @ 1342461524000. Starting simulation...
+info: Entering event queue @ 1343198143000. Starting simulation...
switching cpus
-info: Entering event queue @ 1342999875000. Starting simulation...
+info: Entering event queue @ 1343198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1343999875000. Starting simulation...
+info: Entering event queue @ 1344198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1344999875000. Starting simulation...
+info: Entering event queue @ 1345198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1345999875000. Starting simulation...
+info: Entering event queue @ 1346198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1346999875000. Starting simulation...
+info: Entering event queue @ 1347198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1347999875000. Starting simulation...
+info: Entering event queue @ 1348198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1348999875000. Starting simulation...
+info: Entering event queue @ 1349198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1349999875000. Starting simulation...
+info: Entering event queue @ 1350198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1350999875000. Starting simulation...
+info: Entering event queue @ 1351198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1351999875000. Starting simulation...
+info: Entering event queue @ 1352198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1352999875000. Starting simulation...
+info: Entering event queue @ 1353198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1353999875000. Starting simulation...
+info: Entering event queue @ 1354198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1354999875000. Starting simulation...
+info: Entering event queue @ 1355198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1355999875000. Starting simulation...
+info: Entering event queue @ 1356198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1356999875000. Starting simulation...
+info: Entering event queue @ 1357198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1357999875000. Starting simulation...
+info: Entering event queue @ 1358198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1358999875000. Starting simulation...
+info: Entering event queue @ 1359198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1359999875000. Starting simulation...
+info: Entering event queue @ 1360198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1360999875000. Starting simulation...
+info: Entering event queue @ 1361198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1361999875000. Starting simulation...
+info: Entering event queue @ 1362198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1362999875000. Starting simulation...
+info: Entering event queue @ 1363198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1363999875000. Starting simulation...
+info: Entering event queue @ 1364198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1364999875000. Starting simulation...
+info: Entering event queue @ 1365198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1365999875000. Starting simulation...
+info: Entering event queue @ 1366198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1366999875000. Starting simulation...
+info: Entering event queue @ 1367198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1367999875000. Starting simulation...
+info: Entering event queue @ 1368198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1368999875000. Starting simulation...
+info: Entering event queue @ 1369198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1369999875000. Starting simulation...
+info: Entering event queue @ 1370198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1370999875000. Starting simulation...
+info: Entering event queue @ 1371198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1371999875000. Starting simulation...
+info: Entering event queue @ 1372198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1372999875000. Starting simulation...
+info: Entering event queue @ 1373198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1373999875000. Starting simulation...
+info: Entering event queue @ 1374198145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1374999875000. Starting simulation...
-info: Entering event queue @ 1375736473000. Starting simulation...
+info: Entering event queue @ 1375198145000. Starting simulation...
+info: Entering event queue @ 1375934743000. Starting simulation...
switching cpus
-info: Entering event queue @ 1375736475000. Starting simulation...
+info: Entering event queue @ 1375934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1376736475000. Starting simulation...
+info: Entering event queue @ 1376934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1377736475000. Starting simulation...
+info: Entering event queue @ 1377934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1378736475000. Starting simulation...
+info: Entering event queue @ 1378934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1379736475000. Starting simulation...
+info: Entering event queue @ 1379934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1380736475000. Starting simulation...
+info: Entering event queue @ 1380934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1381736475000. Starting simulation...
+info: Entering event queue @ 1381934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1382736475000. Starting simulation...
+info: Entering event queue @ 1382934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1383736475000. Starting simulation...
+info: Entering event queue @ 1383934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1384736475000. Starting simulation...
+info: Entering event queue @ 1384934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1385736475000. Starting simulation...
+info: Entering event queue @ 1385934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1386736475000. Starting simulation...
+info: Entering event queue @ 1386934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1387736475000. Starting simulation...
+info: Entering event queue @ 1387934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1388736475000. Starting simulation...
+info: Entering event queue @ 1388934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1389736475000. Starting simulation...
+info: Entering event queue @ 1389934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1390736475000. Starting simulation...
+info: Entering event queue @ 1390934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1391736475000. Starting simulation...
+info: Entering event queue @ 1391934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1392736475000. Starting simulation...
+info: Entering event queue @ 1392934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1393736475000. Starting simulation...
+info: Entering event queue @ 1393934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1394736475000. Starting simulation...
+info: Entering event queue @ 1394934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1395736475000. Starting simulation...
+info: Entering event queue @ 1395934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1396736475000. Starting simulation...
+info: Entering event queue @ 1396934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1397736475000. Starting simulation...
+info: Entering event queue @ 1397934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1398736475000. Starting simulation...
+info: Entering event queue @ 1398934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1399736475000. Starting simulation...
+info: Entering event queue @ 1399934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1400736475000. Starting simulation...
+info: Entering event queue @ 1400934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1401736475000. Starting simulation...
+info: Entering event queue @ 1401934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1402736475000. Starting simulation...
+info: Entering event queue @ 1402934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1403736475000. Starting simulation...
+info: Entering event queue @ 1403934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1404736475000. Starting simulation...
+info: Entering event queue @ 1404934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1405736475000. Starting simulation...
+info: Entering event queue @ 1405934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1406736475000. Starting simulation...
+info: Entering event queue @ 1406934745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1407736475000. Starting simulation...
-info: Entering event queue @ 1408472305000. Starting simulation...
+info: Entering event queue @ 1407934745000. Starting simulation...
+info: Entering event queue @ 1408670155000. Starting simulation...
switching cpus
-info: Entering event queue @ 1408472307000. Starting simulation...
+info: Entering event queue @ 1408670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1409472307000. Starting simulation...
+info: Entering event queue @ 1409670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1410472307000. Starting simulation...
+info: Entering event queue @ 1410670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1411472307000. Starting simulation...
+info: Entering event queue @ 1411670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1412472307000. Starting simulation...
+info: Entering event queue @ 1412670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1413472307000. Starting simulation...
+info: Entering event queue @ 1413670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1414472307000. Starting simulation...
+info: Entering event queue @ 1414670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1415472307000. Starting simulation...
+info: Entering event queue @ 1415670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1416472307000. Starting simulation...
+info: Entering event queue @ 1416670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1417472307000. Starting simulation...
+info: Entering event queue @ 1417670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1418472307000. Starting simulation...
+info: Entering event queue @ 1418670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1419472307000. Starting simulation...
+info: Entering event queue @ 1419670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1420472307000. Starting simulation...
+info: Entering event queue @ 1420670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1421472307000. Starting simulation...
+info: Entering event queue @ 1421670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1422472307000. Starting simulation...
+info: Entering event queue @ 1422670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1423472307000. Starting simulation...
+info: Entering event queue @ 1423670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1424472307000. Starting simulation...
+info: Entering event queue @ 1424670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1425472307000. Starting simulation...
+info: Entering event queue @ 1425670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1426472307000. Starting simulation...
+info: Entering event queue @ 1426670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1427472307000. Starting simulation...
+info: Entering event queue @ 1427670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1428472307000. Starting simulation...
+info: Entering event queue @ 1428670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1429472307000. Starting simulation...
+info: Entering event queue @ 1429670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1430472307000. Starting simulation...
+info: Entering event queue @ 1430670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1431472307000. Starting simulation...
+info: Entering event queue @ 1431670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1432472307000. Starting simulation...
+info: Entering event queue @ 1432670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1433472307000. Starting simulation...
+info: Entering event queue @ 1433670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1434472307000. Starting simulation...
+info: Entering event queue @ 1434670157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1435472307000. Starting simulation...
+info: Entering event queue @ 1435670157000. Starting simulation...
switching cpus
-info: Entering event queue @ 1435472308000. Starting simulation...
+info: Entering event queue @ 1435670164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1436472308000. Starting simulation...
+info: Entering event queue @ 1436670164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1437472308000. Starting simulation...
+info: Entering event queue @ 1437670164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1438472308000. Starting simulation...
+info: Entering event queue @ 1438670164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1439472308000. Starting simulation...
+info: Entering event queue @ 1439670164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1440472308000. Starting simulation...
-info: Entering event queue @ 1441208905000. Starting simulation...
+info: Entering event queue @ 1440670164500. Starting simulation...
+info: Entering event queue @ 1441406755000. Starting simulation...
switching cpus
-info: Entering event queue @ 1441208907000. Starting simulation...
+info: Entering event queue @ 1441406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1442208907000. Starting simulation...
+info: Entering event queue @ 1442406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1443208907000. Starting simulation...
+info: Entering event queue @ 1443406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1444208907000. Starting simulation...
+info: Entering event queue @ 1444406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1445208907000. Starting simulation...
+info: Entering event queue @ 1445406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1446208907000. Starting simulation...
+info: Entering event queue @ 1446406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1447208907000. Starting simulation...
+info: Entering event queue @ 1447406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1448208907000. Starting simulation...
+info: Entering event queue @ 1448406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1449208907000. Starting simulation...
+info: Entering event queue @ 1449406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1450208907000. Starting simulation...
+info: Entering event queue @ 1450406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1451208907000. Starting simulation...
+info: Entering event queue @ 1451406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1452208907000. Starting simulation...
+info: Entering event queue @ 1452406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1453208907000. Starting simulation...
+info: Entering event queue @ 1453406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1454208907000. Starting simulation...
+info: Entering event queue @ 1454406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1455208907000. Starting simulation...
+info: Entering event queue @ 1455406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1456208907000. Starting simulation...
+info: Entering event queue @ 1456406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1457208907000. Starting simulation...
+info: Entering event queue @ 1457406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1458208907000. Starting simulation...
+info: Entering event queue @ 1458406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1459208907000. Starting simulation...
+info: Entering event queue @ 1459406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1460208907000. Starting simulation...
+info: Entering event queue @ 1460406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1461208907000. Starting simulation...
+info: Entering event queue @ 1461406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1462208907000. Starting simulation...
+info: Entering event queue @ 1462406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1463208907000. Starting simulation...
+info: Entering event queue @ 1463406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1464208907000. Starting simulation...
+info: Entering event queue @ 1464406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1465208907000. Starting simulation...
+info: Entering event queue @ 1465406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1466208907000. Starting simulation...
+info: Entering event queue @ 1466406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1467208907000. Starting simulation...
+info: Entering event queue @ 1467406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1468208907000. Starting simulation...
+info: Entering event queue @ 1468406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1469208907000. Starting simulation...
+info: Entering event queue @ 1469406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1470208907000. Starting simulation...
+info: Entering event queue @ 1470406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1471208907000. Starting simulation...
+info: Entering event queue @ 1471406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1472208907000. Starting simulation...
+info: Entering event queue @ 1472406757000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1473208907000. Starting simulation...
-info: Entering event queue @ 1473945196000. Starting simulation...
+info: Entering event queue @ 1473406757000. Starting simulation...
+info: Entering event queue @ 1474143334000. Starting simulation...
switching cpus
-info: Entering event queue @ 1473945198000. Starting simulation...
+info: Entering event queue @ 1474143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1474945198000. Starting simulation...
+info: Entering event queue @ 1475143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1475945198000. Starting simulation...
+info: Entering event queue @ 1476143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1476945198000. Starting simulation...
+info: Entering event queue @ 1477143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1477945198000. Starting simulation...
+info: Entering event queue @ 1478143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1478945198000. Starting simulation...
+info: Entering event queue @ 1479143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1479945198000. Starting simulation...
+info: Entering event queue @ 1480143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1480945198000. Starting simulation...
+info: Entering event queue @ 1481143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1481945198000. Starting simulation...
+info: Entering event queue @ 1482143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1482945198000. Starting simulation...
+info: Entering event queue @ 1483143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1483945198000. Starting simulation...
+info: Entering event queue @ 1484143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1484945198000. Starting simulation...
+info: Entering event queue @ 1485143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1485945198000. Starting simulation...
+info: Entering event queue @ 1486143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1486945198000. Starting simulation...
+info: Entering event queue @ 1487143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1487945198000. Starting simulation...
+info: Entering event queue @ 1488143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1488945198000. Starting simulation...
+info: Entering event queue @ 1489143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1489945198000. Starting simulation...
+info: Entering event queue @ 1490143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1490945198000. Starting simulation...
+info: Entering event queue @ 1491143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1491945198000. Starting simulation...
+info: Entering event queue @ 1492143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1492945198000. Starting simulation...
+info: Entering event queue @ 1493143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1493945198000. Starting simulation...
+info: Entering event queue @ 1494143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1494945198000. Starting simulation...
+info: Entering event queue @ 1495143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1495945198000. Starting simulation...
+info: Entering event queue @ 1496143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1496945198000. Starting simulation...
+info: Entering event queue @ 1497143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1497945198000. Starting simulation...
+info: Entering event queue @ 1498143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1498945198000. Starting simulation...
+info: Entering event queue @ 1499143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1499945198000. Starting simulation...
+info: Entering event queue @ 1500143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1500945198000. Starting simulation...
+info: Entering event queue @ 1501143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1501945198000. Starting simulation...
+info: Entering event queue @ 1502143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1502945198000. Starting simulation...
+info: Entering event queue @ 1503143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1503945198000. Starting simulation...
+info: Entering event queue @ 1504143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1504945198000. Starting simulation...
+info: Entering event queue @ 1505143336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1505945198000. Starting simulation...
-info: Entering event queue @ 1506681337000. Starting simulation...
+info: Entering event queue @ 1506143336000. Starting simulation...
+info: Entering event queue @ 1506878939000. Starting simulation...
switching cpus
-info: Entering event queue @ 1506681339000. Starting simulation...
+info: Entering event queue @ 1506878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1507681339000. Starting simulation...
+info: Entering event queue @ 1507878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1508681339000. Starting simulation...
+info: Entering event queue @ 1508878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1509681339000. Starting simulation...
+info: Entering event queue @ 1509878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1510681339000. Starting simulation...
+info: Entering event queue @ 1510878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1511681339000. Starting simulation...
+info: Entering event queue @ 1511878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1512681339000. Starting simulation...
+info: Entering event queue @ 1512878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1513681339000. Starting simulation...
+info: Entering event queue @ 1513878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1514681339000. Starting simulation...
+info: Entering event queue @ 1514878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1515681339000. Starting simulation...
+info: Entering event queue @ 1515878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1516681339000. Starting simulation...
+info: Entering event queue @ 1516878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1517681339000. Starting simulation...
+info: Entering event queue @ 1517878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1518681339000. Starting simulation...
+info: Entering event queue @ 1518878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1519681339000. Starting simulation...
+info: Entering event queue @ 1519878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1520681339000. Starting simulation...
+info: Entering event queue @ 1520878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1521681339000. Starting simulation...
+info: Entering event queue @ 1521878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1522681339000. Starting simulation...
+info: Entering event queue @ 1522878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1523681339000. Starting simulation...
+info: Entering event queue @ 1523878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1524681339000. Starting simulation...
+info: Entering event queue @ 1524878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1525681339000. Starting simulation...
+info: Entering event queue @ 1525878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1526681339000. Starting simulation...
+info: Entering event queue @ 1526878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1527681339000. Starting simulation...
+info: Entering event queue @ 1527878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1528681339000. Starting simulation...
+info: Entering event queue @ 1528878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1529681339000. Starting simulation...
+info: Entering event queue @ 1529878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1530681339000. Starting simulation...
+info: Entering event queue @ 1530878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1531681339000. Starting simulation...
+info: Entering event queue @ 1531878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1532681339000. Starting simulation...
+info: Entering event queue @ 1532878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1533681339000. Starting simulation...
+info: Entering event queue @ 1533878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1534681339000. Starting simulation...
+info: Entering event queue @ 1534878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1535681339000. Starting simulation...
+info: Entering event queue @ 1535878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1536681339000. Starting simulation...
+info: Entering event queue @ 1536878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1537681339000. Starting simulation...
+info: Entering event queue @ 1537878941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1538681339000. Starting simulation...
-info: Entering event queue @ 1539417631000. Starting simulation...
+info: Entering event queue @ 1538878941000. Starting simulation...
+info: Entering event queue @ 1539615539000. Starting simulation...
switching cpus
-info: Entering event queue @ 1539417633000. Starting simulation...
+info: Entering event queue @ 1539615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1540417633000. Starting simulation...
+info: Entering event queue @ 1540615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1541417633000. Starting simulation...
+info: Entering event queue @ 1541615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1542417633000. Starting simulation...
+info: Entering event queue @ 1542615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1543417633000. Starting simulation...
+info: Entering event queue @ 1543615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1544417633000. Starting simulation...
+info: Entering event queue @ 1544615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1545417633000. Starting simulation...
+info: Entering event queue @ 1545615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1546417633000. Starting simulation...
+info: Entering event queue @ 1546615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1547417633000. Starting simulation...
+info: Entering event queue @ 1547615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1548417633000. Starting simulation...
+info: Entering event queue @ 1548615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1549417633000. Starting simulation...
+info: Entering event queue @ 1549615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1550417633000. Starting simulation...
+info: Entering event queue @ 1550615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1551417633000. Starting simulation...
+info: Entering event queue @ 1551615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1552417633000. Starting simulation...
+info: Entering event queue @ 1552615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1553417633000. Starting simulation...
+info: Entering event queue @ 1553615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1554417633000. Starting simulation...
+info: Entering event queue @ 1554615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1555417633000. Starting simulation...
+info: Entering event queue @ 1555615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1556417633000. Starting simulation...
+info: Entering event queue @ 1556615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1557417633000. Starting simulation...
+info: Entering event queue @ 1557615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1558417633000. Starting simulation...
+info: Entering event queue @ 1558615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1559417633000. Starting simulation...
+info: Entering event queue @ 1559615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1560417633000. Starting simulation...
+info: Entering event queue @ 1560615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1561417633000. Starting simulation...
+info: Entering event queue @ 1561615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1562417633000. Starting simulation...
+info: Entering event queue @ 1562615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1563417633000. Starting simulation...
+info: Entering event queue @ 1563615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1564417633000. Starting simulation...
+info: Entering event queue @ 1564615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1565417633000. Starting simulation...
+info: Entering event queue @ 1565615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1566417633000. Starting simulation...
+info: Entering event queue @ 1566615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1567417633000. Starting simulation...
+info: Entering event queue @ 1567615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1568417633000. Starting simulation...
+info: Entering event queue @ 1568615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1569417633000. Starting simulation...
+info: Entering event queue @ 1569615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1570417633000. Starting simulation...
+info: Entering event queue @ 1570615541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1571417633000. Starting simulation...
-info: Entering event queue @ 1572153772000. Starting simulation...
+info: Entering event queue @ 1571615541000. Starting simulation...
+info: Entering event queue @ 1572352118000. Starting simulation...
switching cpus
-info: Entering event queue @ 1572153774000. Starting simulation...
+info: Entering event queue @ 1572352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1573153774000. Starting simulation...
+info: Entering event queue @ 1573352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1574153774000. Starting simulation...
+info: Entering event queue @ 1574352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1575153774000. Starting simulation...
+info: Entering event queue @ 1575352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1576153774000. Starting simulation...
+info: Entering event queue @ 1576352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1577153774000. Starting simulation...
+info: Entering event queue @ 1577352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1578153774000. Starting simulation...
+info: Entering event queue @ 1578352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1579153774000. Starting simulation...
+info: Entering event queue @ 1579352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1580153774000. Starting simulation...
+info: Entering event queue @ 1580352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1581153774000. Starting simulation...
+info: Entering event queue @ 1581352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1582153774000. Starting simulation...
+info: Entering event queue @ 1582352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1583153774000. Starting simulation...
+info: Entering event queue @ 1583352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1584153774000. Starting simulation...
+info: Entering event queue @ 1584352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1585153774000. Starting simulation...
+info: Entering event queue @ 1585352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1586153774000. Starting simulation...
+info: Entering event queue @ 1586352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1587153774000. Starting simulation...
+info: Entering event queue @ 1587352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1588153774000. Starting simulation...
+info: Entering event queue @ 1588352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1589153774000. Starting simulation...
+info: Entering event queue @ 1589352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1590153774000. Starting simulation...
+info: Entering event queue @ 1590352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1591153774000. Starting simulation...
+info: Entering event queue @ 1591352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1592153774000. Starting simulation...
+info: Entering event queue @ 1592352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1593153774000. Starting simulation...
+info: Entering event queue @ 1593352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1594153774000. Starting simulation...
+info: Entering event queue @ 1594352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1595153774000. Starting simulation...
+info: Entering event queue @ 1595352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1596153774000. Starting simulation...
+info: Entering event queue @ 1596352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1597153774000. Starting simulation...
+info: Entering event queue @ 1597352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1598153774000. Starting simulation...
+info: Entering event queue @ 1598352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1599153774000. Starting simulation...
+info: Entering event queue @ 1599352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1600153774000. Starting simulation...
+info: Entering event queue @ 1600352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1601153774000. Starting simulation...
+info: Entering event queue @ 1601352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1602153774000. Starting simulation...
+info: Entering event queue @ 1602352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1603153774000. Starting simulation...
+info: Entering event queue @ 1603352120000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1604153774000. Starting simulation...
-info: Entering event queue @ 1604890063000. Starting simulation...
+info: Entering event queue @ 1604352120000. Starting simulation...
+info: Entering event queue @ 1605087530000. Starting simulation...
switching cpus
-info: Entering event queue @ 1604890065000. Starting simulation...
+info: Entering event queue @ 1605087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1605890065000. Starting simulation...
+info: Entering event queue @ 1606087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1606890065000. Starting simulation...
+info: Entering event queue @ 1607087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1607890065000. Starting simulation...
+info: Entering event queue @ 1608087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1608890065000. Starting simulation...
+info: Entering event queue @ 1609087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1609890065000. Starting simulation...
+info: Entering event queue @ 1610087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1610890065000. Starting simulation...
+info: Entering event queue @ 1611087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1611890065000. Starting simulation...
+info: Entering event queue @ 1612087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1612890065000. Starting simulation...
+info: Entering event queue @ 1613087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1613890065000. Starting simulation...
+info: Entering event queue @ 1614087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1614890065000. Starting simulation...
+info: Entering event queue @ 1615087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1615890065000. Starting simulation...
+info: Entering event queue @ 1616087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1616890065000. Starting simulation...
+info: Entering event queue @ 1617087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1617890065000. Starting simulation...
+info: Entering event queue @ 1618087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1618890065000. Starting simulation...
+info: Entering event queue @ 1619087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1619890065000. Starting simulation...
+info: Entering event queue @ 1620087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1620890065000. Starting simulation...
+info: Entering event queue @ 1621087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1621890065000. Starting simulation...
+info: Entering event queue @ 1622087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1622890065000. Starting simulation...
+info: Entering event queue @ 1623087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1623890065000. Starting simulation...
+info: Entering event queue @ 1624087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1624890065000. Starting simulation...
+info: Entering event queue @ 1625087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1625890065000. Starting simulation...
+info: Entering event queue @ 1626087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1626890065000. Starting simulation...
+info: Entering event queue @ 1627087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1627890065000. Starting simulation...
+info: Entering event queue @ 1628087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1628890065000. Starting simulation...
+info: Entering event queue @ 1629087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1629890065000. Starting simulation...
+info: Entering event queue @ 1630087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1630890065000. Starting simulation...
+info: Entering event queue @ 1631087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1631890065000. Starting simulation...
+info: Entering event queue @ 1632087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1632890065000. Starting simulation...
+info: Entering event queue @ 1633087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1633890065000. Starting simulation...
+info: Entering event queue @ 1634087532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1634890065000. Starting simulation...
+info: Entering event queue @ 1635087532000. Starting simulation...
switching cpus
-info: Entering event queue @ 1634890066000. Starting simulation...
+info: Entering event queue @ 1635087539500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1635890066000. Starting simulation...
+info: Entering event queue @ 1636087539500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1636890066000. Starting simulation...
-info: Entering event queue @ 1637626663000. Starting simulation...
+info: Entering event queue @ 1637087539500. Starting simulation...
+info: Entering event queue @ 1637824130000. Starting simulation...
switching cpus
-info: Entering event queue @ 1637626665000. Starting simulation...
+info: Entering event queue @ 1637824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1638626665000. Starting simulation...
+info: Entering event queue @ 1638824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1639626665000. Starting simulation...
+info: Entering event queue @ 1639824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1640626665000. Starting simulation...
+info: Entering event queue @ 1640824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1641626665000. Starting simulation...
+info: Entering event queue @ 1641824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1642626665000. Starting simulation...
+info: Entering event queue @ 1642824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1643626665000. Starting simulation...
+info: Entering event queue @ 1643824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1644626665000. Starting simulation...
+info: Entering event queue @ 1644824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1645626665000. Starting simulation...
+info: Entering event queue @ 1645824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1646626665000. Starting simulation...
+info: Entering event queue @ 1646824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1647626665000. Starting simulation...
+info: Entering event queue @ 1647824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1648626665000. Starting simulation...
+info: Entering event queue @ 1648824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1649626665000. Starting simulation...
+info: Entering event queue @ 1649824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1650626665000. Starting simulation...
+info: Entering event queue @ 1650824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1651626665000. Starting simulation...
+info: Entering event queue @ 1651824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1652626665000. Starting simulation...
+info: Entering event queue @ 1652824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1653626665000. Starting simulation...
+info: Entering event queue @ 1653824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1654626665000. Starting simulation...
+info: Entering event queue @ 1654824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1655626665000. Starting simulation...
+info: Entering event queue @ 1655824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1656626665000. Starting simulation...
+info: Entering event queue @ 1656824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1657626665000. Starting simulation...
+info: Entering event queue @ 1657824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1658626665000. Starting simulation...
+info: Entering event queue @ 1658824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1659626665000. Starting simulation...
+info: Entering event queue @ 1659824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1660626665000. Starting simulation...
+info: Entering event queue @ 1660824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1661626665000. Starting simulation...
+info: Entering event queue @ 1661824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1662626665000. Starting simulation...
+info: Entering event queue @ 1662824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1663626665000. Starting simulation...
+info: Entering event queue @ 1663824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1664626665000. Starting simulation...
+info: Entering event queue @ 1664824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1665626665000. Starting simulation...
+info: Entering event queue @ 1665824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1666626665000. Starting simulation...
+info: Entering event queue @ 1666824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1667626665000. Starting simulation...
+info: Entering event queue @ 1667824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1668626665000. Starting simulation...
+info: Entering event queue @ 1668824132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1669626665000. Starting simulation...
-info: Entering event queue @ 1670362807000. Starting simulation...
+info: Entering event queue @ 1669824132000. Starting simulation...
+info: Entering event queue @ 1670560751000. Starting simulation...
switching cpus
-info: Entering event queue @ 1670362809000. Starting simulation...
+info: Entering event queue @ 1670560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1671362809000. Starting simulation...
+info: Entering event queue @ 1671560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1672362809000. Starting simulation...
+info: Entering event queue @ 1672560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1673362809000. Starting simulation...
+info: Entering event queue @ 1673560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1674362809000. Starting simulation...
+info: Entering event queue @ 1674560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1675362809000. Starting simulation...
+info: Entering event queue @ 1675560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1676362809000. Starting simulation...
+info: Entering event queue @ 1676560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1677362809000. Starting simulation...
+info: Entering event queue @ 1677560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1678362809000. Starting simulation...
+info: Entering event queue @ 1678560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1679362809000. Starting simulation...
+info: Entering event queue @ 1679560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1680362809000. Starting simulation...
+info: Entering event queue @ 1680560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1681362809000. Starting simulation...
+info: Entering event queue @ 1681560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1682362809000. Starting simulation...
+info: Entering event queue @ 1682560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1683362809000. Starting simulation...
+info: Entering event queue @ 1683560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1684362809000. Starting simulation...
+info: Entering event queue @ 1684560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1685362809000. Starting simulation...
+info: Entering event queue @ 1685560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1686362809000. Starting simulation...
+info: Entering event queue @ 1686560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1687362809000. Starting simulation...
+info: Entering event queue @ 1687560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1688362809000. Starting simulation...
+info: Entering event queue @ 1688560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1689362809000. Starting simulation...
+info: Entering event queue @ 1689560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1690362809000. Starting simulation...
+info: Entering event queue @ 1690560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1691362809000. Starting simulation...
+info: Entering event queue @ 1691560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1692362809000. Starting simulation...
+info: Entering event queue @ 1692560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1693362809000. Starting simulation...
+info: Entering event queue @ 1693560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1694362809000. Starting simulation...
+info: Entering event queue @ 1694560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1695362809000. Starting simulation...
+info: Entering event queue @ 1695560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1696362809000. Starting simulation...
+info: Entering event queue @ 1696560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1697362809000. Starting simulation...
+info: Entering event queue @ 1697560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1698362809000. Starting simulation...
+info: Entering event queue @ 1698560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1699362809000. Starting simulation...
+info: Entering event queue @ 1699560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1700362809000. Starting simulation...
+info: Entering event queue @ 1700560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1701362809000. Starting simulation...
+info: Entering event queue @ 1701560753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1702362809000. Starting simulation...
-info: Entering event queue @ 1703098954000. Starting simulation...
+info: Entering event queue @ 1702560753000. Starting simulation...
+info: Entering event queue @ 1703297351000. Starting simulation...
switching cpus
-info: Entering event queue @ 1703098956000. Starting simulation...
+info: Entering event queue @ 1703297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1704098956000. Starting simulation...
+info: Entering event queue @ 1704297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1705098956000. Starting simulation...
+info: Entering event queue @ 1705297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1706098956000. Starting simulation...
+info: Entering event queue @ 1706297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1707098956000. Starting simulation...
+info: Entering event queue @ 1707297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1708098956000. Starting simulation...
+info: Entering event queue @ 1708297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1709098956000. Starting simulation...
+info: Entering event queue @ 1709297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1710098956000. Starting simulation...
+info: Entering event queue @ 1710297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1711098956000. Starting simulation...
+info: Entering event queue @ 1711297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1712098956000. Starting simulation...
+info: Entering event queue @ 1712297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1713098956000. Starting simulation...
+info: Entering event queue @ 1713297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1714098956000. Starting simulation...
+info: Entering event queue @ 1714297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1715098956000. Starting simulation...
+info: Entering event queue @ 1715297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1716098956000. Starting simulation...
+info: Entering event queue @ 1716297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1717098956000. Starting simulation...
+info: Entering event queue @ 1717297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1718098956000. Starting simulation...
+info: Entering event queue @ 1718297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1719098956000. Starting simulation...
+info: Entering event queue @ 1719297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1720098956000. Starting simulation...
+info: Entering event queue @ 1720297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1721098956000. Starting simulation...
+info: Entering event queue @ 1721297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1722098956000. Starting simulation...
+info: Entering event queue @ 1722297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1723098956000. Starting simulation...
+info: Entering event queue @ 1723297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1724098956000. Starting simulation...
+info: Entering event queue @ 1724297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1725098956000. Starting simulation...
+info: Entering event queue @ 1725297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1726098956000. Starting simulation...
+info: Entering event queue @ 1726297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1727098956000. Starting simulation...
+info: Entering event queue @ 1727297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1728098956000. Starting simulation...
+info: Entering event queue @ 1728297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1729098956000. Starting simulation...
+info: Entering event queue @ 1729297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1730098956000. Starting simulation...
+info: Entering event queue @ 1730297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1731098956000. Starting simulation...
+info: Entering event queue @ 1731297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1732098956000. Starting simulation...
+info: Entering event queue @ 1732297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1733098956000. Starting simulation...
+info: Entering event queue @ 1733297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1734098956000. Starting simulation...
+info: Entering event queue @ 1734297353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1735098956000. Starting simulation...
-info: Entering event queue @ 1735835245000. Starting simulation...
+info: Entering event queue @ 1735297353000. Starting simulation...
+info: Entering event queue @ 1736032914000. Starting simulation...
switching cpus
-info: Entering event queue @ 1735835247000. Starting simulation...
+info: Entering event queue @ 1736032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1736835247000. Starting simulation...
+info: Entering event queue @ 1737032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1737835247000. Starting simulation...
+info: Entering event queue @ 1738032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1738835247000. Starting simulation...
+info: Entering event queue @ 1739032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1739835247000. Starting simulation...
+info: Entering event queue @ 1740032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1740835247000. Starting simulation...
+info: Entering event queue @ 1741032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1741835247000. Starting simulation...
+info: Entering event queue @ 1742032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1742835247000. Starting simulation...
+info: Entering event queue @ 1743032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1743835247000. Starting simulation...
+info: Entering event queue @ 1744032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1744835247000. Starting simulation...
+info: Entering event queue @ 1745032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1745835247000. Starting simulation...
+info: Entering event queue @ 1746032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1746835247000. Starting simulation...
+info: Entering event queue @ 1747032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1747835247000. Starting simulation...
+info: Entering event queue @ 1748032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1748835247000. Starting simulation...
+info: Entering event queue @ 1749032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1749835247000. Starting simulation...
+info: Entering event queue @ 1750032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1750835247000. Starting simulation...
+info: Entering event queue @ 1751032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1751835247000. Starting simulation...
+info: Entering event queue @ 1752032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1752835247000. Starting simulation...
+info: Entering event queue @ 1753032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1753835247000. Starting simulation...
+info: Entering event queue @ 1754032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1754835247000. Starting simulation...
+info: Entering event queue @ 1755032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1755835247000. Starting simulation...
+info: Entering event queue @ 1756032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1756835247000. Starting simulation...
+info: Entering event queue @ 1757032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1757835247000. Starting simulation...
+info: Entering event queue @ 1758032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1758835247000. Starting simulation...
+info: Entering event queue @ 1759032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1759835247000. Starting simulation...
+info: Entering event queue @ 1760032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1760835247000. Starting simulation...
+info: Entering event queue @ 1761032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1761835247000. Starting simulation...
+info: Entering event queue @ 1762032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1762835247000. Starting simulation...
+info: Entering event queue @ 1763032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1763835247000. Starting simulation...
+info: Entering event queue @ 1764032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1764835247000. Starting simulation...
+info: Entering event queue @ 1765032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1765835247000. Starting simulation...
+info: Entering event queue @ 1766032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1766835247000. Starting simulation...
+info: Entering event queue @ 1767032916000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1767835247000. Starting simulation...
-info: Entering event queue @ 1768571389000. Starting simulation...
+info: Entering event queue @ 1768032916000. Starting simulation...
+info: Entering event queue @ 1768769514000. Starting simulation...
switching cpus
-info: Entering event queue @ 1768571391000. Starting simulation...
+info: Entering event queue @ 1768769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1769571391000. Starting simulation...
+info: Entering event queue @ 1769769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1770571391000. Starting simulation...
+info: Entering event queue @ 1770769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1771571391000. Starting simulation...
+info: Entering event queue @ 1771769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1772571391000. Starting simulation...
+info: Entering event queue @ 1772769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1773571391000. Starting simulation...
+info: Entering event queue @ 1773769516000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1774769516000. Starting simulation...
switching cpus
-info: Entering event queue @ 1774571391000. Starting simulation...
+info: Entering event queue @ 1774769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1775571391000. Starting simulation...
+info: Entering event queue @ 1775769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1776571391000. Starting simulation...
+info: Entering event queue @ 1776769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1777571391000. Starting simulation...
+info: Entering event queue @ 1777769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1778571391000. Starting simulation...
+info: Entering event queue @ 1778769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1779571391000. Starting simulation...
+info: Entering event queue @ 1779769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1780571391000. Starting simulation...
+info: Entering event queue @ 1780769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1781571391000. Starting simulation...
+info: Entering event queue @ 1781769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1782571391000. Starting simulation...
+info: Entering event queue @ 1782769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1783571391000. Starting simulation...
+info: Entering event queue @ 1783769517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1784769517000. Starting simulation...
switching cpus
-info: Entering event queue @ 1784571391000. Starting simulation...
+info: Entering event queue @ 1784769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1785571391000. Starting simulation...
+info: Entering event queue @ 1785769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1786571391000. Starting simulation...
+info: Entering event queue @ 1786769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1787571391000. Starting simulation...
+info: Entering event queue @ 1787769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1788571391000. Starting simulation...
+info: Entering event queue @ 1788769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1789571391000. Starting simulation...
+info: Entering event queue @ 1789769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1790571391000. Starting simulation...
+info: Entering event queue @ 1790769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1791571391000. Starting simulation...
+info: Entering event queue @ 1791769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1792571391000. Starting simulation...
+info: Entering event queue @ 1792769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1793571391000. Starting simulation...
+info: Entering event queue @ 1793769518000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1794769518000. Starting simulation...
switching cpus
-info: Entering event queue @ 1794571391000. Starting simulation...
+info: Entering event queue @ 1794769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1795571391000. Starting simulation...
+info: Entering event queue @ 1795769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1796571391000. Starting simulation...
+info: Entering event queue @ 1796769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1797571391000. Starting simulation...
+info: Entering event queue @ 1797769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1798571391000. Starting simulation...
+info: Entering event queue @ 1798769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1799571391000. Starting simulation...
+info: Entering event queue @ 1799769519000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1800571391000. Starting simulation...
-info: Entering event queue @ 1801307680000. Starting simulation...
+info: Entering event queue @ 1800769519000. Starting simulation...
+info: Entering event queue @ 1801506135000. Starting simulation...
switching cpus
-info: Entering event queue @ 1801307682000. Starting simulation...
+info: Entering event queue @ 1801506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1802307682000. Starting simulation...
+info: Entering event queue @ 1802506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1803307682000. Starting simulation...
+info: Entering event queue @ 1803506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1804307682000. Starting simulation...
+info: Entering event queue @ 1804506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1805307682000. Starting simulation...
+info: Entering event queue @ 1805506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1806307682000. Starting simulation...
+info: Entering event queue @ 1806506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1807307682000. Starting simulation...
+info: Entering event queue @ 1807506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1808307682000. Starting simulation...
+info: Entering event queue @ 1808506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1809307682000. Starting simulation...
+info: Entering event queue @ 1809506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1810307682000. Starting simulation...
+info: Entering event queue @ 1810506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1811307682000. Starting simulation...
+info: Entering event queue @ 1811506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1812307682000. Starting simulation...
+info: Entering event queue @ 1812506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1813307682000. Starting simulation...
+info: Entering event queue @ 1813506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1814307682000. Starting simulation...
+info: Entering event queue @ 1814506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1815307682000. Starting simulation...
+info: Entering event queue @ 1815506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1816307682000. Starting simulation...
+info: Entering event queue @ 1816506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1817307682000. Starting simulation...
+info: Entering event queue @ 1817506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1818307682000. Starting simulation...
+info: Entering event queue @ 1818506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1819307682000. Starting simulation...
+info: Entering event queue @ 1819506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1820307682000. Starting simulation...
+info: Entering event queue @ 1820506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1821307682000. Starting simulation...
+info: Entering event queue @ 1821506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1822307682000. Starting simulation...
+info: Entering event queue @ 1822506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1823307682000. Starting simulation...
+info: Entering event queue @ 1823506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1824307682000. Starting simulation...
+info: Entering event queue @ 1824506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1825307682000. Starting simulation...
+info: Entering event queue @ 1825506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1826307682000. Starting simulation...
+info: Entering event queue @ 1826506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1827307682000. Starting simulation...
+info: Entering event queue @ 1827506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1828307682000. Starting simulation...
+info: Entering event queue @ 1828506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1829307682000. Starting simulation...
+info: Entering event queue @ 1829506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1830307682000. Starting simulation...
+info: Entering event queue @ 1830506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1831307682000. Starting simulation...
+info: Entering event queue @ 1831506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1832307682000. Starting simulation...
+info: Entering event queue @ 1832506137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1833307682000. Starting simulation...
-info: Entering event queue @ 1834043821000. Starting simulation...
+info: Entering event queue @ 1833506137000. Starting simulation...
+info: Entering event queue @ 1834241547000. Starting simulation...
switching cpus
-info: Entering event queue @ 1834043823000. Starting simulation...
+info: Entering event queue @ 1834241549000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1835043823000. Starting simulation...
+info: Entering event queue @ 1835241549000. Starting simulation...
switching cpus
-info: Entering event queue @ 1835043824000. Starting simulation...
+info: Entering event queue @ 1835241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1836043824000. Starting simulation...
+info: Entering event queue @ 1836241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1837043824000. Starting simulation...
+info: Entering event queue @ 1837241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1838043824000. Starting simulation...
+info: Entering event queue @ 1838241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1839043824000. Starting simulation...
+info: Entering event queue @ 1839241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1840043824000. Starting simulation...
+info: Entering event queue @ 1840241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1841043824000. Starting simulation...
+info: Entering event queue @ 1841241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1842043824000. Starting simulation...
+info: Entering event queue @ 1842241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1843043824000. Starting simulation...
+info: Entering event queue @ 1843241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1844043824000. Starting simulation...
+info: Entering event queue @ 1844241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1845043824000. Starting simulation...
+info: Entering event queue @ 1845241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1846043824000. Starting simulation...
+info: Entering event queue @ 1846241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1847043824000. Starting simulation...
+info: Entering event queue @ 1847241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1848043824000. Starting simulation...
+info: Entering event queue @ 1848241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1849043824000. Starting simulation...
+info: Entering event queue @ 1849241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1850043824000. Starting simulation...
+info: Entering event queue @ 1850241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1851043824000. Starting simulation...
+info: Entering event queue @ 1851241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1852043824000. Starting simulation...
+info: Entering event queue @ 1852241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1853043824000. Starting simulation...
+info: Entering event queue @ 1853241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1854043824000. Starting simulation...
+info: Entering event queue @ 1854241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1855043824000. Starting simulation...
+info: Entering event queue @ 1855241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1856043824000. Starting simulation...
+info: Entering event queue @ 1856241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1857043824000. Starting simulation...
+info: Entering event queue @ 1857241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1858043824000. Starting simulation...
+info: Entering event queue @ 1858241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1859043824000. Starting simulation...
+info: Entering event queue @ 1859241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1860043824000. Starting simulation...
+info: Entering event queue @ 1860241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1861043824000. Starting simulation...
+info: Entering event queue @ 1861241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1862043824000. Starting simulation...
+info: Entering event queue @ 1862241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1863043824000. Starting simulation...
+info: Entering event queue @ 1863241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1864043824000. Starting simulation...
+info: Entering event queue @ 1864241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1865043824000. Starting simulation...
+info: Entering event queue @ 1865241556500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1866043824000. Starting simulation...
-info: Entering event queue @ 1866780115000. Starting simulation...
+info: Entering event queue @ 1866241556500. Starting simulation...
+info: Entering event queue @ 1866978147000. Starting simulation...
switching cpus
-info: Entering event queue @ 1866780117000. Starting simulation...
+info: Entering event queue @ 1866978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1867780117000. Starting simulation...
+info: Entering event queue @ 1867978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1868780117000. Starting simulation...
+info: Entering event queue @ 1868978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1869780117000. Starting simulation...
+info: Entering event queue @ 1869978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1870780117000. Starting simulation...
+info: Entering event queue @ 1870978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1871780117000. Starting simulation...
+info: Entering event queue @ 1871978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1872780117000. Starting simulation...
+info: Entering event queue @ 1872978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1873780117000. Starting simulation...
+info: Entering event queue @ 1873978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1874780117000. Starting simulation...
+info: Entering event queue @ 1874978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1875780117000. Starting simulation...
+info: Entering event queue @ 1875978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1876780117000. Starting simulation...
+info: Entering event queue @ 1876978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1877780117000. Starting simulation...
+info: Entering event queue @ 1877978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1878780117000. Starting simulation...
+info: Entering event queue @ 1878978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1879780117000. Starting simulation...
+info: Entering event queue @ 1879978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1880780117000. Starting simulation...
+info: Entering event queue @ 1880978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1881780117000. Starting simulation...
+info: Entering event queue @ 1881978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1882780117000. Starting simulation...
+info: Entering event queue @ 1882978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1883780117000. Starting simulation...
+info: Entering event queue @ 1883978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1884780117000. Starting simulation...
+info: Entering event queue @ 1884978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1885780117000. Starting simulation...
+info: Entering event queue @ 1885978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1886780117000. Starting simulation...
+info: Entering event queue @ 1886978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1887780117000. Starting simulation...
+info: Entering event queue @ 1887978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1888780117000. Starting simulation...
+info: Entering event queue @ 1888978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1889780117000. Starting simulation...
+info: Entering event queue @ 1889978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1890780117000. Starting simulation...
+info: Entering event queue @ 1890978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1891780117000. Starting simulation...
+info: Entering event queue @ 1891978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1892780117000. Starting simulation...
+info: Entering event queue @ 1892978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1893780117000. Starting simulation...
+info: Entering event queue @ 1893978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1894780117000. Starting simulation...
+info: Entering event queue @ 1894978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1895780117000. Starting simulation...
+info: Entering event queue @ 1895978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1896780117000. Starting simulation...
+info: Entering event queue @ 1896978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1897780117000. Starting simulation...
+info: Entering event queue @ 1897978149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1898780117000. Starting simulation...
-info: Entering event queue @ 1899516256000. Starting simulation...
+info: Entering event queue @ 1898978149000. Starting simulation...
+info: Entering event queue @ 1899714726000. Starting simulation...
switching cpus
-info: Entering event queue @ 1899516258000. Starting simulation...
+info: Entering event queue @ 1899714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1900516258000. Starting simulation...
+info: Entering event queue @ 1900714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1901516258000. Starting simulation...
+info: Entering event queue @ 1901714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1902516258000. Starting simulation...
+info: Entering event queue @ 1902714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1903516258000. Starting simulation...
+info: Entering event queue @ 1903714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1904516258000. Starting simulation...
+info: Entering event queue @ 1904714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1905516258000. Starting simulation...
+info: Entering event queue @ 1905714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1906516258000. Starting simulation...
+info: Entering event queue @ 1906714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1907516258000. Starting simulation...
+info: Entering event queue @ 1907714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1908516258000. Starting simulation...
+info: Entering event queue @ 1908714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1909516258000. Starting simulation...
+info: Entering event queue @ 1909714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1910516258000. Starting simulation...
+info: Entering event queue @ 1910714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1911516258000. Starting simulation...
+info: Entering event queue @ 1911714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1912516258000. Starting simulation...
+info: Entering event queue @ 1912714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1913516258000. Starting simulation...
+info: Entering event queue @ 1913714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1914516258000. Starting simulation...
+info: Entering event queue @ 1914714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1915516258000. Starting simulation...
+info: Entering event queue @ 1915714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1916516258000. Starting simulation...
+info: Entering event queue @ 1916714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1917516258000. Starting simulation...
+info: Entering event queue @ 1917714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1918516258000. Starting simulation...
+info: Entering event queue @ 1918714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1919516258000. Starting simulation...
+info: Entering event queue @ 1919714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1920516258000. Starting simulation...
+info: Entering event queue @ 1920714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1921516258000. Starting simulation...
+info: Entering event queue @ 1921714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1922516258000. Starting simulation...
+info: Entering event queue @ 1922714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1923516258000. Starting simulation...
+info: Entering event queue @ 1923714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1924516258000. Starting simulation...
+info: Entering event queue @ 1924714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1925516258000. Starting simulation...
+info: Entering event queue @ 1925714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1926516258000. Starting simulation...
+info: Entering event queue @ 1926714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1927516258000. Starting simulation...
+info: Entering event queue @ 1927714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1928516258000. Starting simulation...
+info: Entering event queue @ 1928714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1929516258000. Starting simulation...
+info: Entering event queue @ 1929714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1930516258000. Starting simulation...
+info: Entering event queue @ 1930714728000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1931516258000. Starting simulation...
-info: Entering event queue @ 1932252856000. Starting simulation...
+info: Entering event queue @ 1931714728000. Starting simulation...
+info: Entering event queue @ 1932450138000. Starting simulation...
switching cpus
-info: Entering event queue @ 1932252858000. Starting simulation...
+info: Entering event queue @ 1932450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1933252858000. Starting simulation...
+info: Entering event queue @ 1933450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1934252858000. Starting simulation...
+info: Entering event queue @ 1934450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1935252858000. Starting simulation...
+info: Entering event queue @ 1935450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1936252858000. Starting simulation...
+info: Entering event queue @ 1936450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1937252858000. Starting simulation...
+info: Entering event queue @ 1937450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1938252858000. Starting simulation...
+info: Entering event queue @ 1938450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1939252858000. Starting simulation...
+info: Entering event queue @ 1939450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1940252858000. Starting simulation...
+info: Entering event queue @ 1940450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1941252858000. Starting simulation...
+info: Entering event queue @ 1941450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1942252858000. Starting simulation...
+info: Entering event queue @ 1942450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1943252858000. Starting simulation...
+info: Entering event queue @ 1943450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1944252858000. Starting simulation...
+info: Entering event queue @ 1944450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1945252858000. Starting simulation...
+info: Entering event queue @ 1945450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1946252858000. Starting simulation...
+info: Entering event queue @ 1946450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1947252858000. Starting simulation...
+info: Entering event queue @ 1947450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1948252858000. Starting simulation...
+info: Entering event queue @ 1948450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1949252858000. Starting simulation...
+info: Entering event queue @ 1949450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1950252858000. Starting simulation...
+info: Entering event queue @ 1950450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1951252858000. Starting simulation...
+info: Entering event queue @ 1951450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1952252858000. Starting simulation...
+info: Entering event queue @ 1952450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1953252858000. Starting simulation...
+info: Entering event queue @ 1953450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1954252858000. Starting simulation...
+info: Entering event queue @ 1954450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1955252858000. Starting simulation...
+info: Entering event queue @ 1955450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1956252858000. Starting simulation...
+info: Entering event queue @ 1956450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1957252858000. Starting simulation...
+info: Entering event queue @ 1957450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1958252858000. Starting simulation...
+info: Entering event queue @ 1958450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1959252858000. Starting simulation...
+info: Entering event queue @ 1959450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1960252858000. Starting simulation...
+info: Entering event queue @ 1960450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1961252858000. Starting simulation...
+info: Entering event queue @ 1961450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1962252858000. Starting simulation...
+info: Entering event queue @ 1962450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1963252858000. Starting simulation...
+info: Entering event queue @ 1963450140000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1964252858000. Starting simulation...
-info: Entering event queue @ 1964989147000. Starting simulation...
+info: Entering event queue @ 1964450140000. Starting simulation...
+info: Entering event queue @ 1965186738000. Starting simulation...
switching cpus
-info: Entering event queue @ 1964989149000. Starting simulation...
+info: Entering event queue @ 1965186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1965989149000. Starting simulation...
+info: Entering event queue @ 1966186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1966989149000. Starting simulation...
+info: Entering event queue @ 1967186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1967989149000. Starting simulation...
+info: Entering event queue @ 1968186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1968989149000. Starting simulation...
+info: Entering event queue @ 1969186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1969989149000. Starting simulation...
+info: Entering event queue @ 1970186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1970989149000. Starting simulation...
+info: Entering event queue @ 1971186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1971989149000. Starting simulation...
+info: Entering event queue @ 1972186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1972989149000. Starting simulation...
+info: Entering event queue @ 1973186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1973989149000. Starting simulation...
+info: Entering event queue @ 1974186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1974989149000. Starting simulation...
+info: Entering event queue @ 1975186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1975989149000. Starting simulation...
+info: Entering event queue @ 1976186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1976989149000. Starting simulation...
+info: Entering event queue @ 1977186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1977989149000. Starting simulation...
+info: Entering event queue @ 1978186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1978989149000. Starting simulation...
+info: Entering event queue @ 1979186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1979989149000. Starting simulation...
+info: Entering event queue @ 1980186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1980989149000. Starting simulation...
+info: Entering event queue @ 1981186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1981989149000. Starting simulation...
+info: Entering event queue @ 1982186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1982989149000. Starting simulation...
+info: Entering event queue @ 1983186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1983989149000. Starting simulation...
+info: Entering event queue @ 1984186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1984989149000. Starting simulation...
+info: Entering event queue @ 1985186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1985989149000. Starting simulation...
+info: Entering event queue @ 1986186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1986989149000. Starting simulation...
+info: Entering event queue @ 1987186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1987989149000. Starting simulation...
+info: Entering event queue @ 1988186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1988989149000. Starting simulation...
+info: Entering event queue @ 1989186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1989989149000. Starting simulation...
+info: Entering event queue @ 1990186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1990989149000. Starting simulation...
+info: Entering event queue @ 1991186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1991989149000. Starting simulation...
+info: Entering event queue @ 1992186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1992989149000. Starting simulation...
+info: Entering event queue @ 1993186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1993989149000. Starting simulation...
+info: Entering event queue @ 1994186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1994989149000. Starting simulation...
+info: Entering event queue @ 1995186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1995989149000. Starting simulation...
+info: Entering event queue @ 1996186740000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1996989149000. Starting simulation...
-info: Entering event queue @ 1997725291000. Starting simulation...
+info: Entering event queue @ 1997186740000. Starting simulation...
+info: Entering event queue @ 1997923355000. Starting simulation...
switching cpus
-info: Entering event queue @ 1997725293000. Starting simulation...
+info: Entering event queue @ 1997923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1998725293000. Starting simulation...
+info: Entering event queue @ 1998923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1999725293000. Starting simulation...
+info: Entering event queue @ 1999923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2000725293000. Starting simulation...
+info: Entering event queue @ 2000923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2001725293000. Starting simulation...
+info: Entering event queue @ 2001923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2002725293000. Starting simulation...
+info: Entering event queue @ 2002923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2003725293000. Starting simulation...
+info: Entering event queue @ 2003923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2004725293000. Starting simulation...
+info: Entering event queue @ 2004923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2005725293000. Starting simulation...
+info: Entering event queue @ 2005923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2006725293000. Starting simulation...
+info: Entering event queue @ 2006923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2007725293000. Starting simulation...
+info: Entering event queue @ 2007923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2008725293000. Starting simulation...
+info: Entering event queue @ 2008923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2009725293000. Starting simulation...
+info: Entering event queue @ 2009923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2010725293000. Starting simulation...
+info: Entering event queue @ 2010923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2011725293000. Starting simulation...
+info: Entering event queue @ 2011923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2012725293000. Starting simulation...
+info: Entering event queue @ 2012923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2013725293000. Starting simulation...
+info: Entering event queue @ 2013923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2014725293000. Starting simulation...
+info: Entering event queue @ 2014923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2015725293000. Starting simulation...
+info: Entering event queue @ 2015923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2016725293000. Starting simulation...
+info: Entering event queue @ 2016923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2017725293000. Starting simulation...
+info: Entering event queue @ 2017923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2018725293000. Starting simulation...
+info: Entering event queue @ 2018923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2019725293000. Starting simulation...
+info: Entering event queue @ 2019923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2020725293000. Starting simulation...
+info: Entering event queue @ 2020923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2021725293000. Starting simulation...
+info: Entering event queue @ 2021923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2022725293000. Starting simulation...
+info: Entering event queue @ 2022923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2023725293000. Starting simulation...
+info: Entering event queue @ 2023923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2024725293000. Starting simulation...
+info: Entering event queue @ 2024923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2025725293000. Starting simulation...
+info: Entering event queue @ 2025923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2026725293000. Starting simulation...
+info: Entering event queue @ 2026923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2027725293000. Starting simulation...
+info: Entering event queue @ 2027923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2028725293000. Starting simulation...
+info: Entering event queue @ 2028923357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2029725293000. Starting simulation...
-info: Entering event queue @ 2030461582000. Starting simulation...
+info: Entering event queue @ 2029923357000. Starting simulation...
+info: Entering event queue @ 2030658922000. Starting simulation...
switching cpus
-info: Entering event queue @ 2030461584000. Starting simulation...
+info: Entering event queue @ 2030658924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2031461584000. Starting simulation...
+info: Entering event queue @ 2031658924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2032461584000. Starting simulation...
+info: Entering event queue @ 2032658924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2033461584000. Starting simulation...
+info: Entering event queue @ 2033658924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2034461584000. Starting simulation...
+info: Entering event queue @ 2034658924000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2035461584000. Starting simulation...
+info: Entering event queue @ 2035658924000. Starting simulation...
switching cpus
-info: Entering event queue @ 2035461585000. Starting simulation...
+info: Entering event queue @ 2035658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2036461585000. Starting simulation...
+info: Entering event queue @ 2036658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2037461585000. Starting simulation...
+info: Entering event queue @ 2037658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2038461585000. Starting simulation...
+info: Entering event queue @ 2038658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2039461585000. Starting simulation...
+info: Entering event queue @ 2039658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2040461585000. Starting simulation...
+info: Entering event queue @ 2040658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2041461585000. Starting simulation...
+info: Entering event queue @ 2041658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2042461585000. Starting simulation...
+info: Entering event queue @ 2042658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2043461585000. Starting simulation...
+info: Entering event queue @ 2043658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2044461585000. Starting simulation...
+info: Entering event queue @ 2044658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2045461585000. Starting simulation...
+info: Entering event queue @ 2045658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2046461585000. Starting simulation...
+info: Entering event queue @ 2046658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2047461585000. Starting simulation...
+info: Entering event queue @ 2047658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2048461585000. Starting simulation...
+info: Entering event queue @ 2048658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2049461585000. Starting simulation...
+info: Entering event queue @ 2049658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2050461585000. Starting simulation...
+info: Entering event queue @ 2050658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2051461585000. Starting simulation...
+info: Entering event queue @ 2051658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2052461585000. Starting simulation...
+info: Entering event queue @ 2052658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2053461585000. Starting simulation...
+info: Entering event queue @ 2053658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2054461585000. Starting simulation...
+info: Entering event queue @ 2054658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2055461585000. Starting simulation...
+info: Entering event queue @ 2055658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2056461585000. Starting simulation...
+info: Entering event queue @ 2056658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2057461585000. Starting simulation...
+info: Entering event queue @ 2057658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2058461585000. Starting simulation...
+info: Entering event queue @ 2058658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2059461585000. Starting simulation...
+info: Entering event queue @ 2059658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2060461585000. Starting simulation...
+info: Entering event queue @ 2060658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2061461585000. Starting simulation...
+info: Entering event queue @ 2061658931500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2062461585000. Starting simulation...
-info: Entering event queue @ 2063197726000. Starting simulation...
+info: Entering event queue @ 2062658931500. Starting simulation...
+info: Entering event queue @ 2063395522000. Starting simulation...
switching cpus
-info: Entering event queue @ 2063197728000. Starting simulation...
+info: Entering event queue @ 2063395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2064197728000. Starting simulation...
+info: Entering event queue @ 2064395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2065197728000. Starting simulation...
+info: Entering event queue @ 2065395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2066197728000. Starting simulation...
+info: Entering event queue @ 2066395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2067197728000. Starting simulation...
+info: Entering event queue @ 2067395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2068197728000. Starting simulation...
+info: Entering event queue @ 2068395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2069197728000. Starting simulation...
+info: Entering event queue @ 2069395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2070197728000. Starting simulation...
+info: Entering event queue @ 2070395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2071197728000. Starting simulation...
+info: Entering event queue @ 2071395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2072197728000. Starting simulation...
+info: Entering event queue @ 2072395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2073197728000. Starting simulation...
+info: Entering event queue @ 2073395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2074197728000. Starting simulation...
+info: Entering event queue @ 2074395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2075197728000. Starting simulation...
+info: Entering event queue @ 2075395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2076197728000. Starting simulation...
+info: Entering event queue @ 2076395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2077197728000. Starting simulation...
+info: Entering event queue @ 2077395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2078197728000. Starting simulation...
+info: Entering event queue @ 2078395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2079197728000. Starting simulation...
+info: Entering event queue @ 2079395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2080197728000. Starting simulation...
+info: Entering event queue @ 2080395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2081197728000. Starting simulation...
+info: Entering event queue @ 2081395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2082197728000. Starting simulation...
+info: Entering event queue @ 2082395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2083197728000. Starting simulation...
+info: Entering event queue @ 2083395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2084197728000. Starting simulation...
+info: Entering event queue @ 2084395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2085197728000. Starting simulation...
+info: Entering event queue @ 2085395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2086197728000. Starting simulation...
+info: Entering event queue @ 2086395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2087197728000. Starting simulation...
+info: Entering event queue @ 2087395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2088197728000. Starting simulation...
+info: Entering event queue @ 2088395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2089197728000. Starting simulation...
+info: Entering event queue @ 2089395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2090197728000. Starting simulation...
+info: Entering event queue @ 2090395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2091197728000. Starting simulation...
+info: Entering event queue @ 2091395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2092197728000. Starting simulation...
+info: Entering event queue @ 2092395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2093197728000. Starting simulation...
+info: Entering event queue @ 2093395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2094197728000. Starting simulation...
+info: Entering event queue @ 2094395524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2095197728000. Starting simulation...
-info: Entering event queue @ 2095933873000. Starting simulation...
+info: Entering event queue @ 2095395524000. Starting simulation...
+info: Entering event queue @ 2096132143000. Starting simulation...
switching cpus
-info: Entering event queue @ 2095933875000. Starting simulation...
+info: Entering event queue @ 2096132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2096933875000. Starting simulation...
+info: Entering event queue @ 2097132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2097933875000. Starting simulation...
+info: Entering event queue @ 2098132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2098933875000. Starting simulation...
+info: Entering event queue @ 2099132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2099933875000. Starting simulation...
+info: Entering event queue @ 2100132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2100933875000. Starting simulation...
+info: Entering event queue @ 2101132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2101933875000. Starting simulation...
+info: Entering event queue @ 2102132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2102933875000. Starting simulation...
+info: Entering event queue @ 2103132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2103933875000. Starting simulation...
+info: Entering event queue @ 2104132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2104933875000. Starting simulation...
+info: Entering event queue @ 2105132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2105933875000. Starting simulation...
+info: Entering event queue @ 2106132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2106933875000. Starting simulation...
+info: Entering event queue @ 2107132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2107933875000. Starting simulation...
+info: Entering event queue @ 2108132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2108933875000. Starting simulation...
+info: Entering event queue @ 2109132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2109933875000. Starting simulation...
+info: Entering event queue @ 2110132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2110933875000. Starting simulation...
+info: Entering event queue @ 2111132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2111933875000. Starting simulation...
+info: Entering event queue @ 2112132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2112933875000. Starting simulation...
+info: Entering event queue @ 2113132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2113933875000. Starting simulation...
+info: Entering event queue @ 2114132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2114933875000. Starting simulation...
+info: Entering event queue @ 2115132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2115933875000. Starting simulation...
+info: Entering event queue @ 2116132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2116933875000. Starting simulation...
+info: Entering event queue @ 2117132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2117933875000. Starting simulation...
+info: Entering event queue @ 2118132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2118933875000. Starting simulation...
+info: Entering event queue @ 2119132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2119933875000. Starting simulation...
+info: Entering event queue @ 2120132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2120933875000. Starting simulation...
+info: Entering event queue @ 2121132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2121933875000. Starting simulation...
+info: Entering event queue @ 2122132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2122933875000. Starting simulation...
+info: Entering event queue @ 2123132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2123933875000. Starting simulation...
+info: Entering event queue @ 2124132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2124933875000. Starting simulation...
+info: Entering event queue @ 2125132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2125933875000. Starting simulation...
+info: Entering event queue @ 2126132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2126933875000. Starting simulation...
+info: Entering event queue @ 2127132145000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2127933875000. Starting simulation...
-info: Entering event queue @ 2128670473000. Starting simulation...
+info: Entering event queue @ 2128132145000. Starting simulation...
+info: Entering event queue @ 2128868743000. Starting simulation...
switching cpus
-info: Entering event queue @ 2128670475000. Starting simulation...
+info: Entering event queue @ 2128868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2129670475000. Starting simulation...
+info: Entering event queue @ 2129868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2130670475000. Starting simulation...
+info: Entering event queue @ 2130868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2131670475000. Starting simulation...
+info: Entering event queue @ 2131868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2132670475000. Starting simulation...
+info: Entering event queue @ 2132868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2133670475000. Starting simulation...
+info: Entering event queue @ 2133868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2134670475000. Starting simulation...
+info: Entering event queue @ 2134868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2135670475000. Starting simulation...
+info: Entering event queue @ 2135868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2136670475000. Starting simulation...
+info: Entering event queue @ 2136868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2137670475000. Starting simulation...
+info: Entering event queue @ 2137868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2138670475000. Starting simulation...
+info: Entering event queue @ 2138868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2139670475000. Starting simulation...
+info: Entering event queue @ 2139868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2140670475000. Starting simulation...
+info: Entering event queue @ 2140868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2141670475000. Starting simulation...
+info: Entering event queue @ 2141868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2142670475000. Starting simulation...
+info: Entering event queue @ 2142868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2143670475000. Starting simulation...
+info: Entering event queue @ 2143868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2144670475000. Starting simulation...
+info: Entering event queue @ 2144868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2145670475000. Starting simulation...
+info: Entering event queue @ 2145868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2146670475000. Starting simulation...
+info: Entering event queue @ 2146868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2147670475000. Starting simulation...
+info: Entering event queue @ 2147868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2148670475000. Starting simulation...
+info: Entering event queue @ 2148868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2149670475000. Starting simulation...
+info: Entering event queue @ 2149868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2150670475000. Starting simulation...
+info: Entering event queue @ 2150868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2151670475000. Starting simulation...
+info: Entering event queue @ 2151868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2152670475000. Starting simulation...
+info: Entering event queue @ 2152868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2153670475000. Starting simulation...
+info: Entering event queue @ 2153868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2154670475000. Starting simulation...
+info: Entering event queue @ 2154868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2155670475000. Starting simulation...
+info: Entering event queue @ 2155868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2156670475000. Starting simulation...
+info: Entering event queue @ 2156868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2157670475000. Starting simulation...
+info: Entering event queue @ 2157868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2158670475000. Starting simulation...
+info: Entering event queue @ 2158868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2159670475000. Starting simulation...
+info: Entering event queue @ 2159868745000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2160670475000. Starting simulation...
-info: Entering event queue @ 2161406305000. Starting simulation...
+info: Entering event queue @ 2160868745000. Starting simulation...
+info: Entering event queue @ 2161604155000. Starting simulation...
switching cpus
-info: Entering event queue @ 2161406307000. Starting simulation...
+info: Entering event queue @ 2161604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2162406307000. Starting simulation...
+info: Entering event queue @ 2162604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2163406307000. Starting simulation...
+info: Entering event queue @ 2163604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2164406307000. Starting simulation...
+info: Entering event queue @ 2164604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2165406307000. Starting simulation...
+info: Entering event queue @ 2165604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2166406307000. Starting simulation...
+info: Entering event queue @ 2166604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2167406307000. Starting simulation...
+info: Entering event queue @ 2167604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2168406307000. Starting simulation...
+info: Entering event queue @ 2168604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2169406307000. Starting simulation...
+info: Entering event queue @ 2169604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2170406307000. Starting simulation...
+info: Entering event queue @ 2170604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2171406307000. Starting simulation...
+info: Entering event queue @ 2171604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2172406307000. Starting simulation...
+info: Entering event queue @ 2172604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2173406307000. Starting simulation...
+info: Entering event queue @ 2173604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2174406307000. Starting simulation...
+info: Entering event queue @ 2174604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2175406307000. Starting simulation...
+info: Entering event queue @ 2175604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2176406307000. Starting simulation...
+info: Entering event queue @ 2176604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2177406307000. Starting simulation...
+info: Entering event queue @ 2177604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2178406307000. Starting simulation...
+info: Entering event queue @ 2178604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2179406307000. Starting simulation...
+info: Entering event queue @ 2179604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2180406307000. Starting simulation...
+info: Entering event queue @ 2180604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2181406307000. Starting simulation...
+info: Entering event queue @ 2181604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2182406307000. Starting simulation...
+info: Entering event queue @ 2182604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2183406307000. Starting simulation...
+info: Entering event queue @ 2183604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2184406307000. Starting simulation...
+info: Entering event queue @ 2184604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2185406307000. Starting simulation...
+info: Entering event queue @ 2185604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2186406307000. Starting simulation...
+info: Entering event queue @ 2186604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2187406307000. Starting simulation...
+info: Entering event queue @ 2187604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2188406307000. Starting simulation...
+info: Entering event queue @ 2188604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2189406307000. Starting simulation...
+info: Entering event queue @ 2189604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2190406307000. Starting simulation...
+info: Entering event queue @ 2190604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2191406307000. Starting simulation...
+info: Entering event queue @ 2191604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2192406307000. Starting simulation...
+info: Entering event queue @ 2192604157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2193406307000. Starting simulation...
-info: Entering event queue @ 2194142905000. Starting simulation...
+info: Entering event queue @ 2193604157000. Starting simulation...
+info: Entering event queue @ 2194340734000. Starting simulation...
switching cpus
-info: Entering event queue @ 2194142907000. Starting simulation...
+info: Entering event queue @ 2194340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2195142907000. Starting simulation...
+info: Entering event queue @ 2195340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2196142907000. Starting simulation...
+info: Entering event queue @ 2196340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2197142907000. Starting simulation...
+info: Entering event queue @ 2197340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2198142907000. Starting simulation...
+info: Entering event queue @ 2198340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2199142907000. Starting simulation...
+info: Entering event queue @ 2199340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2200142907000. Starting simulation...
+info: Entering event queue @ 2200340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2201142907000. Starting simulation...
+info: Entering event queue @ 2201340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2202142907000. Starting simulation...
+info: Entering event queue @ 2202340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2203142907000. Starting simulation...
+info: Entering event queue @ 2203340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2204142907000. Starting simulation...
+info: Entering event queue @ 2204340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2205142907000. Starting simulation...
+info: Entering event queue @ 2205340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2206142907000. Starting simulation...
+info: Entering event queue @ 2206340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2207142907000. Starting simulation...
+info: Entering event queue @ 2207340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2208142907000. Starting simulation...
+info: Entering event queue @ 2208340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2209142907000. Starting simulation...
+info: Entering event queue @ 2209340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2210142907000. Starting simulation...
+info: Entering event queue @ 2210340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2211142907000. Starting simulation...
+info: Entering event queue @ 2211340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2212142907000. Starting simulation...
+info: Entering event queue @ 2212340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2213142907000. Starting simulation...
+info: Entering event queue @ 2213340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2214142907000. Starting simulation...
+info: Entering event queue @ 2214340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2215142907000. Starting simulation...
+info: Entering event queue @ 2215340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2216142907000. Starting simulation...
+info: Entering event queue @ 2216340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2217142907000. Starting simulation...
+info: Entering event queue @ 2217340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2218142907000. Starting simulation...
+info: Entering event queue @ 2218340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2219142907000. Starting simulation...
+info: Entering event queue @ 2219340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2220142907000. Starting simulation...
+info: Entering event queue @ 2220340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2221142907000. Starting simulation...
+info: Entering event queue @ 2221340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2222142907000. Starting simulation...
+info: Entering event queue @ 2222340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2223142907000. Starting simulation...
+info: Entering event queue @ 2223340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2224142907000. Starting simulation...
+info: Entering event queue @ 2224340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2225142907000. Starting simulation...
+info: Entering event queue @ 2225340736000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2226142907000. Starting simulation...
-info: Entering event queue @ 2226879196000. Starting simulation...
+info: Entering event queue @ 2226340736000. Starting simulation...
+info: Entering event queue @ 2227077334000. Starting simulation...
switching cpus
-info: Entering event queue @ 2226879198000. Starting simulation...
+info: Entering event queue @ 2227077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2227879198000. Starting simulation...
+info: Entering event queue @ 2228077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2228879198000. Starting simulation...
+info: Entering event queue @ 2229077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2229879198000. Starting simulation...
+info: Entering event queue @ 2230077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2230879198000. Starting simulation...
+info: Entering event queue @ 2231077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2231879198000. Starting simulation...
+info: Entering event queue @ 2232077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2232879198000. Starting simulation...
+info: Entering event queue @ 2233077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2233879198000. Starting simulation...
+info: Entering event queue @ 2234077336000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2234879198000. Starting simulation...
+info: Entering event queue @ 2235077336000. Starting simulation...
switching cpus
-info: Entering event queue @ 2234879199000. Starting simulation...
+info: Entering event queue @ 2235077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2235879199000. Starting simulation...
+info: Entering event queue @ 2236077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2236879199000. Starting simulation...
+info: Entering event queue @ 2237077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2237879199000. Starting simulation...
+info: Entering event queue @ 2238077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2238879199000. Starting simulation...
+info: Entering event queue @ 2239077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2239879199000. Starting simulation...
+info: Entering event queue @ 2240077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2240879199000. Starting simulation...
+info: Entering event queue @ 2241077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2241879199000. Starting simulation...
+info: Entering event queue @ 2242077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2242879199000. Starting simulation...
+info: Entering event queue @ 2243077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2243879199000. Starting simulation...
+info: Entering event queue @ 2244077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2244879199000. Starting simulation...
+info: Entering event queue @ 2245077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2245879199000. Starting simulation...
+info: Entering event queue @ 2246077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2246879199000. Starting simulation...
+info: Entering event queue @ 2247077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2247879199000. Starting simulation...
+info: Entering event queue @ 2248077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2248879199000. Starting simulation...
+info: Entering event queue @ 2249077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2249879199000. Starting simulation...
+info: Entering event queue @ 2250077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2250879199000. Starting simulation...
+info: Entering event queue @ 2251077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2251879199000. Starting simulation...
+info: Entering event queue @ 2252077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2252879199000. Starting simulation...
+info: Entering event queue @ 2253077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2253879199000. Starting simulation...
+info: Entering event queue @ 2254077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2254879199000. Starting simulation...
+info: Entering event queue @ 2255077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2255879199000. Starting simulation...
+info: Entering event queue @ 2256077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2256879199000. Starting simulation...
+info: Entering event queue @ 2257077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2257879199000. Starting simulation...
+info: Entering event queue @ 2258077343500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2258879199000. Starting simulation...
-info: Entering event queue @ 2259615337000. Starting simulation...
+info: Entering event queue @ 2259077343500. Starting simulation...
+info: Entering event queue @ 2259812939000. Starting simulation...
switching cpus
-info: Entering event queue @ 2259615339000. Starting simulation...
+info: Entering event queue @ 2259812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2260615339000. Starting simulation...
+info: Entering event queue @ 2260812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2261615339000. Starting simulation...
+info: Entering event queue @ 2261812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2262615339000. Starting simulation...
+info: Entering event queue @ 2262812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2263615339000. Starting simulation...
+info: Entering event queue @ 2263812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2264615339000. Starting simulation...
+info: Entering event queue @ 2264812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2265615339000. Starting simulation...
+info: Entering event queue @ 2265812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2266615339000. Starting simulation...
+info: Entering event queue @ 2266812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2267615339000. Starting simulation...
+info: Entering event queue @ 2267812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2268615339000. Starting simulation...
+info: Entering event queue @ 2268812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2269615339000. Starting simulation...
+info: Entering event queue @ 2269812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2270615339000. Starting simulation...
+info: Entering event queue @ 2270812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2271615339000. Starting simulation...
+info: Entering event queue @ 2271812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2272615339000. Starting simulation...
+info: Entering event queue @ 2272812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2273615339000. Starting simulation...
+info: Entering event queue @ 2273812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2274615339000. Starting simulation...
+info: Entering event queue @ 2274812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2275615339000. Starting simulation...
+info: Entering event queue @ 2275812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2276615339000. Starting simulation...
+info: Entering event queue @ 2276812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2277615339000. Starting simulation...
+info: Entering event queue @ 2277812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2278615339000. Starting simulation...
+info: Entering event queue @ 2278812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2279615339000. Starting simulation...
+info: Entering event queue @ 2279812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2280615339000. Starting simulation...
+info: Entering event queue @ 2280812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2281615339000. Starting simulation...
+info: Entering event queue @ 2281812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2282615339000. Starting simulation...
+info: Entering event queue @ 2282812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2283615339000. Starting simulation...
+info: Entering event queue @ 2283812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2284615339000. Starting simulation...
+info: Entering event queue @ 2284812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2285615339000. Starting simulation...
+info: Entering event queue @ 2285812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2286615339000. Starting simulation...
+info: Entering event queue @ 2286812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2287615339000. Starting simulation...
+info: Entering event queue @ 2287812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2288615339000. Starting simulation...
+info: Entering event queue @ 2288812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2289615339000. Starting simulation...
+info: Entering event queue @ 2289812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2290615339000. Starting simulation...
+info: Entering event queue @ 2290812941000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2291615339000. Starting simulation...
-info: Entering event queue @ 2292351631000. Starting simulation...
+info: Entering event queue @ 2291812941000. Starting simulation...
+info: Entering event queue @ 2292549539000. Starting simulation...
switching cpus
-info: Entering event queue @ 2292351633000. Starting simulation...
+info: Entering event queue @ 2292549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2293351633000. Starting simulation...
+info: Entering event queue @ 2293549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2294351633000. Starting simulation...
+info: Entering event queue @ 2294549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2295351633000. Starting simulation...
+info: Entering event queue @ 2295549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2296351633000. Starting simulation...
+info: Entering event queue @ 2296549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2297351633000. Starting simulation...
+info: Entering event queue @ 2297549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2298351633000. Starting simulation...
+info: Entering event queue @ 2298549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2299351633000. Starting simulation...
+info: Entering event queue @ 2299549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2300351633000. Starting simulation...
+info: Entering event queue @ 2300549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2301351633000. Starting simulation...
+info: Entering event queue @ 2301549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2302351633000. Starting simulation...
+info: Entering event queue @ 2302549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2303351633000. Starting simulation...
+info: Entering event queue @ 2303549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2304351633000. Starting simulation...
+info: Entering event queue @ 2304549541000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2305351633000. Starting simulation...
+info: Entering event queue @ 2305549541000. Starting simulation...
switching cpus
-info: Entering event queue @ 2305351696000. Starting simulation...
+info: Entering event queue @ 2305549582000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2306351696000. Starting simulation...
+info: Entering event queue @ 2306549582000. Starting simulation...
switching cpus
-info: Entering event queue @ 2306351697000. Starting simulation...
+info: Entering event queue @ 2306549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2307351697000. Starting simulation...
+info: Entering event queue @ 2307549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2308351697000. Starting simulation...
+info: Entering event queue @ 2308549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2309351697000. Starting simulation...
+info: Entering event queue @ 2309549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2310351697000. Starting simulation...
+info: Entering event queue @ 2310549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2311351697000. Starting simulation...
+info: Entering event queue @ 2311549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2312351697000. Starting simulation...
+info: Entering event queue @ 2312549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2313351697000. Starting simulation...
+info: Entering event queue @ 2313549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2314351697000. Starting simulation...
+info: Entering event queue @ 2314549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2315351697000. Starting simulation...
+info: Entering event queue @ 2315549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2316351697000. Starting simulation...
+info: Entering event queue @ 2316549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2317351697000. Starting simulation...
+info: Entering event queue @ 2317549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2318351697000. Starting simulation...
+info: Entering event queue @ 2318549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2319351697000. Starting simulation...
+info: Entering event queue @ 2319549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2320351697000. Starting simulation...
+info: Entering event queue @ 2320549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2321351697000. Starting simulation...
+info: Entering event queue @ 2321549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2322351697000. Starting simulation...
+info: Entering event queue @ 2322549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2323351697000. Starting simulation...
+info: Entering event queue @ 2323549589500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2324351697000. Starting simulation...
-info: Entering event queue @ 2325088231000. Starting simulation...
+info: Entering event queue @ 2324549589500. Starting simulation...
+info: Entering event queue @ 2325286118000. Starting simulation...
+info: Entering event queue @ 2325286124000. Starting simulation...
switching cpus
-info: Entering event queue @ 2325088237000. Starting simulation...
+info: Entering event queue @ 2325286125500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2326088237000. Starting simulation...
+info: Entering event queue @ 2326286125500. Starting simulation...
switching cpus
-info: Entering event queue @ 2326088238500. Starting simulation...
+info: Entering event queue @ 2326286133000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2327088238500. Starting simulation...
+info: Entering event queue @ 2327286133000. Starting simulation...
switching cpus
-info: Entering event queue @ 2327088324000. Starting simulation...
+info: Entering event queue @ 2327286140500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2328088324000. Starting simulation...
+info: Entering event queue @ 2328286140500. Starting simulation...
switching cpus
-info: Entering event queue @ 2328088325000. Starting simulation...
+info: Entering event queue @ 2328286186000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2329088325000. Starting simulation...
+info: Entering event queue @ 2329286186000. Starting simulation...
switching cpus
-info: Entering event queue @ 2329088480000. Starting simulation...
+info: Entering event queue @ 2329286223000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2330088480000. Starting simulation...
+info: Entering event queue @ 2330286223000. Starting simulation...
switching cpus
-info: Entering event queue @ 2330088481000. Starting simulation...
+info: Entering event queue @ 2330286230500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2331088481000. Starting simulation...
+info: Entering event queue @ 2331286230500. Starting simulation...
switching cpus
-info: Entering event queue @ 2331088482000. Starting simulation...
+info: Entering event queue @ 2331286254000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2332088482000. Starting simulation...
+info: Entering event queue @ 2332286254000. Starting simulation...
switching cpus
-info: Entering event queue @ 2332088483000. Starting simulation...
+info: Entering event queue @ 2332286408000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2333088483000. Starting simulation...
+info: Entering event queue @ 2333286408000. Starting simulation...
switching cpus
-info: Entering event queue @ 2333088484000. Starting simulation...
+info: Entering event queue @ 2333286415500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2334088484000. Starting simulation...
+info: Entering event queue @ 2334286415500. Starting simulation...
switching cpus
-info: Entering event queue @ 2334088485000. Starting simulation...
+info: Entering event queue @ 2334286517000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2335088485000. Starting simulation...
+info: Entering event queue @ 2335286517000. Starting simulation...
switching cpus
-info: Entering event queue @ 2335088511000. Starting simulation...
+info: Entering event queue @ 2335286619000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2336088511000. Starting simulation...
+info: Entering event queue @ 2336286619000. Starting simulation...
switching cpus
-info: Entering event queue @ 2336088552000. Starting simulation...
+info: Entering event queue @ 2336286772000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2337088552000. Starting simulation...
+info: Entering event queue @ 2337286772000. Starting simulation...
switching cpus
-info: Entering event queue @ 2337088554000. Starting simulation...
+info: Entering event queue @ 2337286779500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2338088554000. Starting simulation...
+info: Entering event queue @ 2338286779500. Starting simulation...
switching cpus
-info: Entering event queue @ 2338088597000. Starting simulation...
+info: Entering event queue @ 2338286858000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2339088597000. Starting simulation...
+info: Entering event queue @ 2339286858000. Starting simulation...
switching cpus
-info: Entering event queue @ 2339088612000. Starting simulation...
+info: Entering event queue @ 2339286865500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2340088612000. Starting simulation...
+info: Entering event queue @ 2340286865500. Starting simulation...
switching cpus
-info: Entering event queue @ 2340088674000. Starting simulation...
+info: Entering event queue @ 2340286954000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2341088674000. Starting simulation...
+info: Entering event queue @ 2341286954000. Starting simulation...
switching cpus
-info: Entering event queue @ 2341088772000. Starting simulation...
+info: Entering event queue @ 2341287003000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2342088772000. Starting simulation...
+info: Entering event queue @ 2342287003000. Starting simulation...
switching cpus
-info: Entering event queue @ 2342088773000. Starting simulation...
+info: Entering event queue @ 2342287101000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2343088773000. Starting simulation...
+info: Entering event queue @ 2343287101000. Starting simulation...
switching cpus
-info: Entering event queue @ 2343088775000. Starting simulation...
+info: Entering event queue @ 2343287108500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2344088775000. Starting simulation...
+info: Entering event queue @ 2344287108500. Starting simulation...
switching cpus
-info: Entering event queue @ 2344088789000. Starting simulation...
+info: Entering event queue @ 2344287231000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2345088789000. Starting simulation...
+info: Entering event queue @ 2345287231000. Starting simulation...
switching cpus
-info: Entering event queue @ 2345088919000. Starting simulation...
+info: Entering event queue @ 2345287255000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2346088919000. Starting simulation...
+info: Entering event queue @ 2346287255000. Starting simulation...
switching cpus
-info: Entering event queue @ 2346088990000. Starting simulation...
+info: Entering event queue @ 2346287350000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2347088990000. Starting simulation...
+info: Entering event queue @ 2347287350000. Starting simulation...
switching cpus
-info: Entering event queue @ 2347089092000. Starting simulation...
+info: Entering event queue @ 2347287397000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2348089092000. Starting simulation...
+info: Entering event queue @ 2348287397000. Starting simulation...
switching cpus
-info: Entering event queue @ 2348089095500. Starting simulation...
+info: Entering event queue @ 2348287404500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2349089095500. Starting simulation...
+info: Entering event queue @ 2349287404500. Starting simulation...
switching cpus
-info: Entering event queue @ 2349089096500. Starting simulation...
+info: Entering event queue @ 2349287448000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2350089096500. Starting simulation...
+info: Entering event queue @ 2350287448000. Starting simulation...
switching cpus
-info: Entering event queue @ 2350089098500. Starting simulation...
+info: Entering event queue @ 2350287455500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2351089098500. Starting simulation...
+info: Entering event queue @ 2351287455500. Starting simulation...
switching cpus
-info: Entering event queue @ 2351089113000. Starting simulation...
+info: Entering event queue @ 2351287463000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2352089113000. Starting simulation...
+info: Entering event queue @ 2352287463000. Starting simulation...
switching cpus
-info: Entering event queue @ 2352089199000. Starting simulation...
+info: Entering event queue @ 2352287470500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2353089199000. Starting simulation...
+info: Entering event queue @ 2353287470500. Starting simulation...
switching cpus
-info: Entering event queue @ 2353089200000. Starting simulation...
+info: Entering event queue @ 2353287572000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2354089200000. Starting simulation...
+info: Entering event queue @ 2354287572000. Starting simulation...
switching cpus
-info: Entering event queue @ 2354089248000. Starting simulation...
+info: Entering event queue @ 2354287703000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2355089248000. Starting simulation...
+info: Entering event queue @ 2355287703000. Starting simulation...
switching cpus
-info: Entering event queue @ 2355089265000. Starting simulation...
+info: Entering event queue @ 2355287710500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2356089265000. Starting simulation...
+info: Entering event queue @ 2356287710500. Starting simulation...
switching cpus
-info: Entering event queue @ 2356089316000. Starting simulation...
+info: Entering event queue @ 2356287765000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2357089316000. Starting simulation...
-info: Entering event queue @ 2357824372000. Starting simulation...
+info: Entering event queue @ 2357287765000. Starting simulation...
+info: Entering event queue @ 2358021530000. Starting simulation...
switching cpus
-info: Entering event queue @ 2357824374000. Starting simulation...
+info: Entering event queue @ 2358021532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2358824374000. Starting simulation...
+info: Entering event queue @ 2359021532000. Starting simulation...
switching cpus
-info: Entering event queue @ 2358824488000. Starting simulation...
+info: Entering event queue @ 2359021676000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2359824488000. Starting simulation...
+info: Entering event queue @ 2360021676000. Starting simulation...
switching cpus
-info: Entering event queue @ 2359824489000. Starting simulation...
+info: Entering event queue @ 2360021831000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2360824489000. Starting simulation...
+info: Entering event queue @ 2361021831000. Starting simulation...
switching cpus
-info: Entering event queue @ 2360824618000. Starting simulation...
+info: Entering event queue @ 2361021907000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2361824618000. Starting simulation...
+info: Entering event queue @ 2362021907000. Starting simulation...
switching cpus
-info: Entering event queue @ 2361824637000. Starting simulation...
+info: Entering event queue @ 2362021914500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2362824637000. Starting simulation...
+info: Entering event queue @ 2363021914500. Starting simulation...
switching cpus
-info: Entering event queue @ 2362824638000. Starting simulation...
+info: Entering event queue @ 2363021992000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2363824638000. Starting simulation...
+info: Entering event queue @ 2364021992000. Starting simulation...
switching cpus
-info: Entering event queue @ 2363824687000. Starting simulation...
+info: Entering event queue @ 2364022007000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2364824687000. Starting simulation...
+info: Entering event queue @ 2365022007000. Starting simulation...
switching cpus
-info: Entering event queue @ 2364824823000. Starting simulation...
+info: Entering event queue @ 2365022014500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2365824823000. Starting simulation...
+info: Entering event queue @ 2366022014500. Starting simulation...
switching cpus
-info: Entering event queue @ 2365824964000. Starting simulation...
+info: Entering event queue @ 2366022027000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2366824964000. Starting simulation...
+info: Entering event queue @ 2367022027000. Starting simulation...
switching cpus
-info: Entering event queue @ 2366824989000. Starting simulation...
+info: Entering event queue @ 2367022117000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2367824989000. Starting simulation...
+info: Entering event queue @ 2368022117000. Starting simulation...
switching cpus
-info: Entering event queue @ 2367825012000. Starting simulation...
+info: Entering event queue @ 2368022124500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2368825012000. Starting simulation...
+info: Entering event queue @ 2369022124500. Starting simulation...
switching cpus
-info: Entering event queue @ 2368825145000. Starting simulation...
+info: Entering event queue @ 2369022270000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2369825145000. Starting simulation...
+info: Entering event queue @ 2370022270000. Starting simulation...
switching cpus
-info: Entering event queue @ 2369825146000. Starting simulation...
+info: Entering event queue @ 2370022277500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2370825146000. Starting simulation...
+info: Entering event queue @ 2371022277500. Starting simulation...
switching cpus
-info: Entering event queue @ 2370825288000. Starting simulation...
+info: Entering event queue @ 2371022285000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2371825288000. Starting simulation...
+info: Entering event queue @ 2372022285000. Starting simulation...
switching cpus
-info: Entering event queue @ 2371825289000. Starting simulation...
+info: Entering event queue @ 2372022414000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2372825289000. Starting simulation...
+info: Entering event queue @ 2373022414000. Starting simulation...
switching cpus
-info: Entering event queue @ 2372825296000. Starting simulation...
+info: Entering event queue @ 2373022432000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2373825296000. Starting simulation...
+info: Entering event queue @ 2374022432000. Starting simulation...
switching cpus
-info: Entering event queue @ 2373825361000. Starting simulation...
+info: Entering event queue @ 2374022439500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2374825361000. Starting simulation...
+info: Entering event queue @ 2375022439500. Starting simulation...
switching cpus
-info: Entering event queue @ 2374825463000. Starting simulation...
+info: Entering event queue @ 2375022569000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2375825463000. Starting simulation...
+info: Entering event queue @ 2376022569000. Starting simulation...
switching cpus
-info: Entering event queue @ 2375825612000. Starting simulation...
+info: Entering event queue @ 2376022686000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2376825612000. Starting simulation...
+info: Entering event queue @ 2377022686000. Starting simulation...
switching cpus
-info: Entering event queue @ 2376825684000. Starting simulation...
+info: Entering event queue @ 2377022827000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2377825684000. Starting simulation...
+info: Entering event queue @ 2378022827000. Starting simulation...
switching cpus
-info: Entering event queue @ 2377825750000. Starting simulation...
+info: Entering event queue @ 2378022982000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2378825750000. Starting simulation...
+info: Entering event queue @ 2379022982000. Starting simulation...
switching cpus
-info: Entering event queue @ 2378825867000. Starting simulation...
+info: Entering event queue @ 2379023037000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2379825867000. Starting simulation...
+info: Entering event queue @ 2380023037000. Starting simulation...
switching cpus
-info: Entering event queue @ 2379825907000. Starting simulation...
+info: Entering event queue @ 2380023062000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2380825907000. Starting simulation...
+info: Entering event queue @ 2381023062000. Starting simulation...
switching cpus
-info: Entering event queue @ 2380825985000. Starting simulation...
+info: Entering event queue @ 2381023069500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2381825985000. Starting simulation...
+info: Entering event queue @ 2382023069500. Starting simulation...
switching cpus
-info: Entering event queue @ 2381826127000. Starting simulation...
+info: Entering event queue @ 2382023080500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2382826127000. Starting simulation...
+info: Entering event queue @ 2383023080500. Starting simulation...
switching cpus
-info: Entering event queue @ 2382826217000. Starting simulation...
+info: Entering event queue @ 2383023209000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2383826217000. Starting simulation...
+info: Entering event queue @ 2384023209000. Starting simulation...
switching cpus
-info: Entering event queue @ 2383826218000. Starting simulation...
+info: Entering event queue @ 2384023216500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2384826218000. Starting simulation...
+info: Entering event queue @ 2385023216500. Starting simulation...
switching cpus
-info: Entering event queue @ 2384826219000. Starting simulation...
+info: Entering event queue @ 2385023294000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2385826219000. Starting simulation...
+info: Entering event queue @ 2386023294000. Starting simulation...
switching cpus
-info: Entering event queue @ 2385826249000. Starting simulation...
+info: Entering event queue @ 2386023307500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2386826249000. Starting simulation...
+info: Entering event queue @ 2387023307500. Starting simulation...
switching cpus
-info: Entering event queue @ 2386826330000. Starting simulation...
+info: Entering event queue @ 2387023398000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2387826330000. Starting simulation...
+info: Entering event queue @ 2388023398000. Starting simulation...
switching cpus
-info: Entering event queue @ 2387826331000. Starting simulation...
+info: Entering event queue @ 2388023422000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2388826331000. Starting simulation...
+info: Entering event queue @ 2389023422000. Starting simulation...
switching cpus
-info: Entering event queue @ 2388826388000. Starting simulation...
+info: Entering event queue @ 2389023429500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2389826388000. Starting simulation...
-info: Entering event queue @ 2390560663000. Starting simulation...
+info: Entering event queue @ 2390023429500. Starting simulation...
+info: Entering event queue @ 2390758151000. Starting simulation...
switching cpus
-info: Entering event queue @ 2390560665000. Starting simulation...
+info: Entering event queue @ 2390758153000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2391560665000. Starting simulation...
+info: Entering event queue @ 2391758153000. Starting simulation...
switching cpus
-info: Entering event queue @ 2391560666000. Starting simulation...
+info: Entering event queue @ 2391758161000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2392560666000. Starting simulation...
+info: Entering event queue @ 2392758161000. Starting simulation...
switching cpus
-info: Entering event queue @ 2392560703000. Starting simulation...
+info: Entering event queue @ 2392758168500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2393560703000. Starting simulation...
+info: Entering event queue @ 2393758168500. Starting simulation...
switching cpus
-info: Entering event queue @ 2393560798000. Starting simulation...
+info: Entering event queue @ 2393758292000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2394560798000. Starting simulation...
+info: Entering event queue @ 2394758292000. Starting simulation...
switching cpus
-info: Entering event queue @ 2394560799000. Starting simulation...
+info: Entering event queue @ 2394758302000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2395560799000. Starting simulation...
+info: Entering event queue @ 2395758302000. Starting simulation...
switching cpus
-info: Entering event queue @ 2395560928000. Starting simulation...
+info: Entering event queue @ 2395758458000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2396560928000. Starting simulation...
+info: Entering event queue @ 2396758458000. Starting simulation...
switching cpus
-info: Entering event queue @ 2396561075000. Starting simulation...
+info: Entering event queue @ 2396758470000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2397561075000. Starting simulation...
+info: Entering event queue @ 2397758470000. Starting simulation...
switching cpus
-info: Entering event queue @ 2397561139000. Starting simulation...
+info: Entering event queue @ 2397758606000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2398561139000. Starting simulation...
+info: Entering event queue @ 2398758606000. Starting simulation...
switching cpus
-info: Entering event queue @ 2398561189000. Starting simulation...
+info: Entering event queue @ 2398758753000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2399561189000. Starting simulation...
+info: Entering event queue @ 2399758753000. Starting simulation...
switching cpus
-info: Entering event queue @ 2399561344000. Starting simulation...
+info: Entering event queue @ 2399758906000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2400561344000. Starting simulation...
+info: Entering event queue @ 2400758906000. Starting simulation...
switching cpus
-info: Entering event queue @ 2400561484000. Starting simulation...
+info: Entering event queue @ 2400759041000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2401561484000. Starting simulation...
+info: Entering event queue @ 2401759041000. Starting simulation...
switching cpus
-info: Entering event queue @ 2401561534000. Starting simulation...
+info: Entering event queue @ 2401759189000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2402561534000. Starting simulation...
+info: Entering event queue @ 2402759189000. Starting simulation...
switching cpus
-info: Entering event queue @ 2402561628000. Starting simulation...
+info: Entering event queue @ 2402759220000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2403561628000. Starting simulation...
+info: Entering event queue @ 2403759220000. Starting simulation...
switching cpus
-info: Entering event queue @ 2403561712000. Starting simulation...
+info: Entering event queue @ 2403759362000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2404561712000. Starting simulation...
+info: Entering event queue @ 2404759362000. Starting simulation...
switching cpus
-info: Entering event queue @ 2404561726000. Starting simulation...
+info: Entering event queue @ 2404759454000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2405561726000. Starting simulation...
+info: Entering event queue @ 2405759454000. Starting simulation...
switching cpus
-info: Entering event queue @ 2405561835000. Starting simulation...
+info: Entering event queue @ 2405759609000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2406561835000. Starting simulation...
+info: Entering event queue @ 2406759609000. Starting simulation...
switching cpus
-info: Entering event queue @ 2406561960000. Starting simulation...
+info: Entering event queue @ 2406759693000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2407561960000. Starting simulation...
+info: Entering event queue @ 2407759693000. Starting simulation...
switching cpus
-info: Entering event queue @ 2407562071000. Starting simulation...
+info: Entering event queue @ 2407759791000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2408562071000. Starting simulation...
+info: Entering event queue @ 2408759791000. Starting simulation...
switching cpus
-info: Entering event queue @ 2408562185000. Starting simulation...
+info: Entering event queue @ 2408759806000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2409562185000. Starting simulation...
+info: Entering event queue @ 2409759806000. Starting simulation...
switching cpus
-info: Entering event queue @ 2409562309000. Starting simulation...
+info: Entering event queue @ 2409759845000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2410562309000. Starting simulation...
+info: Entering event queue @ 2410759845000. Starting simulation...
switching cpus
-info: Entering event queue @ 2410562346000. Starting simulation...
+info: Entering event queue @ 2410759950000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2411562346000. Starting simulation...
+info: Entering event queue @ 2411759950000. Starting simulation...
switching cpus
-info: Entering event queue @ 2411562485000. Starting simulation...
+info: Entering event queue @ 2411759976000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2412562485000. Starting simulation...
+info: Entering event queue @ 2412759976000. Starting simulation...
switching cpus
-info: Entering event queue @ 2412562486000. Starting simulation...
+info: Entering event queue @ 2412759983500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2413562486000. Starting simulation...
+info: Entering event queue @ 2413759983500. Starting simulation...
switching cpus
-info: Entering event queue @ 2413562559000. Starting simulation...
+info: Entering event queue @ 2413760084000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2414562559000. Starting simulation...
+info: Entering event queue @ 2414760084000. Starting simulation...
switching cpus
-info: Entering event queue @ 2414562654000. Starting simulation...
+info: Entering event queue @ 2414760142000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2415562654000. Starting simulation...
+info: Entering event queue @ 2415760142000. Starting simulation...
switching cpus
-info: Entering event queue @ 2415562655000. Starting simulation...
+info: Entering event queue @ 2415760169000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2416562655000. Starting simulation...
+info: Entering event queue @ 2416760169000. Starting simulation...
switching cpus
-info: Entering event queue @ 2416562810000. Starting simulation...
+info: Entering event queue @ 2416760278000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2417562810000. Starting simulation...
+info: Entering event queue @ 2417760278000. Starting simulation...
switching cpus
-info: Entering event queue @ 2417562871000. Starting simulation...
+info: Entering event queue @ 2417760378000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2418562871000. Starting simulation...
+info: Entering event queue @ 2418760378000. Starting simulation...
switching cpus
-info: Entering event queue @ 2418562872000. Starting simulation...
+info: Entering event queue @ 2418760524000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2419562872000. Starting simulation...
+info: Entering event queue @ 2419760524000. Starting simulation...
switching cpus
-info: Entering event queue @ 2419562919000. Starting simulation...
+info: Entering event queue @ 2419760601000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2420562919000. Starting simulation...
+info: Entering event queue @ 2420760601000. Starting simulation...
switching cpus
-info: Entering event queue @ 2420562986000. Starting simulation...
+info: Entering event queue @ 2420760619000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2421562986000. Starting simulation...
+info: Entering event queue @ 2421760619000. Starting simulation...
switching cpus
-info: Entering event queue @ 2421562987000. Starting simulation...
+info: Entering event queue @ 2421760647000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2422562987000. Starting simulation...
-info: Entering event queue @ 2423297572000. Starting simulation...
+info: Entering event queue @ 2422760647000. Starting simulation...
+info: Entering event queue @ 2423494730000. Starting simulation...
switching cpus
-info: Entering event queue @ 2423297574000. Starting simulation...
+info: Entering event queue @ 2423494732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2424297574000. Starting simulation...
+info: Entering event queue @ 2424494732000. Starting simulation...
switching cpus
-info: Entering event queue @ 2424297699000. Starting simulation...
+info: Entering event queue @ 2424494817000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2425297699000. Starting simulation...
switching cpus
-info: Entering event queue @ 2425297786000. Starting simulation...
+info: Entering event queue @ 2425494817000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2426297786000. Starting simulation...
+info: Entering event queue @ 2426494817000. Starting simulation...
switching cpus
-info: Entering event queue @ 2426297856000. Starting simulation...
+info: Entering event queue @ 2426494898000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2427297856000. Starting simulation...
+info: Entering event queue @ 2427494898000. Starting simulation...
switching cpus
-info: Entering event queue @ 2427298009000. Starting simulation...
+info: Entering event queue @ 2427494973000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2428298009000. Starting simulation...
+info: Entering event queue @ 2428494973000. Starting simulation...
switching cpus
-info: Entering event queue @ 2428298043000. Starting simulation...
+info: Entering event queue @ 2428494980500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2429298043000. Starting simulation...
+info: Entering event queue @ 2429494980500. Starting simulation...
switching cpus
-info: Entering event queue @ 2429298115000. Starting simulation...
+info: Entering event queue @ 2429495036000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2430298115000. Starting simulation...
+info: Entering event queue @ 2430495036000. Starting simulation...
switching cpus
-info: Entering event queue @ 2430298116000. Starting simulation...
+info: Entering event queue @ 2430495139000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2431298116000. Starting simulation...
+info: Entering event queue @ 2431495139000. Starting simulation...
switching cpus
-info: Entering event queue @ 2431298128000. Starting simulation...
+info: Entering event queue @ 2431495146500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2432298128000. Starting simulation...
+info: Entering event queue @ 2432495146500. Starting simulation...
switching cpus
-info: Entering event queue @ 2432298154000. Starting simulation...
+info: Entering event queue @ 2432495281000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2433298154000. Starting simulation...
+info: Entering event queue @ 2433495281000. Starting simulation...
switching cpus
-info: Entering event queue @ 2433298155000. Starting simulation...
+info: Entering event queue @ 2433495390000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2434298155000. Starting simulation...
+info: Entering event queue @ 2434495390000. Starting simulation...
switching cpus
-info: Entering event queue @ 2434298209000. Starting simulation...
+info: Entering event queue @ 2434495397500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2435298209000. Starting simulation...
+info: Entering event queue @ 2435495397500. Starting simulation...
switching cpus
-info: Entering event queue @ 2435298264000. Starting simulation...
+info: Entering event queue @ 2435495416000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2436298264000. Starting simulation...
+info: Entering event queue @ 2436495416000. Starting simulation...
switching cpus
-info: Entering event queue @ 2436298295000. Starting simulation...
+info: Entering event queue @ 2436495532000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2437298295000. Starting simulation...
+info: Entering event queue @ 2437495532000. Starting simulation...
switching cpus
-info: Entering event queue @ 2437298393000. Starting simulation...
+info: Entering event queue @ 2437495571000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2438298393000. Starting simulation...
+info: Entering event queue @ 2438495571000. Starting simulation...
switching cpus
-info: Entering event queue @ 2438298535000. Starting simulation...
+info: Entering event queue @ 2438495727000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2439298535000. Starting simulation...
+info: Entering event queue @ 2439495727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2439298588000. Starting simulation...
+info: Entering event queue @ 2439495866000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2440298588000. Starting simulation...
+info: Entering event queue @ 2440495866000. Starting simulation...
switching cpus
-info: Entering event queue @ 2440298715000. Starting simulation...
+info: Entering event queue @ 2440495930000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2441298715000. Starting simulation...
+info: Entering event queue @ 2441495930000. Starting simulation...
switching cpus
-info: Entering event queue @ 2441298826000. Starting simulation...
+info: Entering event queue @ 2441495956000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2442298826000. Starting simulation...
+info: Entering event queue @ 2442495956000. Starting simulation...
switching cpus
-info: Entering event queue @ 2442298827000. Starting simulation...
+info: Entering event queue @ 2442496014000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2443298827000. Starting simulation...
+info: Entering event queue @ 2443496014000. Starting simulation...
switching cpus
-info: Entering event queue @ 2443298920000. Starting simulation...
+info: Entering event queue @ 2443496047000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2444298920000. Starting simulation...
+info: Entering event queue @ 2444496047000. Starting simulation...
switching cpus
-info: Entering event queue @ 2444298968000. Starting simulation...
+info: Entering event queue @ 2444496070000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2445298968000. Starting simulation...
+info: Entering event queue @ 2445496070000. Starting simulation...
switching cpus
-info: Entering event queue @ 2445298969000. Starting simulation...
+info: Entering event queue @ 2445496224000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2446298969000. Starting simulation...
+info: Entering event queue @ 2446496224000. Starting simulation...
switching cpus
-info: Entering event queue @ 2446299109000. Starting simulation...
+info: Entering event queue @ 2446496340000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2447299109000. Starting simulation...
+info: Entering event queue @ 2447496340000. Starting simulation...
switching cpus
-info: Entering event queue @ 2447299228000. Starting simulation...
+info: Entering event queue @ 2447496437000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2448299228000. Starting simulation...
+info: Entering event queue @ 2448496437000. Starting simulation...
switching cpus
-info: Entering event queue @ 2448299344000. Starting simulation...
+info: Entering event queue @ 2448496470000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2449299344000. Starting simulation...
+info: Entering event queue @ 2449496470000. Starting simulation...
switching cpus
-info: Entering event queue @ 2449299491000. Starting simulation...
+info: Entering event queue @ 2449496529000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2450299491000. Starting simulation...
+info: Entering event queue @ 2450496529000. Starting simulation...
switching cpus
-info: Entering event queue @ 2450299553000. Starting simulation...
+info: Entering event queue @ 2450496616000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2451299553000. Starting simulation...
+info: Entering event queue @ 2451496616000. Starting simulation...
switching cpus
-info: Entering event queue @ 2451299683000. Starting simulation...
+info: Entering event queue @ 2451496657000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2452299683000. Starting simulation...
+info: Entering event queue @ 2452496657000. Starting simulation...
switching cpus
-info: Entering event queue @ 2452299768000. Starting simulation...
+info: Entering event queue @ 2452496803000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2453299768000. Starting simulation...
+info: Entering event queue @ 2453496803000. Starting simulation...
switching cpus
-info: Entering event queue @ 2453299890000. Starting simulation...
+info: Entering event queue @ 2453496810500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2454299890000. Starting simulation...
+info: Entering event queue @ 2454496810500. Starting simulation...
switching cpus
-info: Entering event queue @ 2454299959000. Starting simulation...
+info: Entering event queue @ 2454496936000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2455299959000. Starting simulation...
-info: Entering event queue @ 2456033037000. Starting simulation...
+info: Entering event queue @ 2455496936000. Starting simulation...
+info: Entering event queue @ 2456231330000. Starting simulation...
switching cpus
-info: Entering event queue @ 2456033039000. Starting simulation...
+info: Entering event queue @ 2456231332000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2457033039000. Starting simulation...
+info: Entering event queue @ 2457231332000. Starting simulation...
switching cpus
-info: Entering event queue @ 2457033167000. Starting simulation...
+info: Entering event queue @ 2457231468000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2458033167000. Starting simulation...
+info: Entering event queue @ 2458231468000. Starting simulation...
switching cpus
-info: Entering event queue @ 2458033184000. Starting simulation...
+info: Entering event queue @ 2458231599000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2459033184000. Starting simulation...
+info: Entering event queue @ 2459231599000. Starting simulation...
switching cpus
-info: Entering event queue @ 2459033282000. Starting simulation...
+info: Entering event queue @ 2459231662000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2460033282000. Starting simulation...
+info: Entering event queue @ 2460231662000. Starting simulation...
switching cpus
-info: Entering event queue @ 2460033316000. Starting simulation...
+info: Entering event queue @ 2460231735000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2461033316000. Starting simulation...
+info: Entering event queue @ 2461231735000. Starting simulation...
switching cpus
-info: Entering event queue @ 2461033409000. Starting simulation...
+info: Entering event queue @ 2461231751000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2462033409000. Starting simulation...
+info: Entering event queue @ 2462231751000. Starting simulation...
switching cpus
-info: Entering event queue @ 2462033511000. Starting simulation...
+info: Entering event queue @ 2462231781000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2463033511000. Starting simulation...
+info: Entering event queue @ 2463231781000. Starting simulation...
switching cpus
-info: Entering event queue @ 2463033638000. Starting simulation...
+info: Entering event queue @ 2463231788500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2464033638000. Starting simulation...
+info: Entering event queue @ 2464231788500. Starting simulation...
switching cpus
-info: Entering event queue @ 2464033758000. Starting simulation...
+info: Entering event queue @ 2464231848000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2465033758000. Starting simulation...
+info: Entering event queue @ 2465231848000. Starting simulation...
switching cpus
-info: Entering event queue @ 2465033759000. Starting simulation...
+info: Entering event queue @ 2465231865000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2466033759000. Starting simulation...
+info: Entering event queue @ 2466231865000. Starting simulation...
switching cpus
-info: Entering event queue @ 2466033904000. Starting simulation...
+info: Entering event queue @ 2466231917000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2467033904000. Starting simulation...
+info: Entering event queue @ 2467231917000. Starting simulation...
switching cpus
-info: Entering event queue @ 2467033927000. Starting simulation...
+info: Entering event queue @ 2467232004000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2468033927000. Starting simulation...
+info: Entering event queue @ 2468232004000. Starting simulation...
switching cpus
-info: Entering event queue @ 2468034035000. Starting simulation...
+info: Entering event queue @ 2468232072000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2469034035000. Starting simulation...
+info: Entering event queue @ 2469232072000. Starting simulation...
switching cpus
-info: Entering event queue @ 2469034153000. Starting simulation...
+info: Entering event queue @ 2469232192000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2470034153000. Starting simulation...
+info: Entering event queue @ 2470232192000. Starting simulation...
switching cpus
-info: Entering event queue @ 2470034198000. Starting simulation...
+info: Entering event queue @ 2470232287000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2471034198000. Starting simulation...
+info: Entering event queue @ 2471232287000. Starting simulation...
switching cpus
-info: Entering event queue @ 2471034246000. Starting simulation...
+info: Entering event queue @ 2471232409000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2472034246000. Starting simulation...
+info: Entering event queue @ 2472232409000. Starting simulation...
switching cpus
-info: Entering event queue @ 2472034313000. Starting simulation...
+info: Entering event queue @ 2472232561000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2473034313000. Starting simulation...
+info: Entering event queue @ 2473232561000. Starting simulation...
switching cpus
-info: Entering event queue @ 2473034456000. Starting simulation...
+info: Entering event queue @ 2473232685000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2474034456000. Starting simulation...
+info: Entering event queue @ 2474232685000. Starting simulation...
switching cpus
-info: Entering event queue @ 2474034604000. Starting simulation...
+info: Entering event queue @ 2474232739000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2475034604000. Starting simulation...
+info: Entering event queue @ 2475232739000. Starting simulation...
switching cpus
-info: Entering event queue @ 2475034749000. Starting simulation...
+info: Entering event queue @ 2475232746500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2476034749000. Starting simulation...
+info: Entering event queue @ 2476232746500. Starting simulation...
switching cpus
-info: Entering event queue @ 2476034794000. Starting simulation...
+info: Entering event queue @ 2476232869000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2477034794000. Starting simulation...
+info: Entering event queue @ 2477232869000. Starting simulation...
switching cpus
-info: Entering event queue @ 2477034802000. Starting simulation...
+info: Entering event queue @ 2477232953000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2478034802000. Starting simulation...
+info: Entering event queue @ 2478232953000. Starting simulation...
switching cpus
-info: Entering event queue @ 2478034803000. Starting simulation...
+info: Entering event queue @ 2478232960500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2479034803000. Starting simulation...
+info: Entering event queue @ 2479232960500. Starting simulation...
switching cpus
-info: Entering event queue @ 2479034908000. Starting simulation...
+info: Entering event queue @ 2479232968000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2480034908000. Starting simulation...
+info: Entering event queue @ 2480232968000. Starting simulation...
switching cpus
-info: Entering event queue @ 2480034957000. Starting simulation...
+info: Entering event queue @ 2480233089000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2481034957000. Starting simulation...
+info: Entering event queue @ 2481233089000. Starting simulation...
switching cpus
-info: Entering event queue @ 2481034958000. Starting simulation...
+info: Entering event queue @ 2481233134000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2482034958000. Starting simulation...
+info: Entering event queue @ 2482233134000. Starting simulation...
switching cpus
-info: Entering event queue @ 2482035090000. Starting simulation...
+info: Entering event queue @ 2482233141500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2483035090000. Starting simulation...
+info: Entering event queue @ 2483233141500. Starting simulation...
switching cpus
-info: Entering event queue @ 2483035091000. Starting simulation...
+info: Entering event queue @ 2483233286000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2484035091000. Starting simulation...
+info: Entering event queue @ 2484233286000. Starting simulation...
switching cpus
-info: Entering event queue @ 2484035144000. Starting simulation...
+info: Entering event queue @ 2484233426000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2485035144000. Starting simulation...
+info: Entering event queue @ 2485233426000. Starting simulation...
switching cpus
-info: Entering event queue @ 2485035271000. Starting simulation...
+info: Entering event queue @ 2485233556000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2486035271000. Starting simulation...
-info: Entering event queue @ 2486035296500. Starting simulation...
+info: Entering event queue @ 2486233556000. Starting simulation...
switching cpus
-info: Entering event queue @ 2486035328001. Starting simulation...
+info: Entering event queue @ 2486233563500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2487035328001. Starting simulation...
+info: Entering event queue @ 2487233563500. Starting simulation...
switching cpus
-info: Entering event queue @ 2487035397000. Starting simulation...
+info: Entering event queue @ 2487233646000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2488035397000. Starting simulation...
-info: Entering event queue @ 2488769554000. Starting simulation...
+info: Entering event queue @ 2488233646000. Starting simulation...
+info: Entering event queue @ 2488966935000. Starting simulation...
switching cpus
-info: Entering event queue @ 2488769556000. Starting simulation...
+info: Entering event queue @ 2488966937000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2489769556000. Starting simulation...
+info: Entering event queue @ 2489966937000. Starting simulation...
switching cpus
-info: Entering event queue @ 2489769557000. Starting simulation...
+info: Entering event queue @ 2489966944500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2490769557000. Starting simulation...
+info: Entering event queue @ 2490966944500. Starting simulation...
switching cpus
-info: Entering event queue @ 2490769609000. Starting simulation...
+info: Entering event queue @ 2490967075000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2491769609000. Starting simulation...
+info: Entering event queue @ 2491967075000. Starting simulation...
switching cpus
-info: Entering event queue @ 2491769729000. Starting simulation...
+info: Entering event queue @ 2491967146000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2492769729000. Starting simulation...
+info: Entering event queue @ 2492967146000. Starting simulation...
switching cpus
-info: Entering event queue @ 2492769746000. Starting simulation...
+info: Entering event queue @ 2492967153500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2493769746000. Starting simulation...
+info: Entering event queue @ 2493967153500. Starting simulation...
switching cpus
-info: Entering event queue @ 2493769816000. Starting simulation...
+info: Entering event queue @ 2493967161000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2494769816000. Starting simulation...
+info: Entering event queue @ 2494967161000. Starting simulation...
switching cpus
-info: Entering event queue @ 2494769817000. Starting simulation...
+info: Entering event queue @ 2494967168500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2495769817000. Starting simulation...
+info: Entering event queue @ 2495967168500. Starting simulation...
switching cpus
-info: Entering event queue @ 2495769874000. Starting simulation...
+info: Entering event queue @ 2495967212000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2496769874000. Starting simulation...
+info: Entering event queue @ 2496967212000. Starting simulation...
switching cpus
-info: Entering event queue @ 2496769981000. Starting simulation...
+info: Entering event queue @ 2496967335000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2497769981000. Starting simulation...
switching cpus
-info: Entering event queue @ 2497769982000. Starting simulation...
+info: Entering event queue @ 2497967335000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2498769982000. Starting simulation...
+info: Entering event queue @ 2498967335000. Starting simulation...
switching cpus
-info: Entering event queue @ 2498770059000. Starting simulation...
+info: Entering event queue @ 2498967427000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2499770059000. Starting simulation...
+info: Entering event queue @ 2499967427000. Starting simulation...
switching cpus
-info: Entering event queue @ 2499770067000. Starting simulation...
+info: Entering event queue @ 2499967545000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2500770067000. Starting simulation...
+info: Entering event queue @ 2500967545000. Starting simulation...
switching cpus
-info: Entering event queue @ 2500770068000. Starting simulation...
+info: Entering event queue @ 2500967552500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2501770068000. Starting simulation...
+info: Entering event queue @ 2501967552500. Starting simulation...
switching cpus
-info: Entering event queue @ 2501770143000. Starting simulation...
+info: Entering event queue @ 2501967556000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2502770143000. Starting simulation...
+info: Entering event queue @ 2502967556000. Starting simulation...
switching cpus
-info: Entering event queue @ 2502770205000. Starting simulation...
+info: Entering event queue @ 2502967624000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2503770205000. Starting simulation...
+info: Entering event queue @ 2503967624000. Starting simulation...
switching cpus
-info: Entering event queue @ 2503770206000. Starting simulation...
+info: Entering event queue @ 2503967631500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2504770206000. Starting simulation...
+info: Entering event queue @ 2504967631500. Starting simulation...
switching cpus
-info: Entering event queue @ 2504770245000. Starting simulation...
+info: Entering event queue @ 2504967739000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2505770245000. Starting simulation...
+info: Entering event queue @ 2505967739000. Starting simulation...
switching cpus
-info: Entering event queue @ 2505770337000. Starting simulation...
+info: Entering event queue @ 2505967746500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2506770337000. Starting simulation...
+info: Entering event queue @ 2506967746500. Starting simulation...
switching cpus
-info: Entering event queue @ 2506770376000. Starting simulation...
+info: Entering event queue @ 2506967777000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2507770376000. Starting simulation...
+info: Entering event queue @ 2507967777000. Starting simulation...
switching cpus
-info: Entering event queue @ 2507770429000. Starting simulation...
+info: Entering event queue @ 2507967850000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2508770429000. Starting simulation...
+info: Entering event queue @ 2508967850000. Starting simulation...
switching cpus
-info: Entering event queue @ 2508770532000. Starting simulation...
+info: Entering event queue @ 2508967857500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2509770532000. Starting simulation...
+info: Entering event queue @ 2509967857500. Starting simulation...
switching cpus
-info: Entering event queue @ 2509770565000. Starting simulation...
+info: Entering event queue @ 2509967904000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2510770565000. Starting simulation...
+info: Entering event queue @ 2510967904000. Starting simulation...
switching cpus
-info: Entering event queue @ 2510770668000. Starting simulation...
+info: Entering event queue @ 2510968030000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2511770668000. Starting simulation...
+info: Entering event queue @ 2511968030000. Starting simulation...
switching cpus
-info: Entering event queue @ 2511770737000. Starting simulation...
+info: Entering event queue @ 2511968037500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2512770737000. Starting simulation...
+info: Entering event queue @ 2512968037500. Starting simulation...
switching cpus
-info: Entering event queue @ 2512770886000. Starting simulation...
+info: Entering event queue @ 2512968149000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2513770886000. Starting simulation...
+info: Entering event queue @ 2513968149000. Starting simulation...
switching cpus
-info: Entering event queue @ 2513770887000. Starting simulation...
+info: Entering event queue @ 2513968255000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2514770887000. Starting simulation...
+info: Entering event queue @ 2514968255000. Starting simulation...
switching cpus
-info: Entering event queue @ 2514771013000. Starting simulation...
+info: Entering event queue @ 2514968262500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2515771013000. Starting simulation...
+info: Entering event queue @ 2515968262500. Starting simulation...
switching cpus
-info: Entering event queue @ 2515771025000. Starting simulation...
+info: Entering event queue @ 2515968353000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2516771025000. Starting simulation...
+info: Entering event queue @ 2516968353000. Starting simulation...
switching cpus
-info: Entering event queue @ 2516771132000. Starting simulation...
+info: Entering event queue @ 2516968367000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2517771132000. Starting simulation...
+info: Entering event queue @ 2517968367000. Starting simulation...
switching cpus
-info: Entering event queue @ 2517771133000. Starting simulation...
+info: Entering event queue @ 2517968374500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2518771133000. Starting simulation...
+info: Entering event queue @ 2518968374500. Starting simulation...
switching cpus
-info: Entering event queue @ 2518771270000. Starting simulation...
+info: Entering event queue @ 2518968382000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2519771270000. Starting simulation...
+info: Entering event queue @ 2519968382000. Starting simulation...
switching cpus
-info: Entering event queue @ 2519771364000. Starting simulation...
+info: Entering event queue @ 2519968393000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2520771364000. Starting simulation...
-info: Entering event queue @ 2521505845000. Starting simulation...
+info: Entering event queue @ 2520968393000. Starting simulation...
+info: Entering event queue @ 2521703535000. Starting simulation...
switching cpus
-info: Entering event queue @ 2521505847000. Starting simulation...
+info: Entering event queue @ 2521703537000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2522505847000. Starting simulation...
+info: Entering event queue @ 2522703537000. Starting simulation...
switching cpus
-info: Entering event queue @ 2522505848000. Starting simulation...
+info: Entering event queue @ 2522703612000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2523505848000. Starting simulation...
+info: Entering event queue @ 2523703612000. Starting simulation...
switching cpus
-info: Entering event queue @ 2523505849000. Starting simulation...
+info: Entering event queue @ 2523703619500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2524505849000. Starting simulation...
+info: Entering event queue @ 2524703619500. Starting simulation...
switching cpus
-info: Entering event queue @ 2524505850000. Starting simulation...
+info: Entering event queue @ 2524703726000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2525505850000. Starting simulation...
+info: Entering event queue @ 2525703726000. Starting simulation...
switching cpus
-info: Entering event queue @ 2525505953000. Starting simulation...
+info: Entering event queue @ 2525703841000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2526505953000. Starting simulation...
+info: Entering event queue @ 2526703841000. Starting simulation...
+info: Entering event queue @ 2526703980500. Starting simulation...
switching cpus
-info: Entering event queue @ 2526505954000. Starting simulation...
+info: Entering event queue @ 2526703988000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2527505954000. Starting simulation...
-info: Entering event queue @ 2527505964000. Starting simulation...
+info: Entering event queue @ 2527703988000. Starting simulation...
switching cpus
-info: Entering event queue @ 2527505965500. Starting simulation...
+info: Entering event queue @ 2527704057000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2528505965500. Starting simulation...
+info: Entering event queue @ 2528704057000. Starting simulation...
+info: Entering event queue @ 2528704070000. Starting simulation...
switching cpus
-info: Entering event queue @ 2528506085000. Starting simulation...
+info: Entering event queue @ 2528704072500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2529506085000. Starting simulation...
+info: Entering event queue @ 2529704072500. Starting simulation...
switching cpus
-info: Entering event queue @ 2529506182000. Starting simulation...
+info: Entering event queue @ 2529704080000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2530506182000. Starting simulation...
+info: Entering event queue @ 2530704080000. Starting simulation...
switching cpus
-info: Entering event queue @ 2530506241000. Starting simulation...
+info: Entering event queue @ 2530704175000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2531506241000. Starting simulation...
+info: Entering event queue @ 2531704175000. Starting simulation...
switching cpus
-info: Entering event queue @ 2531506368000. Starting simulation...
+info: Entering event queue @ 2531704259000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2532506368000. Starting simulation...
+info: Entering event queue @ 2532704259000. Starting simulation...
switching cpus
-info: Entering event queue @ 2532506400000. Starting simulation...
+info: Entering event queue @ 2532704266500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2533506400000. Starting simulation...
+info: Entering event queue @ 2533704266500. Starting simulation...
switching cpus
-info: Entering event queue @ 2533506404000. Starting simulation...
+info: Entering event queue @ 2533704275000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2534506404000. Starting simulation...
+info: Entering event queue @ 2534704275000. Starting simulation...
switching cpus
-info: Entering event queue @ 2534506527000. Starting simulation...
+info: Entering event queue @ 2534704354000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2535506527000. Starting simulation...
+info: Entering event queue @ 2535704354000. Starting simulation...
switching cpus
-info: Entering event queue @ 2535506668000. Starting simulation...
+info: Entering event queue @ 2535704361500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2536506668000. Starting simulation...
+info: Entering event queue @ 2536704361500. Starting simulation...
switching cpus
-info: Entering event queue @ 2536506816000. Starting simulation...
+info: Entering event queue @ 2536704449000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2537506816000. Starting simulation...
+info: Entering event queue @ 2537704449000. Starting simulation...
switching cpus
-info: Entering event queue @ 2537506817000. Starting simulation...
+info: Entering event queue @ 2537704557000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2538506817000. Starting simulation...
+info: Entering event queue @ 2538704557000. Starting simulation...
switching cpus
-info: Entering event queue @ 2538506962000. Starting simulation...
+info: Entering event queue @ 2538704705000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2539506962000. Starting simulation...
+info: Entering event queue @ 2539704705000. Starting simulation...
switching cpus
-info: Entering event queue @ 2539507054000. Starting simulation...
+info: Entering event queue @ 2539704773000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2540507054000. Starting simulation...
+info: Entering event queue @ 2540704773000. Starting simulation...
switching cpus
-info: Entering event queue @ 2540507055000. Starting simulation...
+info: Entering event queue @ 2540704780500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2541507055000. Starting simulation...
+info: Entering event queue @ 2541704780500. Starting simulation...
switching cpus
-info: Entering event queue @ 2541507057000. Starting simulation...
+info: Entering event queue @ 2541704788000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2542507057000. Starting simulation...
+info: Entering event queue @ 2542704788000. Starting simulation...
switching cpus
-info: Entering event queue @ 2542507129000. Starting simulation...
+info: Entering event queue @ 2542704795500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2543507129000. Starting simulation...
+info: Entering event queue @ 2543704795500. Starting simulation...
switching cpus
-info: Entering event queue @ 2543507190000. Starting simulation...
+info: Entering event queue @ 2543704917000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2544507190000. Starting simulation...
+info: Entering event queue @ 2544704917000. Starting simulation...
switching cpus
-info: Entering event queue @ 2544507208000. Starting simulation...
+info: Entering event queue @ 2544705016000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2545507208000. Starting simulation...
+info: Entering event queue @ 2545705016000. Starting simulation...
switching cpus
-info: Entering event queue @ 2545507209000. Starting simulation...
+info: Entering event queue @ 2545705132000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2546507209000. Starting simulation...
+info: Entering event queue @ 2546705132000. Starting simulation...
switching cpus
-info: Entering event queue @ 2546507292000. Starting simulation...
+info: Entering event queue @ 2546705217000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2547507292000. Starting simulation...
+info: Entering event queue @ 2547705217000. Starting simulation...
switching cpus
-info: Entering event queue @ 2547507296000. Starting simulation...
+info: Entering event queue @ 2547705224500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2548507296000. Starting simulation...
+info: Entering event queue @ 2548705224500. Starting simulation...
switching cpus
-info: Entering event queue @ 2548507297000. Starting simulation...
+info: Entering event queue @ 2548705235000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2549507297000. Starting simulation...
+info: Entering event queue @ 2549705235000. Starting simulation...
switching cpus
-info: Entering event queue @ 2549507392000. Starting simulation...
+info: Entering event queue @ 2549705357000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2550507392000. Starting simulation...
+info: Entering event queue @ 2550705357000. Starting simulation...
switching cpus
-info: Entering event queue @ 2550507429000. Starting simulation...
+info: Entering event queue @ 2550705364500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2551507429000. Starting simulation...
+info: Entering event queue @ 2551705364500. Starting simulation...
switching cpus
-info: Entering event queue @ 2551507430000. Starting simulation...
+info: Entering event queue @ 2551705395000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2552507430000. Starting simulation...
+info: Entering event queue @ 2552705395000. Starting simulation...
switching cpus
-info: Entering event queue @ 2552507449000. Starting simulation...
+info: Entering event queue @ 2552705402500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2553507449000. Starting simulation...
-info: Entering event queue @ 2554241989000. Starting simulation...
+info: Entering event queue @ 2553705402500. Starting simulation...
+info: Entering event queue @ 2554438939000. Starting simulation...
switching cpus
-info: Entering event queue @ 2554241991000. Starting simulation...
+info: Entering event queue @ 2554438946500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2555241991000. Starting simulation...
+info: Entering event queue @ 2555438946500. Starting simulation...
switching cpus
-info: Entering event queue @ 2555241999500. Starting simulation...
+info: Entering event queue @ 2555438954000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2556241999500. Starting simulation...
+info: Entering event queue @ 2556438954000. Starting simulation...
switching cpus
-info: Entering event queue @ 2556242000500. Starting simulation...
+info: Entering event queue @ 2556438961500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2557242000500. Starting simulation...
+info: Entering event queue @ 2557438961500. Starting simulation...
switching cpus
-info: Entering event queue @ 2557242001500. Starting simulation...
+info: Entering event queue @ 2557438969000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2558242001500. Starting simulation...
+info: Entering event queue @ 2558438969000. Starting simulation...
switching cpus
-info: Entering event queue @ 2558242077000. Starting simulation...
+info: Entering event queue @ 2558438976500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2559242077000. Starting simulation...
+info: Entering event queue @ 2559438976500. Starting simulation...
switching cpus
-info: Entering event queue @ 2559242141000. Starting simulation...
+info: Entering event queue @ 2559439045000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2560242141000. Starting simulation...
+info: Entering event queue @ 2560439045000. Starting simulation...
switching cpus
-info: Entering event queue @ 2560242242000. Starting simulation...
+info: Entering event queue @ 2560439111000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2561242242000. Starting simulation...
+info: Entering event queue @ 2561439111000. Starting simulation...
switching cpus
-info: Entering event queue @ 2561242255000. Starting simulation...
+info: Entering event queue @ 2561439229000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2562242255000. Starting simulation...
+info: Entering event queue @ 2562439229000. Starting simulation...
switching cpus
-info: Entering event queue @ 2562242375000. Starting simulation...
+info: Entering event queue @ 2562439304000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2563242375000. Starting simulation...
+info: Entering event queue @ 2563439304000. Starting simulation...
switching cpus
-info: Entering event queue @ 2563242389000. Starting simulation...
+info: Entering event queue @ 2563439451000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2564242389000. Starting simulation...
+info: Entering event queue @ 2564439451000. Starting simulation...
switching cpus
-info: Entering event queue @ 2564242391000. Starting simulation...
+info: Entering event queue @ 2564439484000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2565242391000. Starting simulation...
+info: Entering event queue @ 2565439484000. Starting simulation...
switching cpus
-info: Entering event queue @ 2565242463000. Starting simulation...
+info: Entering event queue @ 2565439632000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2566242463000. Starting simulation...
+info: Entering event queue @ 2566439632000. Starting simulation...
switching cpus
-info: Entering event queue @ 2566242542000. Starting simulation...
+info: Entering event queue @ 2566439771000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2567242542000. Starting simulation...
+info: Entering event queue @ 2567439771000. Starting simulation...
switching cpus
-info: Entering event queue @ 2567242688000. Starting simulation...
+info: Entering event queue @ 2567439778500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2568242688000. Starting simulation...
+info: Entering event queue @ 2568439778500. Starting simulation...
switching cpus
-info: Entering event queue @ 2568242730000. Starting simulation...
+info: Entering event queue @ 2568439829000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2569242730000. Starting simulation...
+info: Entering event queue @ 2569439829000. Starting simulation...
switching cpus
-info: Entering event queue @ 2569242838000. Starting simulation...
+info: Entering event queue @ 2569439894000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2570242838000. Starting simulation...
+info: Entering event queue @ 2570439894000. Starting simulation...
switching cpus
-info: Entering event queue @ 2570242940000. Starting simulation...
+info: Entering event queue @ 2570439901500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2571242940000. Starting simulation...
+info: Entering event queue @ 2571439901500. Starting simulation...
switching cpus
-info: Entering event queue @ 2571242946000. Starting simulation...
+info: Entering event queue @ 2571440025000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2572242946000. Starting simulation...
+info: Entering event queue @ 2572440025000. Starting simulation...
switching cpus
-info: Entering event queue @ 2572243030000. Starting simulation...
+info: Entering event queue @ 2572440157000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2573243030000. Starting simulation...
+info: Entering event queue @ 2573440157000. Starting simulation...
switching cpus
-info: Entering event queue @ 2573243031000. Starting simulation...
+info: Entering event queue @ 2573440165000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2574243031000. Starting simulation...
+info: Entering event queue @ 2574440165000. Starting simulation...
switching cpus
-info: Entering event queue @ 2574243077000. Starting simulation...
+info: Entering event queue @ 2574440172500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2575243077000. Starting simulation...
+info: Entering event queue @ 2575440172500. Starting simulation...
switching cpus
-info: Entering event queue @ 2575243233000. Starting simulation...
+info: Entering event queue @ 2575440283000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2576243233000. Starting simulation...
+info: Entering event queue @ 2576440283000. Starting simulation...
switching cpus
-info: Entering event queue @ 2576243261000. Starting simulation...
+info: Entering event queue @ 2576440290500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2577243261000. Starting simulation...
+info: Entering event queue @ 2577440290500. Starting simulation...
switching cpus
-info: Entering event queue @ 2577243262000. Starting simulation...
+info: Entering event queue @ 2577440355000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2578243262000. Starting simulation...
+info: Entering event queue @ 2578440355000. Starting simulation...
switching cpus
-info: Entering event queue @ 2578243340000. Starting simulation...
+info: Entering event queue @ 2578440362500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2579243340000. Starting simulation...
+info: Entering event queue @ 2579440362500. Starting simulation...
switching cpus
-info: Entering event queue @ 2579243341000. Starting simulation...
+info: Entering event queue @ 2579440365000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2580243341000. Starting simulation...
+info: Entering event queue @ 2580440365000. Starting simulation...
switching cpus
-info: Entering event queue @ 2580243342000. Starting simulation...
+info: Entering event queue @ 2580440372500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2581243342000. Starting simulation...
+info: Entering event queue @ 2581440372500. Starting simulation...
switching cpus
-info: Entering event queue @ 2581243343000. Starting simulation...
+info: Entering event queue @ 2581440380000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2582243343000. Starting simulation...
+info: Entering event queue @ 2582440380000. Starting simulation...
+info: Entering event queue @ 2582440388500. Starting simulation...
switching cpus
-info: Entering event queue @ 2582243344000. Starting simulation...
+info: Entering event queue @ 2582440391000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2583243344000. Starting simulation...
-info: Entering event queue @ 2583243355000. Starting simulation...
+info: Entering event queue @ 2583440391000. Starting simulation...
+info: Entering event queue @ 2583440399500. Starting simulation...
switching cpus
-info: Entering event queue @ 2583243358500. Starting simulation...
+info: Entering event queue @ 2583440403000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2584243358500. Starting simulation...
+info: Entering event queue @ 2584440403000. Starting simulation...
switching cpus
-info: Entering event queue @ 2584243360500. Starting simulation...
+info: Entering event queue @ 2584440412000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2585243360500. Starting simulation...
+info: Entering event queue @ 2585440412000. Starting simulation...
switching cpus
-info: Entering event queue @ 2585243362500. Starting simulation...
+info: Entering event queue @ 2585440419500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2586243362500. Starting simulation...
-info: Entering event queue @ 2586996937000. Starting simulation...
+info: Entering event queue @ 2586440419500. Starting simulation...
+info: Entering event queue @ 2587181122000. Starting simulation...
switching cpus
-info: Entering event queue @ 2586996939000. Starting simulation...
+info: Entering event queue @ 2587181124000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2587996939000. Starting simulation...
+info: Entering event queue @ 2588181124000. Starting simulation...
switching cpus
-info: Entering event queue @ 2587996940000. Starting simulation...
+info: Entering event queue @ 2588181131500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2588996940000. Starting simulation...
+info: Entering event queue @ 2589181131500. Starting simulation...
switching cpus
-info: Entering event queue @ 2588996941000. Starting simulation...
+info: Entering event queue @ 2589181133000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2589996941000. Starting simulation...
+info: Entering event queue @ 2590181133000. Starting simulation...
switching cpus
-info: Entering event queue @ 2589996942000. Starting simulation...
+info: Entering event queue @ 2590181140500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2590996942000. Starting simulation...
+info: Entering event queue @ 2591181140500. Starting simulation...
switching cpus
-info: Entering event queue @ 2590996944000. Starting simulation...
+info: Entering event queue @ 2591181172000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2591996944000. Starting simulation...
+info: Entering event queue @ 2592181172000. Starting simulation...
switching cpus
-info: Entering event queue @ 2591996945000. Starting simulation...
+info: Entering event queue @ 2592181179500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2592996945000. Starting simulation...
+info: Entering event queue @ 2593181179500. Starting simulation...
switching cpus
-info: Entering event queue @ 2592996946000. Starting simulation...
+info: Entering event queue @ 2593181187000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2593996946000. Starting simulation...
+info: Entering event queue @ 2594181187000. Starting simulation...
switching cpus
-info: Entering event queue @ 2593996952500. Starting simulation...
+info: Entering event queue @ 2594181194500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2594996952500. Starting simulation...
+info: Entering event queue @ 2595181194500. Starting simulation...
switching cpus
-info: Entering event queue @ 2594996953500. Starting simulation...
+info: Entering event queue @ 2595181202000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2595996953500. Starting simulation...
+info: Entering event queue @ 2596181202000. Starting simulation...
switching cpus
-info: Entering event queue @ 2595996958500. Starting simulation...
+info: Entering event queue @ 2596181209500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2596996958500. Starting simulation...
+info: Entering event queue @ 2597181209500. Starting simulation...
switching cpus
-info: Entering event queue @ 2596996959500. Starting simulation...
+info: Entering event queue @ 2597181217000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2597996959500. Starting simulation...
+info: Entering event queue @ 2598181217000. Starting simulation...
switching cpus
-info: Entering event queue @ 2597996960500. Starting simulation...
+info: Entering event queue @ 2598181222000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2598996960500. Starting simulation...
+info: Entering event queue @ 2599181222000. Starting simulation...
switching cpus
-info: Entering event queue @ 2598996961500. Starting simulation...
+info: Entering event queue @ 2599181229500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2599996961500. Starting simulation...
+info: Entering event queue @ 2600181229500. Starting simulation...
switching cpus
-info: Entering event queue @ 2599996963500. Starting simulation...
+info: Entering event queue @ 2600181237000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2600996963500. Starting simulation...
+info: Entering event queue @ 2601181237000. Starting simulation...
+info: Entering event queue @ 2601181244500. Starting simulation...
switching cpus
-info: Entering event queue @ 2600996975000. Starting simulation...
+info: Entering event queue @ 2601181247500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2601996975000. Starting simulation...
+info: Entering event queue @ 2602181247500. Starting simulation...
switching cpus
-info: Entering event queue @ 2601996976000. Starting simulation...
+info: Entering event queue @ 2602181255000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2602996976000. Starting simulation...
+info: Entering event queue @ 2603181255000. Starting simulation...
+info: Entering event queue @ 2603181266500. Starting simulation...
switching cpus
-info: Entering event queue @ 2602997129000. Starting simulation...
+info: Entering event queue @ 2603181269000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2603997129000. Starting simulation...
+info: Entering event queue @ 2604181269000. Starting simulation...
switching cpus
-info: Entering event queue @ 2603997243000. Starting simulation...
+info: Entering event queue @ 2604181375000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2604997243000. Starting simulation...
+info: Entering event queue @ 2605181375000. Starting simulation...
switching cpus
-info: Entering event queue @ 2604997244500. Starting simulation...
+info: Entering event queue @ 2605181382500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2605997244500. Starting simulation...
+info: Entering event queue @ 2606181382500. Starting simulation...
switching cpus
-info: Entering event queue @ 2605997245500. Starting simulation...
+info: Entering event queue @ 2606181390000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2606997245500. Starting simulation...
+info: Entering event queue @ 2607181390000. Starting simulation...
switching cpus
-info: Entering event queue @ 2606997246500. Starting simulation...
+info: Entering event queue @ 2607181397500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2607997246500. Starting simulation...
-info: Entering event queue @ 2607997257000. Starting simulation...
+info: Entering event queue @ 2608181397500. Starting simulation...
switching cpus
-info: Entering event queue @ 2607997260500. Starting simulation...
+info: Entering event queue @ 2608181405000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2608997260500. Starting simulation...
+info: Entering event queue @ 2609181405000. Starting simulation...
switching cpus
-info: Entering event queue @ 2608997261500. Starting simulation...
+info: Entering event queue @ 2609181412500. Starting simulation...
---------- Begin Simulation Statistics ----------
-sim_seconds 2.608779 # Number of seconds simulated
-sim_ticks 2608778789000 # Number of ticks simulated
-final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.610012 # Number of seconds simulated
+sim_ticks 2610011893000 # Number of ticks simulated
+final_tick 2610011893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 616577 # Simulator instruction rate (inst/s)
-host_op_rate 784589 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26716567066 # Simulator tick rate (ticks/s)
-host_mem_usage 403640 # Number of bytes of host memory used
-host_seconds 97.65 # Real time elapsed on the host
-sim_insts 60206536 # Number of instructions simulated
-sim_ops 76612339 # Number of ops (including micro ops) simulated
+host_inst_rate 167893 # Simulator instruction rate (inst/s)
+host_op_rate 213643 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7278548305 # Simulator tick rate (ticks/s)
+host_mem_usage 438276 # Number of bytes of host memory used
+host_seconds 358.59 # Real time elapsed on the host
+sim_insts 60204721 # Number of instructions simulated
+sim_ops 76610045 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4486348 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4557348 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1520260 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1495880 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 356960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4558796 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 347904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4486256 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132433500 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 356960 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 347904 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory
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system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 70132 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 71232 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 380065 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 373970 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.num_reads::cpu0.data 71264 # Number of read requests responded to by this memory
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+system.physmem.num_writes::cpu1.data 376483 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47004917 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1719712 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1746928 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 582748 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 573402 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_read::cpu0.data 1746657 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::cpu0.inst 136766 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2302460 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2320330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494012 # Total number of read requests seen
-system.physmem.writeReqs 811397 # Total number of write requests seen
-system.physmem.cpureqs 213789 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991616768 # Total number of bytes read from memory
-system.physmem.bytesWritten 51929408 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132432464 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6687308 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 974838 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 967895 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967761 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 968555 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 968388 # Track reads on a per bank basis
+system.physmem.bw_total::cpu0.inst 136766 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 53303362 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494031 # Total number of read requests seen
+system.physmem.writeReqs 811452 # Total number of write requests seen
+system.physmem.cpureqs 213827 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991617984 # Total number of bytes read from memory
+system.physmem.bytesWritten 51932928 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132433500 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 27 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4514 # Reqs where no action is needed
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system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::7 968241 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50747 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50350 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50200 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50702 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50721 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51041 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50585 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2608774377500 # Total gap between requests
+system.physmem.totGap 2610007485000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 6676 # Categorize read packet sizes
+system.physmem.readPktSize::2 6679 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 151912 # Categorize read packet sizes
+system.physmem.readPktSize::6 151928 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 754035 # Categorize write packet sizes
+system.physmem.writePktSize::2 754067 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 57362 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1116374 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 57385 # Categorize write packet sizes
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
-system.physmem.totQLat 338360116500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 433225996500 # Sum of mem lat for all requests
-system.physmem.totBusLat 77469930000 # Total cycles spent in databus access
-system.physmem.totBankLat 17395950000 # Total cycles spent in bank access
-system.physmem.avgQLat 21838.16 # Average queueing delay per request
-system.physmem.avgBankLat 1122.75 # Average bank access latency per request
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+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.totQLat 338127152500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 432998718750 # Sum of mem lat for all requests
+system.physmem.totBusLat 77470020000 # Total cycles spent in databus access
+system.physmem.totBankLat 17401546250 # Total cycles spent in bank access
+system.physmem.avgQLat 21823.10 # Average queueing delay per request
+system.physmem.avgBankLat 1123.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27960.91 # Average memory access latency
-system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 27946.21 # Average memory access latency
+system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.13 # Data bus utilization in percentage
+system.physmem.busUtil 3.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 1.24 # Average write queue length over time
-system.physmem.readRowHits 15419485 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793971 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 1.25 # Average write queue length over time
+system.physmem.readRowHits 15419474 # Number of row buffer hits during reads
+system.physmem.writeRowHits 794097 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
-system.physmem.avgGap 159994.42 # Average gap between requests
+system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes
+system.physmem.avgGap 160069.31 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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-system.l2c.overall_mshr_uncacheable_latency::total 176071976481 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028449 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023237 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.016208 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992171 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989946 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531750 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542988 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.537407 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.101701 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88156392171 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87704881505 # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027541 # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990623 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.991059 # mshr miss rate for UpgradeReq accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.data 0.226238 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39501.680210 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43350.723311 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40931.064034 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.988490 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.312086 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.875094 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33558.476402 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 33072.702655 # average ReadExReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42647.842798 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7507395 # DTB read hits
-system.cpu0.dtb.read_misses 6880 # DTB read misses
-system.cpu0.dtb.write_hits 5552217 # DTB write hits
-system.cpu0.dtb.write_misses 1843 # DTB write misses
-system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
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+system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7514275 # DTB read accesses
-system.cpu0.dtb.write_accesses 5554060 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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-system.cpu0.dtb.accesses 13068335 # DTB accesses
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-system.cpu0.itb.inst_misses 3610 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
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-system.cpu0.itb.hits 30766787 # DTB hits
-system.cpu0.itb.misses 3610 # DTB misses
-system.cpu0.itb.accesses 30770397 # DTB accesses
-system.cpu0.numCycles 2552895768 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 30144155 # Number of instructions committed
-system.cpu0.committedOps 38293148 # Number of ops (including micro ops) committed
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-system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses
-system.cpu0.num_func_calls 1041305 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4017298 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 34424496 # number of integer instructions
-system.cpu0.num_fp_insts 5276 # number of float instructions
-system.cpu0.num_int_register_reads 197342644 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 37147872 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13659420 # number of memory refs
-system.cpu0.num_load_insts 7847088 # Number of load instructions
-system.cpu0.num_store_insts 5812332 # Number of store instructions
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-system.cpu0.num_busy_cycles -933868699.544441 # Number of busy cycles
-system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles
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+system.cpu0.num_fp_register_writes 1352 # number of times the floating registers were written
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+system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles
+system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83016 # number of quiesce instructions executed
-system.cpu0.icache.replacements 856082 # number of replacements
-system.cpu0.icache.tagsinuse 510.977353 # Cycle average of tags in use
-system.cpu0.icache.total_refs 60644038 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 354.101290 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 156.876063 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.691604 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.306399 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998003 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 30350406 # number of ReadReq hits
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-system.cpu0.icache.demand_misses::cpu0.inst 416381 # number of demand (read+write) misses
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system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100989012000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806840500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795852500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027678 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026720 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024606 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024406 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654781500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100140166000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794947500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027810 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024277 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048849 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043678 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12265.219794 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12158.017994 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.684919 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29620.617861 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30547.377682 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30087.271116 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.156919 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11356.982952 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.922470 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12262.108163 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.325907 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.573030 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.614938 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29881.588719 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.087245 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7490951 # DTB read hits
-system.cpu1.dtb.read_misses 7083 # DTB read misses
-system.cpu1.dtb.write_hits 5680260 # DTB write hits
-system.cpu1.dtb.write_misses 1778 # DTB write misses
-system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 7594464 # DTB read hits
+system.cpu1.dtb.read_misses 6935 # DTB read misses
+system.cpu1.dtb.write_hits 5731015 # DTB write hits
+system.cpu1.dtb.write_misses 1760 # DTB write misses
+system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6452 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7498034 # DTB read accesses
-system.cpu1.dtb.write_accesses 5682038 # DTB write accesses
+system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 7601399 # DTB read accesses
+system.cpu1.dtb.write_accesses 5732775 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13171211 # DTB hits
-system.cpu1.dtb.misses 8861 # DTB misses
-system.cpu1.dtb.accesses 13180072 # DTB accesses
-system.cpu1.itb.inst_hits 30733845 # ITB inst hits
-system.cpu1.itb.inst_misses 3661 # ITB inst misses
+system.cpu1.dtb.hits 13325479 # DTB hits
+system.cpu1.dtb.misses 8695 # DTB misses
+system.cpu1.dtb.accesses 13334174 # DTB accesses
+system.cpu1.itb.inst_hits 31195731 # ITB inst hits
+system.cpu1.itb.inst_misses 3619 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1275 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2756 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2687 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 30737506 # ITB inst accesses
-system.cpu1.itb.hits 30733845 # DTB hits
-system.cpu1.itb.misses 3661 # DTB misses
-system.cpu1.itb.accesses 30737506 # DTB accesses
-system.cpu1.numCycles 2664661810 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 31199350 # ITB inst accesses
+system.cpu1.itb.hits 31195731 # DTB hits
+system.cpu1.itb.misses 3619 # DTB misses
+system.cpu1.itb.accesses 31199350 # DTB accesses
+system.cpu1.numCycles 2551680783 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30062381 # Number of instructions committed
-system.cpu1.committedOps 38319191 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 34454554 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses
-system.cpu1.num_func_calls 1098878 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3931539 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 34454554 # number of integer instructions
-system.cpu1.num_fp_insts 4993 # number of float instructions
-system.cpu1.num_int_register_reads 197476132 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 37039734 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13739046 # number of memory refs
-system.cpu1.num_load_insts 7815505 # Number of load instructions
-system.cpu1.num_store_insts 5923541 # Number of store instructions
-system.cpu1.num_idle_cycles 1359990951.127739 # Number of idle cycles
-system.cpu1.num_busy_cycles 1304670858.872261 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles
+system.cpu1.committedInsts 30572056 # Number of instructions committed
+system.cpu1.committedOps 38927187 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 34988620 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses
+system.cpu1.num_func_calls 1115365 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 34988620 # number of integer instructions
+system.cpu1.num_fp_insts 5077 # number of float instructions
+system.cpu1.num_int_register_reads 200559310 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 37663253 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written
+system.cpu1.num_mem_refs 13910244 # number of memory refs
+system.cpu1.num_load_insts 7929876 # Number of load instructions
+system.cpu1.num_store_insts 5980368 # Number of store instructions
+system.cpu1.num_idle_cycles 10585260111.377636 # Number of idle cycles
+system.cpu1.num_busy_cycles -8033579328.377636 # Number of busy cycles
+system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.replacements 0 # number of replacements
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1196198690564 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1196198690564 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947260006 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1195947260006 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
+Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:19:51
-gem5 started Mar 4 2013 00:22:16
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 27 2013 00:32:51
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5132857897000 because m5_exit instruction encountered
+Exiting @ tick 5132865528000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.136865 # Number of seconds simulated
-sim_ticks 5136864508000 # Number of ticks simulated
-final_tick 5136864508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.132866 # Number of seconds simulated
+sim_ticks 5132865528000 # Number of ticks simulated
+final_tick 5132865528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 157360 # Simulator instruction rate (inst/s)
-host_op_rate 311060 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1981722494 # Simulator tick rate (ticks/s)
-host_mem_usage 783288 # Number of bytes of host memory used
-host_seconds 2592.12 # Real time elapsed on the host
-sim_insts 407895398 # Number of instructions simulated
-sim_ops 806304609 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2499136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory
+host_inst_rate 61482 # Simulator instruction rate (inst/s)
+host_op_rate 121532 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 773550742 # Simulator tick rate (ticks/s)
+host_mem_usage 771808 # Number of bytes of host memory used
+host_seconds 6635.46 # Real time elapsed on the host
+sim_insts 407963797 # Number of instructions simulated
+sim_ops 806422961 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2435200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1076928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10801024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14380480 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1076928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1076928 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9561920 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9561920 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 39049 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1080768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10867584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14387264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1080768 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1080768 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9583040 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9583040 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38050 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16827 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168766 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224695 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149405 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149405 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 486510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16887 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169806 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224801 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149735 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149735 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 474433 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 209647 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2102649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2799466 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 209647 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 209647 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1861431 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1861431 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1861431 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 486510 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 210558 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2117255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2802969 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 210558 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 1866996 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 209647 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2102649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4660898 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 224695 # Total number of read requests seen
-system.physmem.writeReqs 149405 # Total number of write requests seen
-system.physmem.cpureqs 378068 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14380480 # Total number of bytes read from memory
-system.physmem.bytesWritten 9561920 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14380480 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9561920 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 102 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3959 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14159 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13042 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::3 16282 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13746 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13201 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13511 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16248 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::15 15933 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9055 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 8495 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8476 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 11557 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8626 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8868 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 11671 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8971 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8652 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 8710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 11130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8376 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8654 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 210558 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 4669965 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 224801 # Total number of read requests seen
+system.physmem.writeReqs 149735 # Total number of write requests seen
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+system.physmem.bytesRead 14387264 # Total number of bytes read from memory
+system.physmem.bytesWritten 9583040 # Total number of bytes written to memory
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+system.physmem.bytesConsumedWr 9583040 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
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+system.physmem.perBankWrReqs::14 8591 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 11146 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5136864456000 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5132865474500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 224695 # Categorize read packet sizes
+system.physmem.readPktSize::6 224801 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 149405 # Categorize write packet sizes
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system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
-system.physmem.totQLat 4766626250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9279378750 # Sum of mem lat for all requests
-system.physmem.totBusLat 1122965000 # Total cycles spent in databus access
-system.physmem.totBankLat 3389787500 # Total cycles spent in bank access
-system.physmem.avgQLat 21223.40 # Average queueing delay per request
-system.physmem.avgBankLat 15093.02 # Average bank access latency per request
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+system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
+system.physmem.totQLat 4748150250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9279735250 # Sum of mem lat for all requests
+system.physmem.totBusLat 1123565000 # Total cycles spent in databus access
+system.physmem.totBankLat 3408020000 # Total cycles spent in bank access
+system.physmem.avgQLat 21129.84 # Average queueing delay per request
+system.physmem.avgBankLat 15166.10 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41316.42 # Average memory access latency
+system.physmem.avgMemAccLat 41295.94 # Average memory access latency
system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
+system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 11.02 # Average write queue length over time
-system.physmem.readRowHits 193644 # Number of row buffer hits during reads
-system.physmem.writeRowHits 105706 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 70.75 # Row buffer hit rate for writes
-system.physmem.avgGap 13731260.24 # Average gap between requests
-system.iocache.replacements 47574 # number of replacements
-system.iocache.tagsinuse 0.116323 # Cycle average of tags in use
+system.physmem.avgWrQLen 10.74 # Average write queue length over time
+system.physmem.readRowHits 193533 # Number of row buffer hits during reads
+system.physmem.writeRowHits 105971 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.12 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes
+system.physmem.avgGap 13704598.42 # Average gap between requests
+system.iocache.replacements 47575 # number of replacements
+system.iocache.tagsinuse 0.104035 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.116323 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
+system.iocache.warmup_cycle 4991882227000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.104035 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.006502 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.006502 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses
-system.iocache.overall_misses::total 47629 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144901871 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 144901871 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053199611 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10053199611 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10198101482 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10198101482 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10198101482 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10198101482 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
+system.iocache.overall_misses::total 47630 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142432660 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 142432660 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10000305290 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10000305290 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10142737950 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10142737950 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10142737950 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10142737950 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 159407.998900 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.786194 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 215179.786194 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 214115.381007 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 214115.381007 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 138033 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156519.406593 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 156519.406593 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214047.630351 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 214047.630351 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 212948.518791 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 212948.518791 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 135861 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 12531 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 12418 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.015322 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.940651 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97611900 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 97611900 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622412826 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7622412826 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7720024726 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7720024726 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95090941 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 95090941 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7569522729 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7569522729 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7664613670 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7664613670 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107383.828383 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163150.959461 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.959461 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104495.539560 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 104495.539560 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 86192778 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86192778 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1105969 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81285940 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 79207876 # Number of BTB hits
+system.cpu.branchPred.lookups 86256793 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86256793 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1113068 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 81525739 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79259204 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.443514 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 97.219853 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.numCycles 448117283 # number of cpu cycles simulated
+system.cpu.numCycles 448546895 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27407295 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 425903825 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86192778 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79207876 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163564309 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4697150 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125610 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63070837 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 35658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 51192 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9007924 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 482953 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2789 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257808166 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.261396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.418051 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27629675 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 426131263 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86256793 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79259204 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163637829 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4743979 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122519 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 63152705 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 51550 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9043434 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 488848 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3024 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 258223805 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.257780 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.417802 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94670555 36.72% 36.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1565511 0.61% 37.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71913522 27.89% 65.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 935622 0.36% 65.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1598852 0.62% 66.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2418850 0.94% 67.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1070189 0.42% 67.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1376236 0.53% 68.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82258829 31.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95012138 36.79% 36.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1565899 0.61% 37.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71926197 27.85% 65.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 935616 0.36% 65.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1604506 0.62% 66.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2433567 0.94% 67.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1079084 0.42% 67.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1383528 0.54% 68.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82283270 31.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257808166 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192344 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950429 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31124176 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60511588 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159357091 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3262426 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3552885 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 837683480 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 953 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3552885 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33860427 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37375460 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 11010468 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159557932 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12450994 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834052267 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19515 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5867687 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4751018 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 8643 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 995567635 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1810525606 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1810524958 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964273740 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31293888 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 458980 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 466833 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28792477 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17053482 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10121038 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1248085 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 996765 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 827936036 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1250306 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823005910 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 148163 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21984013 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33436004 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 197912 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257808166 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.192319 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.383919 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 258223805 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192303 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.950026 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31307096 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60630076 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159436775 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3257103 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3592755 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838113616 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 880 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3592755 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34040592 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37476959 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 11041434 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159631550 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12440515 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834468110 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19385 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5834152 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4771877 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 8971 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 996054249 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1811560635 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1811560099 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964410768 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31643474 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 457361 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 464527 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28752334 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17095902 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10132687 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1166436 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 902107 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828339786 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1247404 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823331592 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 149918 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22245950 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33811662 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 194652 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 258223805 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.188442 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.385103 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71353106 27.68% 27.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15525279 6.02% 33.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10289212 3.99% 37.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7463811 2.90% 40.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75897283 29.44% 70.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3839331 1.49% 71.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72507991 28.12% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 780183 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 151970 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71699549 27.77% 27.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15529974 6.01% 33.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10286408 3.98% 37.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7471868 2.89% 40.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75917572 29.40% 70.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3857166 1.49% 71.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72524361 28.09% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 784342 0.30% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 152565 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257808166 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 258223805 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 363662 34.07% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 553259 51.83% 85.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 150581 14.11% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 368681 34.39% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 552933 51.58% 85.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 150329 14.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 310965 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795485356 96.66% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 310005 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795767028 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17833485 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9376104 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17865255 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9389304 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823005910 # Type of FU issued
-system.cpu.iq.rate 1.836586 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1067502 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905165811 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851180208 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818537057 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 213 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 302 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 823762347 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1638684 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823331592 # Type of FU issued
+system.cpu.iq.rate 1.835553 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1071943 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1906239242 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851843261 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818849223 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 824093432 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1643495 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3078529 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 22784 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11411 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1710138 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3116410 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 23570 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11612 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1711798 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12218 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932508 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11844 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3552885 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26109999 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2115264 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829186342 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 321096 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17053482 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10121038 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 718511 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1615692 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 10262 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11411 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 648780 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 593291 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1242071 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821133450 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17423083 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1872459 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3592755 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26248050 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2110636 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829587190 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 321004 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17095902 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10132687 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 717072 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1612321 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11848 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11612 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 657039 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 595254 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1252293 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821445338 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17448687 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1886253 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26567058 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83190955 # Number of branches executed
-system.cpu.iew.exec_stores 9143975 # Number of stores executed
-system.cpu.iew.exec_rate 1.832407 # Inst execution rate
-system.cpu.iew.wb_sent 820672114 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818537115 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639752264 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045484939 # num instructions consuming a value
+system.cpu.iew.exec_refs 26607218 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83228491 # Number of branches executed
+system.cpu.iew.exec_stores 9158531 # Number of stores executed
+system.cpu.iew.exec_rate 1.831348 # Inst execution rate
+system.cpu.iew.wb_sent 820983226 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 818849277 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 639988645 # num instructions producing a value
+system.cpu.iew.wb_consumers 1045811759 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.826614 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.825560 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611954 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 22773726 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052392 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1110510 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254255281 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.171240 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.853929 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 23057499 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052750 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1117600 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 254631050 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.167025 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.854459 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82490050 32.44% 32.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11810591 4.65% 37.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3912535 1.54% 38.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74936309 29.47% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2436608 0.96% 69.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1481517 0.58% 69.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 940613 0.37% 70.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70914138 27.89% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5332920 2.10% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82837862 32.53% 32.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11822724 4.64% 37.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3905327 1.53% 38.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74951929 29.44% 68.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2438342 0.96% 69.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1480698 0.58% 69.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 927919 0.36% 70.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70920568 27.85% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5345681 2.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254255281 # Number of insts commited each cycle
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+system.cpu.itb_walker_cache.demand_miss_latency::total 118480500 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118480500 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 118480500 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36189 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 36189 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 35789 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 35789 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 35789 # number of overall (read+write) accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11176.470588 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11176.470588 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11176.470588 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36191 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 36191 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36191 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 36191 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298113 # miss rate for overall accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10981.601631 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10981.601631 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10981.601631 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10981.601631 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1917 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1917 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10506 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10506 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10506 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 10506 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10506 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10506 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96408000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96408000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96408000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96408000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96408000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.293570 # mshr miss rate for ReadReq accesses
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-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for demand accesses
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-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for overall accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.470588 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 2074 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 2074 # number of writebacks
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+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10789 # number of ReadReq MSHR misses
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+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10789 # number of overall MSHR misses
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+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96902500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96902500 # number of overall MSHR miss cycles
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+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for demand accesses
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+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for overall accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8981.601631 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 107366 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 12.959117 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 135123 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 107381 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.258351 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959117 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809945 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total 0.809945 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135139 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 135139 # number of ReadReq hits
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-system.cpu.dtb_walker_cache.demand_hits::total 135139 # number of demand (read+write) hits
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-system.cpu.dtb_walker_cache.overall_hits::total 135139 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108408 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 108408 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108408 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 108408 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108408 # number of overall misses
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-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1365628000 # number of demand (read+write) miss cycles
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-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1365628000 # number of overall miss cycles
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-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243547 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 243547 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243547 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 243547 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243547 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 243547 # number of overall (read+write) accesses
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-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.445121 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.445121 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.445121 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.445121 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.445121 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12597.114604 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12597.114604 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12597.114604 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12597.114604 # average overall miss latency
+system.cpu.dtb_walker_cache.replacements 112679 # number of replacements
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+system.cpu.dtb_walker_cache.total_refs 129664 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs 112694 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.150585 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5099752322000 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.888368 # Average occupied blocks per requestor
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+system.cpu.dtb_walker_cache.occ_percent::total 0.868023 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 129683 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 129683 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 129683 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 129683 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 129683 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 129683 # number of overall hits
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+system.cpu.dtb_walker_cache.ReadReq_misses::total 113702 # number of ReadReq misses
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+system.cpu.dtb_walker_cache.demand_misses::total 113702 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113702 # number of overall misses
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+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1421375500 # number of demand (read+write) miss cycles
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+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1421375500 # number of overall miss cycles
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+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243385 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 243385 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243385 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 243385 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243385 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 243385 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.467169 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.467169 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.467169 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.467169 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.467169 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.467169 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12500.883889 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12500.883889 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12500.883889 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12500.883889 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 35267 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 35267 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108408 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108408 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108408 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 108408 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108408 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 108408 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1148812000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1148812000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1148812000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.445121 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.445121 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.445121 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10597.114604 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57028.999762 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56326.692819 # average ReadReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:19:12
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 269661304500 because target called exit()
+Exiting @ tick 269668883500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.269672 # Number of seconds simulated
-sim_ticks 269671683500 # Number of ticks simulated
-final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.269669 # Number of seconds simulated
+sim_ticks 269668883500 # Number of ticks simulated
+final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 149368 # Simulator instruction rate (inst/s)
-host_op_rate 149368 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66926769 # Simulator tick rate (ticks/s)
-host_mem_usage 224496 # Number of bytes of host memory used
-host_seconds 4029.35 # Real time elapsed on the host
+host_inst_rate 49435 # Simulator instruction rate (inst/s)
+host_op_rate 49435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 22150100 # Simulator tick rate (ticks/s)
+host_mem_usage 271532 # Number of bytes of host memory used
+host_seconds 12174.61 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 269671631500 # Total gap between requests
+system.physmem.totGap 269668831500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1014 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 383646750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests
+system.physmem.totQLat 383236250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
-system.physmem.totBankLat 580690000 # Total cycles spent in bank access
-system.physmem.avgQLat 14598.43 # Average queueing delay per request
-system.physmem.avgBankLat 22096.27 # Average bank access latency per request
+system.physmem.totBankLat 580676250 # Total cycles spent in bank access
+system.physmem.avgQLat 14582.81 # Average queueing delay per request
+system.physmem.avgBankLat 22095.75 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41694.70 # Average memory access latency
+system.physmem.avgMemAccLat 41678.56 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 296 # Number of row buffer hits during writes
system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
-system.physmem.avgGap 9875187.91 # Average gap between requests
-system.cpu.branchPred.lookups 86405403 # Number of BP lookups
-system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
+system.physmem.avgGap 9875085.38 # Average gap between requests
+system.cpu.branchPred.lookups 86401588 # Number of BP lookups
+system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 114517881 # DTB read hits
+system.cpu.dtb.read_hits 114517866 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 114520512 # DTB read accesses
-system.cpu.dtb.write_hits 39453501 # DTB write hits
+system.cpu.dtb.read_accesses 114520497 # DTB read accesses
+system.cpu.dtb.write_hits 39453488 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 39455803 # DTB write accesses
-system.cpu.dtb.data_hits 153971382 # DTB hits
+system.cpu.dtb.write_accesses 39455790 # DTB write accesses
+system.cpu.dtb.data_hits 153971354 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 153976315 # DTB accesses
-system.cpu.itb.fetch_hits 24997849 # ITB hits
+system.cpu.dtb.data_accesses 153976287 # DTB accesses
+system.cpu.itb.fetch_hits 24966979 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 24997871 # ITB accesses
+system.cpu.itb.fetch_accesses 24967001 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 539343368 # number of cpu cycles simulated
+system.cpu.numCycles 539337768 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 154928367 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 154930401 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.579328 # Percentage of cycles cpu is active
+system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed.
+system.cpu.activity 90.579949 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
-system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
-system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use
-system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use
+system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits
-system.cpu.icache.overall_hits::total 24996815 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
-system.cpu.icache.overall_misses::total 1034 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits
+system.cpu.icache.overall_hits::total 24965946 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses
+system.cpu.icache.overall_misses::total 1033 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:43:44
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:39
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 133778696500 because target called exit()
+Exiting @ tick 133696809500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133774 # Number of seconds simulated
-sim_ticks 133773851500 # Number of ticks simulated
-final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133697 # Number of seconds simulated
+sim_ticks 133696809500 # Number of ticks simulated
+final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 262576 # Simulator instruction rate (inst/s)
-host_op_rate 262576 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62108832 # Simulator tick rate (ticks/s)
-host_mem_usage 226536 # Number of bytes of host memory used
-host_seconds 2153.86 # Real time elapsed on the host
+host_inst_rate 77616 # Simulator instruction rate (inst/s)
+host_op_rate 77616 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18348551 # Simulator tick rate (ticks/s)
+host_mem_usage 272684 # Number of bytes of host memory used
+host_seconds 7286.51 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 26524 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26526 # Total number of read requests seen
system.physmem.writeReqs 1048 # Total number of write requests seen
-system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1697536 # Total number of bytes read from memory
+system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1697664 # Total number of bytes read from memory
system.physmem.bytesWritten 67072 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 133773818000 # Total gap between requests
+system.physmem.totGap 133696776000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 26524 # Categorize read packet sizes
+system.physmem.readPktSize::6 26526 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1048 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 654284750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests
-system.physmem.totBusLat 132545000 # Total cycles spent in databus access
-system.physmem.totBankLat 559143750 # Total cycles spent in bank access
-system.physmem.avgQLat 24681.61 # Average queueing delay per request
-system.physmem.avgBankLat 21092.60 # Average bank access latency per request
+system.physmem.totQLat 652146750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests
+system.physmem.totBusLat 132555000 # Total cycles spent in databus access
+system.physmem.totBankLat 565881250 # Total cycles spent in bank access
+system.physmem.avgQLat 24599.10 # Average queueing delay per request
+system.physmem.avgBankLat 21345.15 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 50774.21 # Average memory access latency
-system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 50944.25 # Average memory access latency
+system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.10 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.24 # Average write queue length over time
-system.physmem.readRowHits 16966 # Number of row buffer hits during reads
-system.physmem.writeRowHits 271 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
-system.physmem.avgGap 4851799.58 # Average gap between requests
-system.cpu.branchPred.lookups 76502410 # Number of BP lookups
-system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits
+system.physmem.avgWrQLen 9.33 # Average write queue length over time
+system.physmem.readRowHits 16975 # Number of row buffer hits during reads
+system.physmem.writeRowHits 275 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes
+system.physmem.avgGap 4848653.66 # Average gap between requests
+system.cpu.branchPred.lookups 76441752 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 122629608 # DTB read hits
-system.cpu.dtb.read_misses 28810 # DTB read misses
+system.cpu.dtb.read_hits 122608255 # DTB read hits
+system.cpu.dtb.read_misses 28801 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 122658418 # DTB read accesses
-system.cpu.dtb.write_hits 40760367 # DTB write hits
-system.cpu.dtb.write_misses 25602 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 40785969 # DTB write accesses
-system.cpu.dtb.data_hits 163389975 # DTB hits
-system.cpu.dtb.data_misses 54412 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 163444387 # DTB accesses
-system.cpu.itb.fetch_hits 65529846 # ITB hits
+system.cpu.dtb.read_accesses 122637056 # DTB read accesses
+system.cpu.dtb.write_hits 40754827 # DTB write hits
+system.cpu.dtb.write_misses 25617 # DTB write misses
+system.cpu.dtb.write_acv 1 # DTB write access violations
+system.cpu.dtb.write_accesses 40780444 # DTB write accesses
+system.cpu.dtb.data_hits 163363082 # DTB hits
+system.cpu.dtb.data_misses 54418 # DTB misses
+system.cpu.dtb.data_acv 1 # DTB access violations
+system.cpu.dtb.data_accesses 163417500 # DTB accesses
+system.cpu.itb.fetch_hits 65484737 # ITB hits
system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 65529887 # ITB accesses
+system.cpu.itb.fetch_accesses 65484778 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 267547704 # number of cpu cycles simulated
+system.cpu.numCycles 267393620 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 63 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 42377854 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 14839100 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.822324 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued
-system.cpu.iq.rate 2.260254 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued
+system.cpu.iq.rate 2.261003 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 596495784 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 42874327 # number of nop insts executed
-system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed
-system.cpu.iew.exec_branches 66641793 # Number of branches executed
-system.cpu.iew.exec_stores 40804228 # Number of stores executed
-system.cpu.iew.exec_rate 2.241089 # Inst execution rate
-system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 415969736 # num instructions producing a value
-system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value
+system.cpu.iew.exec_nop 42838707 # number of nop insts executed
+system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed
+system.cpu.iew.exec_branches 66623579 # Number of branches executed
+system.cpu.iew.exec_stores 40798694 # Number of stores executed
+system.cpu.iew.exec_rate 2.241913 # Inst execution rate
+system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 415924305 # num instructions producing a value
+system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 258214194 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 892544623 # The number of ROB reads
-system.cpu.rob.rob_writes 1336970755 # The number of ROB writes
-system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 892250711 # The number of ROB reads
+system.cpu.rob.rob_writes 1336492363 # The number of ROB writes
+system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 845171662 # number of integer regfile reads
-system.cpu.int_regfile_writes 490625638 # number of integer regfile writes
-system.cpu.fp_regfile_reads 396 # number of floating regfile reads
+system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 844981893 # number of integer regfile reads
+system.cpu.int_regfile_writes 490535855 # number of integer regfile writes
+system.cpu.fp_regfile_reads 379 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 39 # number of replacements
-system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use
-system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use
+system.cpu.icache.total_refs 65483355 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 973 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits
-system.cpu.icache.overall_hits::total 65528462 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses
-system.cpu.icache.overall_misses::total 1383 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles
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+system.cpu.dcache.blocked_cycles::no_mshrs 306629 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 2099 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 18462 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.608656 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 190.818182 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks
-system.cpu.dcache.writebacks::total 444903 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.writebacks::writebacks 444926 # number of writebacks
+system.cpu.dcache.writebacks::total 444926 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 812044 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 812044 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547454 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1547454 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2359498 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2359498 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2359498 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2359498 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210442 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 210442 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254495 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 254495 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 464937 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 464937 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 464937 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 464937 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697776000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697776000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4104342498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4104342498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6802118498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6802118498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6802118498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6802118498 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:48:55
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 01:22:50
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 164543008000 because target called exit()
+Exiting @ tick 164562530500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.164572 # Number of seconds simulated
-sim_ticks 164572262000 # Number of ticks simulated
-final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.164563 # Number of seconds simulated
+sim_ticks 164562530500 # Number of ticks simulated
+final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 185108 # Simulator instruction rate (inst/s)
-host_op_rate 195599 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53440170 # Simulator tick rate (ticks/s)
-host_mem_usage 241944 # Number of bytes of host memory used
-host_seconds 3079.56 # Real time elapsed on the host
+host_inst_rate 62422 # Simulator instruction rate (inst/s)
+host_op_rate 65960 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18020016 # Simulator tick rate (ticks/s)
+host_mem_usage 288128 # Number of bytes of host memory used
+host_seconds 9132.21 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162432 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27336 # Total number of read requests seen
-system.physmem.writeReqs 2538 # Total number of write requests seen
-system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1749376 # Total number of bytes read from memory
-system.physmem.bytesWritten 162432 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162368 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27315 # Total number of read requests seen
+system.physmem.writeReqs 2537 # Total number of write requests seen
+system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1748096 # Total number of bytes read from memory
+system.physmem.bytesWritten 162368 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 164572246000 # Total gap between requests
+system.physmem.totGap 164562514500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27336 # Categorize read packet sizes
+system.physmem.readPktSize::6 27315 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 2538 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 2537 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 921339250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests
-system.physmem.totBusLat 136675000 # Total cycles spent in databus access
-system.physmem.totBankLat 614020000 # Total cycles spent in bank access
-system.physmem.avgQLat 33704.25 # Average queueing delay per request
-system.physmem.avgBankLat 22461.95 # Average bank access latency per request
-system.physmem.avgBusLat 4999.82 # Average bus latency per request
-system.physmem.avgMemAccLat 61166.02 # Average memory access latency
-system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
+system.physmem.totQLat 922192000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests
+system.physmem.totBusLat 136575000 # Total cycles spent in databus access
+system.physmem.totBankLat 613318750 # Total cycles spent in bank access
+system.physmem.avgQLat 33761.38 # Average queueing delay per request
+system.physmem.avgBankLat 22453.55 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 61214.93 # Average memory access latency
+system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.09 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 7.98 # Average write queue length over time
-system.physmem.readRowHits 16887 # Number of row buffer hits during reads
+system.physmem.avgWrQLen 5.61 # Average write queue length over time
+system.physmem.readRowHits 16878 # Number of row buffer hits during reads
system.physmem.writeRowHits 1046 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes
-system.physmem.avgGap 5508878.82 # Average gap between requests
-system.cpu.branchPred.lookups 85156760 # Number of BP lookups
-system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits
+system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes
+system.physmem.avgGap 5512612.71 # Average gap between requests
+system.cpu.branchPred.lookups 85150983 # Number of BP lookups
+system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 329144525 # number of cpu cycles simulated
+system.cpu.numCycles 329125062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued
-system.cpu.iq.rate 1.961470 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued
+system.cpu.iq.rate 1.961548 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3084 # number of nop insts executed
-system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed
-system.cpu.iew.exec_branches 74674061 # Number of branches executed
-system.cpu.iew.exec_stores 75873180 # Number of stores executed
-system.cpu.iew.exec_rate 1.949037 # Inst execution rate
-system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 418732313 # num instructions producing a value
-system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value
+system.cpu.iew.exec_nop 3079 # number of nop insts executed
+system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed
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+system.cpu.iew.exec_rate 1.949135 # Inst execution rate
+system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 418527294 # num instructions producing a value
+system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle
system.cpu.commit.committedInsts 570051636 # Number of instructions committed
system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 977066653 # The number of ROB reads
-system.cpu.rob.rob_writes 1370815087 # The number of ROB writes
-system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 977022777 # The number of ROB reads
+system.cpu.rob.rob_writes 1370762747 # The number of ROB writes
+system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570051585 # Number of Instructions Simulated
system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
-system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads
-system.cpu.int_regfile_writes 663049374 # number of integer regfile writes
+system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads
+system.cpu.int_regfile_writes 663034338 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads
+system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads
system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
-system.cpu.icache.replacements 66 # number of replacements
-system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use
-system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks.
+system.cpu.icache.replacements 49 # number of replacements
+system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use
+system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 67083102 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses
-system.cpu.icache.overall_misses::total 1141 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor
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+system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 1113 # number of overall misses
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+system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47746.712533 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 832 # number of ReadReq MSHR misses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency
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-system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 13 2013 11:20:14
-gem5 started Feb 13 2013 14:16:35
-gem5 executing on u200540-lin
+gem5 compiled Mar 26 2013 15:04:14
+gem5 started Mar 26 2013 23:39:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 387315507500 because target called exit()
+Exiting @ tick 387290918500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.387321 # Number of seconds simulated
-sim_ticks 387320726500 # Number of ticks simulated
-final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.387291 # Number of seconds simulated
+sim_ticks 387290918500 # Number of ticks simulated
+final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176162 # Simulator instruction rate (inst/s)
-host_op_rate 176717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48695201 # Simulator tick rate (ticks/s)
-host_mem_usage 235496 # Number of bytes of host memory used
-host_seconds 7953.98 # Real time elapsed on the host
+host_inst_rate 75176 # Simulator instruction rate (inst/s)
+host_op_rate 75413 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20778674 # Simulator tick rate (ticks/s)
+host_mem_usage 280588 # Number of bytes of host memory used
+host_seconds 18638.87 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27427 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27428 # Total number of read requests seen
system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1755264 # Total number of bytes read from memory
+system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1755328 # Total number of bytes read from memory
system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 387320698500 # Total gap between requests
+system.physmem.totGap 387290890500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27427 # Categorize read packet sizes
+system.physmem.readPktSize::6 27428 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 2533 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 712904000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests
-system.physmem.totBusLat 137135000 # Total cycles spent in databus access
-system.physmem.totBankLat 589187500 # Total cycles spent in bank access
-system.physmem.avgQLat 25992.78 # Average queueing delay per request
-system.physmem.avgBankLat 21482.03 # Average bank access latency per request
+system.physmem.totQLat 716281750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests
+system.physmem.totBusLat 137140000 # Total cycles spent in databus access
+system.physmem.totBankLat 588376250 # Total cycles spent in bank access
+system.physmem.avgQLat 26114.98 # Average queueing delay per request
+system.physmem.avgBankLat 21451.66 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52474.81 # Average memory access latency
+system.physmem.avgMemAccLat 52566.65 # Average memory access latency
system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 16.63 # Average write queue length over time
-system.physmem.readRowHits 17586 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1048 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes
-system.physmem.avgGap 12927927.19 # Average gap between requests
-system.cpu.branchPred.lookups 97754812 # Number of BP lookups
-system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits
+system.physmem.avgWrQLen 17.33 # Average write queue length over time
+system.physmem.readRowHits 17584 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1051 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes
+system.physmem.avgGap 12926500.80 # Average gap between requests
+system.cpu.branchPred.lookups 97760274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
-system.cpu.numCycles 774641454 # number of cpu cycles simulated
+system.cpu.numCycles 774581838 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups
+system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing
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+system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed
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+system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle
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-system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued
-system.cpu.iq.rate 1.883865 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued
+system.cpu.iq.rate 1.884093 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 93683374 # number of nop insts executed
-system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed
-system.cpu.iew.exec_branches 89035290 # Number of branches executed
-system.cpu.iew.exec_stores 170448337 # Number of stores executed
-system.cpu.iew.exec_rate 1.876999 # Inst execution rate
-system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1153395564 # num instructions producing a value
-system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value
+system.cpu.iew.exec_nop 93685275 # number of nop insts executed
+system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed
+system.cpu.iew.exec_branches 89035299 # Number of branches executed
+system.cpu.iew.exec_stores 170447970 # Number of stores executed
+system.cpu.iew.exec_rate 1.877225 # Inst execution rate
+system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1153472607 # num instructions producing a value
+system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2295766308 # The number of ROB reads
-system.cpu.rob.rob_writes 3234429823 # The number of ROB writes
-system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2295781723 # The number of ROB reads
+system.cpu.rob.rob_writes 3234577019 # The number of ROB writes
+system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
-system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads
-system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads
-system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes
-system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads
+system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads
+system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes
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+system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes
+system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
-system.cpu.icache.replacements 200 # number of replacements
-system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use
-system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks.
+system.cpu.icache.replacements 197 # number of replacements
+system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use
+system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 161931886 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses
-system.cpu.icache.overall_misses::total 1937 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43689.140504 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 43689.140504 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 43689.140504 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 43689.140504 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 62434000 # number of overall MSHR miss cycles
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+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 27 2013 00:17:33
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 607412415000 because target called exit()
+Exiting @ tick 607388314000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.607412 # Number of seconds simulated
-sim_ticks 607412415000 # Number of ticks simulated
-final_tick 607412415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.607388 # Number of seconds simulated
+sim_ticks 607388314000 # Number of ticks simulated
+final_tick 607388314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59004 # Simulator instruction rate (inst/s)
-host_op_rate 108719 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40726098 # Simulator tick rate (ticks/s)
-host_mem_usage 295644 # Number of bytes of host memory used
-host_seconds 14914.57 # Real time elapsed on the host
+host_inst_rate 39851 # Simulator instruction rate (inst/s)
+host_op_rate 73427 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27504625 # Simulator tick rate (ticks/s)
+host_mem_usage 294932 # Number of bytes of host memory used
+host_seconds 22083.13 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1693248 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162176 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26457 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 94934 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2787641 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2882575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 94934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 94934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 266995 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 266995 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 266995 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 94934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2787641 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3149570 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27360 # Total number of read requests seen
-system.physmem.writeReqs 2534 # Total number of write requests seen
+system.physmem.bytes_read::cpu.inst 57920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1751040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 57920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 57920 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 905 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27360 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 95359 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2787541 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2882900 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 95359 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 95359 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 266900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 266900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 266900 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 95359 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2787541 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3149800 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27361 # Total number of read requests seen
+system.physmem.writeReqs 2533 # Total number of write requests seen
system.physmem.cpureqs 29894 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1750912 # Total number of bytes read from memory
-system.physmem.bytesWritten 162176 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytesRead 1751040 # Total number of bytes read from memory
+system.physmem.bytesWritten 162112 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1751040 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1711 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1718 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1656 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1655 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1711 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1717 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1738 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1751 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 607412402000 # Total gap between requests
+system.physmem.totGap 607388300000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27360 # Categorize read packet sizes
+system.physmem.readPktSize::6 27361 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 2534 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 26889 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 2533 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 88987000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 893982000 # Sum of mem lat for all requests
-system.physmem.totBusLat 136800000 # Total cycles spent in databus access
-system.physmem.totBankLat 668195000 # Total cycles spent in bank access
-system.physmem.avgQLat 3252.45 # Average queueing delay per request
-system.physmem.avgBankLat 24422.33 # Average bank access latency per request
+system.physmem.totQLat 89920500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 894824250 # Sum of mem lat for all requests
+system.physmem.totBusLat 136805000 # Total cycles spent in databus access
+system.physmem.totBankLat 668098750 # Total cycles spent in bank access
+system.physmem.avgQLat 3286.45 # Average queueing delay per request
+system.physmem.avgBankLat 24417.92 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32674.78 # Average memory access latency
+system.physmem.avgMemAccLat 32704.37 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 13.09 # Average write queue length over time
-system.physmem.readRowHits 16427 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1022 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.33 # Row buffer hit rate for writes
-system.physmem.avgGap 20318873.42 # Average gap between requests
-system.cpu.branchPred.lookups 158382296 # Number of BP lookups
-system.cpu.branchPred.condPredicted 158382296 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 26387252 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 83381183 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 83179505 # Number of BTB hits
+system.physmem.avgWrQLen 12.62 # Average write queue length over time
+system.physmem.readRowHits 16432 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1027 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 60.06 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.54 # Row buffer hit rate for writes
+system.physmem.avgGap 20318067.17 # Average gap between requests
+system.cpu.branchPred.lookups 158363276 # Number of BP lookups
+system.cpu.branchPred.condPredicted 158363276 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 26388177 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 84556073 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 84327975 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.758125 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 99.730241 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1214824831 # number of cpu cycles simulated
+system.cpu.numCycles 1214776629 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 179163349 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1457867613 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 158382296 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 83179505 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 399005833 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 88132062 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 574704368 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 186835049 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10712979 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1214462855 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.059159 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.252870 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 179085869 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1458535582 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 158363276 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 84327975 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 399051382 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 88177914 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 574644515 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 188128638 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 12060508 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1214415274 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.059853 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.253551 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 822674810 67.74% 67.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 26926688 2.22% 69.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 13135389 1.08% 71.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20566511 1.69% 72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26637257 2.19% 74.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18247973 1.50% 76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31504454 2.59% 79.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 39098170 3.22% 82.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 215671603 17.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 822580385 67.73% 67.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26905566 2.22% 69.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 13181581 1.09% 71.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20540967 1.69% 72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26638083 2.19% 74.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18230799 1.50% 76.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31362370 2.58% 79.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 39059510 3.22% 82.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 215916013 17.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1214462855 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.130375 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.200064 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 288324734 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 497934423 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 274040429 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92574368 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 61588901 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2343698812 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 61588901 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 336957337 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 124218348 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2659 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 304046563 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 387649047 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2248109589 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 242721119 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 120169480 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2618670353 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5724257672 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5724251768 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5904 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1214415274 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.130364 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.200662 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 288243803 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 497890873 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 274138871 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92508603 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 61633124 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2344113948 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 61633124 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 336916939 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 124193279 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2662 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 304031533 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 387637737 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2248223321 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 352 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 242707605 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 120173474 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2618640021 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5724414358 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5724407502 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6856 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 731775093 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 91 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 731348064 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 531825278 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 219280996 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 342077982 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144753457 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1993869707 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 294 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1783892793 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 265772 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 371981386 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 760150327 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 245 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1214462855 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.468874 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.421634 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 731744761 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 86 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 731270344 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 531930252 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 219281722 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 342004102 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 144706308 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1994081706 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 268 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1783937479 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 271890 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 372188972 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 760599366 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 219 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1214415274 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.468968 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.421626 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 360357006 29.67% 29.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 364326915 30.00% 59.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234272776 19.29% 78.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 141367539 11.64% 90.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60718828 5.00% 95.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 39723200 3.27% 98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 11050512 0.91% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2045307 0.17% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 600772 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 360308657 29.67% 29.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 364274837 30.00% 59.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234367873 19.30% 78.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 141282709 11.63% 90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60755557 5.00% 95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 39735013 3.27% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 11052402 0.91% 99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2038744 0.17% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 599482 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1214462855 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1214415274 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 450048 15.52% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2249912 77.59% 93.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 199796 6.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 457362 15.66% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2260297 77.38% 93.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 203472 6.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 46812279 2.62% 2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1065698440 59.74% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 478836274 26.84% 89.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 192545800 10.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 46812177 2.62% 2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1065743062 59.74% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 478833230 26.84% 89.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 192549010 10.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1783892793 # Type of FU issued
-system.cpu.iq.rate 1.468436 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2899756 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4785413585 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2366027132 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1724688067 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 384 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1824 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1739980085 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 209981192 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1783937479 # Type of FU issued
+system.cpu.iq.rate 1.468531 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2921131 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001637 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4785482838 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2366447244 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1724674774 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 415 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2104 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1740046229 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 204 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 210002024 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 112783156 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 38868 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 181899 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 31094938 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 112888130 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39196 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 182689 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 31095664 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2165 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 66 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 61588901 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1215520 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 110006 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1993870001 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 63340037 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 531825278 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 219280996 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 53594 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2844 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 181899 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2045614 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 24471458 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 26517072 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1766151616 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 474571020 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 17741177 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 61633124 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1215598 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 109803 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1994081974 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 63261504 # Number of squashed instructions skipped by dispatch
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-system.cpu.iew.exec_stores 191719045 # Number of stores executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::1 415089887 36.00% 72.28% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::3 122167535 10.60% 90.42% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::8 32441929 2.81% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::5 25351733 2.20% 94.71% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 361976 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
-system.cpu.cpi 1.380443 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.380443 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.724405 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.724405 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 0.724434 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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-system.cpu.icache.total_refs 186833677 # Total number of references to valid blocks.
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-system.cpu.icache.occ_percent::total 0.397822 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_misses::total 1367 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1367 # number of demand (read+write) misses
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-system.cpu.icache.overall_miss_latency::cpu.inst 65166500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 65166500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 186835049 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 186835049 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 186835049 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 186835049 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47671.177762 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47671.177762 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47671.177762 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47671.177762 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 146 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 444 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 444 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_misses::total 923 # number of demand (read+write) MSHR misses
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-system.cpu.icache.demand_mshr_miss_latency::total 47626500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47626500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 47626500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51599.674973 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51599.674973 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51599.674973 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51599.674973 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51599.674973 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51940.193966 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51940.193966 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2556 # number of replacements
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 446028 # number of replacements
-system.cpu.dcache.tagsinuse 4092.714418 # Cycle average of tags in use
-system.cpu.dcache.total_refs 452315129 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 450124 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1004.867834 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 446101 # number of replacements
+system.cpu.dcache.tagsinuse 4092.714287 # Cycle average of tags in use
+system.cpu.dcache.total_refs 452328275 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 450197 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 1004.734094 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4092.714418 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 4092.714287 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 264375496 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 264375496 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187939628 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187939628 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 452315124 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 452315124 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 452315124 # number of overall hits
-system.cpu.dcache.overall_hits::total 452315124 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 211166 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 211166 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 246430 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 246430 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 457596 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 457596 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 457596 # number of overall misses
-system.cpu.dcache.overall_misses::total 457596 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3021463500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3021463500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4117356500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4117356500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7138820000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7138820000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7138820000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7138820000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 264586662 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 264586662 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::cpu.data 264388646 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 264388646 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 187939623 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 187939623 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 452328269 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 452328269 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 452328269 # number of overall hits
+system.cpu.dcache.overall_hits::total 452328269 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 211237 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 211237 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 246435 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 246435 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 457672 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 457672 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 457672 # number of overall misses
+system.cpu.dcache.overall_misses::total 457672 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022054000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3022054000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4117738500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4117738500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7139792500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7139792500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7139792500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7139792500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 264599883 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 264599883 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 452772720 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 452772720 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 452772720 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 452772720 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 452785941 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 452785941 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 452785941 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 452785941 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14308.475323 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14308.475323 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16708.016475 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16708.016475 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15600.704552 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15600.704552 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.461463 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.461463 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16709.227585 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16709.227585 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15600.238817 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15600.238817 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.473684 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.023256 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 428982 # number of writebacks
-system.cpu.dcache.writebacks::total 428982 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7377 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7377 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 87 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 87 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7464 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7464 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7464 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7464 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203789 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 203789 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246343 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 246343 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 450132 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 450132 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 450132 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 450132 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528052500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528052500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3623861000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3623861000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151913500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6151913500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151913500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6151913500 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 429059 # number of writebacks
+system.cpu.dcache.writebacks::total 429059 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7389 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7389 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 79 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 79 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7468 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7468 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7468 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7468 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203848 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 203848 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246356 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 246356 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 450204 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 450204 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 450204 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 450204 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529010500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529010500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3624235500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3624235500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6153246000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6153246000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6153246000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6153246000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.245131 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.245131 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14710.631112 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14710.631112 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12406.354244 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12406.354244 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14711.375002 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14711.375002 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:55:20
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 01:31:22
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26773408500 because target called exit()
+Exiting @ tick 26780899500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026786 # Number of seconds simulated
-sim_ticks 26785824500 # Number of ticks simulated
-final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026781 # Number of seconds simulated
+sim_ticks 26780899500 # Number of ticks simulated
+final_tick 26780899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 121944 # Simulator instruction rate (inst/s)
-host_op_rate 122819 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36056613 # Simulator tick rate (ticks/s)
-host_mem_usage 374016 # Number of bytes of host memory used
-host_seconds 742.88 # Real time elapsed on the host
+host_inst_rate 55932 # Simulator instruction rate (inst/s)
+host_op_rate 56334 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16535050 # Simulator tick rate (ticks/s)
+host_mem_usage 421208 # Number of bytes of host memory used
+host_seconds 1619.64 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
+system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15513 # Total number of read requests seen
+system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1680003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 35385219 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 37065223 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1680003 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1680003 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1680003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 35385219 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 37065223 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15510 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 992832 # Total number of bytes read from memory
+system.physmem.cpureqs 15513 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 992640 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 992640 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 998 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1010 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 999 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26785652500 # Total gap between requests
+system.physmem.totGap 26780729500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15513 # Categorize read packet sizes
+system.physmem.readPktSize::6 15510 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 10153 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 5074 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 55611750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests
-system.physmem.totBusLat 77565000 # Total cycles spent in databus access
-system.physmem.totBankLat 181830000 # Total cycles spent in bank access
-system.physmem.avgQLat 3584.85 # Average queueing delay per request
-system.physmem.avgBankLat 11721.14 # Average bank access latency per request
+system.physmem.totQLat 54693250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 313977000 # Sum of mem lat for all requests
+system.physmem.totBusLat 77550000 # Total cycles spent in databus access
+system.physmem.totBankLat 181733750 # Total cycles spent in bank access
+system.physmem.avgQLat 3526.32 # Average queueing delay per request
+system.physmem.avgBankLat 11717.20 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20305.99 # Average memory access latency
+system.physmem.avgMemAccLat 20243.52 # Average memory access latency
system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.29 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 14781 # Number of row buffer hits during reads
+system.physmem.readRowHits 14776 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1726658.45 # Average gap between requests
-system.cpu.branchPred.lookups 26682480 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits
+system.physmem.avgGap 1726675.02 # Average gap between requests
+system.cpu.branchPred.lookups 26686067 # Number of BP lookups
+system.cpu.branchPred.condPredicted 22003641 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 842721 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11370784 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11281397 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.213889 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 70454 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53571650 # number of cpu cycles simulated
+system.cpu.numCycles 53561800 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 14175164 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 127899633 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26686067 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11351851 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24037657 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4765030 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 11217249 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 13847383 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 331199 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53336140 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.414591 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.216158 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29336778 55.00% 55.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3388806 6.35% 61.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2028790 3.80% 65.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1556293 2.92% 68.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1665637 3.12% 71.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2919109 5.47% 76.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1511505 2.83% 79.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1091219 2.05% 81.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9838003 18.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 53336140 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.498229 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.387889 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16937190 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9066542 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22437695 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 997386 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3897327 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4443416 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8715 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 126080182 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42547 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3897327 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18717098 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3539811 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 156330 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21553550 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5472024 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 123163469 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 421860 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4589739 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1294 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 143620029 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 536487458 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 536482847 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4611 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.UndoneMaps 36205843 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12496499 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29481175 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5524207 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2105622 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1304065 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118177785 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 105170475 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 79267 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26750487 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65594281 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 53336140 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.971843 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.910853 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15308492 28.70% 28.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11622242 21.79% 50.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8283131 15.53% 66.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6774123 12.70% 78.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4939733 9.26% 87.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2964995 5.56% 93.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2471425 4.63% 98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 528847 0.99% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 443152 0.83% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53336140 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 45613 6.89% 6.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 340087 51.41% 58.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 275830 41.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74428958 70.77% 70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 145 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 185 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25611753 24.35% 95.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5118456 4.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued
-system.cpu.iq.rate 1.962814 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105170475 # Type of FU issued
+system.cpu.iq.rate 1.963535 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 661557 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 264417181 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 144941243 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102695992 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 733 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 321 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 105831667 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 444874 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6907209 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6633 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6354 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 779363 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 31305 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 3897327 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 927642 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 126590 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 118198971 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 309734 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29481175 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5524207 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents 66006 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6795 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6354 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 446949 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 445983 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 892932 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104193042 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25290857 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 977433 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12720 # number of nop insts executed
-system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21325145 # Number of branches executed
-system.cpu.iew.exec_stores 5059434 # Number of stores executed
-system.cpu.iew.exec_rate 1.944605 # Inst execution rate
-system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62233069 # num instructions producing a value
-system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value
+system.cpu.iew.exec_nop 12714 # number of nop insts executed
+system.cpu.iew.exec_refs 30352506 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21328586 # Number of branches executed
+system.cpu.iew.exec_stores 5061649 # Number of stores executed
+system.cpu.iew.exec_rate 1.945286 # Inst execution rate
+system.cpu.iew.wb_sent 102976105 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102696313 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62237913 # num instructions producing a value
+system.cpu.iew.wb_consumers 104299650 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.917342 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.596722 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 26949111 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 834092 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 49438813 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.845776 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.541803 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19950290 40.35% 40.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13144948 26.59% 66.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4163783 8.42% 75.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3432949 6.94% 82.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1533470 3.10% 85.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 746046 1.51% 86.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 934782 1.89% 88.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 251563 0.51% 89.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5280982 10.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 49438813 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5280982 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162355527 # The number of ROB reads
-system.cpu.rob.rob_writes 240299704 # The number of ROB writes
-system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 162354168 # The number of ROB reads
+system.cpu.rob.rob_writes 240321058 # The number of ROB writes
+system.cpu.timesIdled 43778 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 225660 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
-system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495535708 # number of integer regfile reads
-system.cpu.int_regfile_writes 120542575 # number of integer regfile writes
-system.cpu.fp_regfile_reads 173 # number of floating regfile reads
-system.cpu.fp_regfile_writes 431 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads
+system.cpu.cpi 0.591256 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.591256 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.691314 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.691314 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 495624515 # number of integer regfile reads
+system.cpu.int_regfile_writes 120561799 # number of integer regfile writes
+system.cpu.fp_regfile_reads 167 # number of floating regfile reads
+system.cpu.fp_regfile_writes 408 # number of floating regfile writes
+system.cpu.misc_regfile_reads 29097050 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use
-system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks.
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system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.046502 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.046502 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.046502 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.046502 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11821.626223 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11821.626223 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28246.112735 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28246.112735 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14192.176961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14192.176961 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 152397 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 23857 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387936 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks
-system.cpu.dcache.writebacks::total 942900 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 942899 # number of writebacks
+system.cpu.dcache.writebacks::total 942899 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270103 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 270103 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154489 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 154489 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 424592 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 424592 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 424592 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 424592 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904041 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 904041 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43560 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43560 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947601 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947601 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947601 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947601 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990058500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990058500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 983302939 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 983302939 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10973361439 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10973361439 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10973361439 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10973361439 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036493 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009200 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009200 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032113 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032113 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.448486 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.448486 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22573.529362 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22573.529362 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 27 2013 00:35:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 66030660000 because target called exit()
+Exiting @ tick 66015916000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.066031 # Number of seconds simulated
-sim_ticks 66030660000 # Number of ticks simulated
-final_tick 66030660000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.066016 # Number of seconds simulated
+sim_ticks 66015916000 # Number of ticks simulated
+final_tick 66015916000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55728 # Simulator instruction rate (inst/s)
-host_op_rate 98128 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23291229 # Simulator tick rate (ticks/s)
-host_mem_usage 430752 # Number of bytes of host memory used
-host_seconds 2835.00 # Real time elapsed on the host
+host_inst_rate 35889 # Simulator instruction rate (inst/s)
+host_op_rate 63194 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14996247 # Simulator tick rate (ticks/s)
+host_mem_usage 431068 # Number of bytes of host memory used
+host_seconds 4402.16 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 64768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1881920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1946688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64768 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 10176 # Number of bytes written to this memory
-system.physmem.bytes_written::total 10176 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1012 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30417 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 159 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 159 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 980878 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28500700 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29481577 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 980878 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 980878 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 154110 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 154110 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 154110 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 980878 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28500700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29635687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30419 # Total number of read requests seen
-system.physmem.writeReqs 159 # Total number of write requests seen
-system.physmem.cpureqs 30579 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1946688 # Total number of bytes read from memory
-system.physmem.bytesWritten 10176 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1946688 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 10176 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 38 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1882688 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory
+system.physmem.bytes_written::total 10816 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29417 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 169 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 982066 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28518698 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29500765 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 982066 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 982066 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 163839 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 163839 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 163839 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 982066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28518698 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29664604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30432 # Total number of read requests seen
+system.physmem.writeReqs 169 # Total number of write requests seen
+system.physmem.cpureqs 30602 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1947520 # Total number of bytes read from memory
+system.physmem.bytesWritten 10816 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1947520 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1880 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 1931 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1971 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1938 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1871 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1844 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1894 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 14 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 66030647000 # Total gap between requests
+system.physmem.totGap 66015903000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 30419 # Categorize read packet sizes
+system.physmem.readPktSize::6 30432 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 159 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 29848 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 96 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 169 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 29838 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 12950000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 610712500 # Sum of mem lat for all requests
-system.physmem.totBusLat 151905000 # Total cycles spent in databus access
-system.physmem.totBankLat 445857500 # Total cycles spent in bank access
-system.physmem.avgQLat 426.25 # Average queueing delay per request
-system.physmem.avgBankLat 14675.54 # Average bank access latency per request
+system.physmem.totQLat 14883000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 612849250 # Sum of mem lat for all requests
+system.physmem.totBusLat 151875000 # Total cycles spent in databus access
+system.physmem.totBankLat 446091250 # Total cycles spent in bank access
+system.physmem.avgQLat 489.98 # Average queueing delay per request
+system.physmem.avgBankLat 14686.13 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20101.79 # Average memory access latency
-system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 20176.11 # Average memory access latency
+system.physmem.avgRdBW 29.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 29.50 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.37 # Average write queue length over time
-system.physmem.readRowHits 29124 # Number of row buffer hits during reads
-system.physmem.writeRowHits 74 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.86 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 46.54 # Row buffer hit rate for writes
-system.physmem.avgGap 2159416.80 # Average gap between requests
-system.cpu.branchPred.lookups 34530822 # Number of BP lookups
-system.cpu.branchPred.condPredicted 34530822 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 911360 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 24729253 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 24630321 # Number of BTB hits
+system.physmem.avgWrQLen 12.99 # Average write queue length over time
+system.physmem.readRowHits 29112 # Number of row buffer hits during reads
+system.physmem.writeRowHits 92 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 54.44 # Row buffer hit rate for writes
+system.physmem.avgGap 2157311.95 # Average gap between requests
+system.cpu.branchPred.lookups 34543649 # Number of BP lookups
+system.cpu.branchPred.condPredicted 34543649 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 911313 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 24748799 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 24648647 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.599939 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 99.595326 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 132061321 # number of cpu cycles simulated
+system.cpu.numCycles 132031833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 26640465 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 185644154 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 34530822 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24630321 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 56512430 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6116130 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 43661882 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 26608466 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 185598145 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 34543649 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24648647 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 56505869 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6118180 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 43668483 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 168 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25987124 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 190736 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 131984046 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.483688 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.326165 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 25960165 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 191907 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 131953761 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.484443 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.326412 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 78029555 59.12% 59.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1995729 1.51% 60.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2956074 2.24% 62.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3928612 2.98% 65.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7800232 5.91% 71.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4757812 3.60% 75.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2739309 2.08% 77.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1526136 1.16% 78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 28250587 21.40% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 77999092 59.11% 59.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1996445 1.51% 60.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2954879 2.24% 62.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3924320 2.97% 65.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7795201 5.91% 71.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4757326 3.61% 75.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2733781 2.07% 77.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1559430 1.18% 78.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 28233287 21.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131984046 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.261476 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.405742 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37482972 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 35916557 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44772529 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8642915 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5169073 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 324582822 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 5169073 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43046448 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8564916 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9080 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 47588733 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27605796 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 320159922 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 237 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 45758 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25753634 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 322185741 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 849178580 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 849176902 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1678 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 131953761 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261631 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.405708 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37450717 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 35919295 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44755686 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8657316 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5170747 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 324590135 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 5170747 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 43008680 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8572089 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9131 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 47592423 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 27600691 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 320189266 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 52468 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 25750177 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 322200191 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 849206572 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 849204881 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1691 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 42972994 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 471 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 465 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62311011 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 102521831 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 35289955 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39590581 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5948018 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 315836203 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1692 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 302241523 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 114427 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 37009178 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 54193553 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1247 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131984046 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.289985 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.700189 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 42987444 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 470 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 62325140 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 102538299 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 35256894 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 39591249 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6019659 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 315840251 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1684 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 302185420 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 114738 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 37013163 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 54220323 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1239 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 131953761 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.290086 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.700741 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24578568 18.62% 18.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23258852 17.62% 36.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25861899 19.59% 55.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25827751 19.57% 75.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18939781 14.35% 89.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8317897 6.30% 96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4131388 3.13% 99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 904597 0.69% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 163313 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24578254 18.63% 18.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23242336 17.61% 36.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25887812 19.62% 55.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 25783281 19.54% 75.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18948095 14.36% 89.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8310182 6.30% 96.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4120126 3.12% 99.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 915829 0.69% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 167846 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131984046 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 131953761 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 38531 1.97% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1832245 93.51% 95.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 88531 4.52% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1827997 93.47% 95.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 89360 4.57% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 31281 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 171212053 56.65% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97762843 32.35% 89.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33235315 11.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 171162971 56.64% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97754962 32.35% 89.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33236179 11.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 302241523 # Type of FU issued
-system.cpu.iq.rate 2.288645 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1959307 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 738540324 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 352878782 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 299597425 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 502 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 804 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 304169320 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 54003142 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 302185420 # Type of FU issued
+system.cpu.iq.rate 2.288732 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1955715 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006472 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 738394566 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 352887317 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 299540345 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 488 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 781 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 304109629 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 54010503 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 11742446 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 27574 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33469 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3850203 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11758914 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26738 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33947 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3817142 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3240 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8519 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5169073 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1760712 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 159375 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 315837895 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 196193 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 102521831 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 35289955 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 5170747 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1767696 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 159609 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 315841935 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 195500 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 102538299 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 35256894 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3161 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 73375 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33469 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 522333 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 446338 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 968671 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 300624260 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 97295381 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1617263 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents 3164 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 73504 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33947 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 522441 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 446022 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 968463 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 300565656 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 97285754 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1619764 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 130311532 # number of memory reference insts executed
-system.cpu.iew.exec_branches 30892471 # Number of branches executed
-system.cpu.iew.exec_stores 33016151 # Number of stores executed
-system.cpu.iew.exec_rate 2.276399 # Inst execution rate
-system.cpu.iew.wb_sent 300027844 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 299597573 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 219555050 # num instructions producing a value
-system.cpu.iew.wb_consumers 298061824 # num instructions consuming a value
+system.cpu.iew.exec_refs 130302195 # number of memory reference insts executed
+system.cpu.iew.exec_branches 30889184 # Number of branches executed
+system.cpu.iew.exec_stores 33016441 # Number of stores executed
+system.cpu.iew.exec_rate 2.276464 # Inst execution rate
+system.cpu.iew.wb_sent 299955561 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 299540489 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 219513821 # num instructions producing a value
+system.cpu.iew.wb_consumers 298021184 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.268625 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.736609 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.268699 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.736571 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 37658416 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 37662479 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 911380 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 126814973 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.193688 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.964855 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 911334 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 126783014 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.194241 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.965349 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58216662 45.91% 45.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 19288284 15.21% 61.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11866550 9.36% 70.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9593635 7.57% 78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1717867 1.35% 79.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2074758 1.64% 81.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1297787 1.02% 82.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 717245 0.57% 82.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22042185 17.38% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58216104 45.92% 45.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 19275036 15.20% 61.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 11824840 9.33% 70.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9597612 7.57% 78.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1736989 1.37% 79.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2070795 1.63% 81.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1302129 1.03% 82.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 715865 0.56% 82.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22043644 17.39% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 126814973 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 126783014 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186174 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22042185 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22043644 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 420623668 # The number of ROB reads
-system.cpu.rob.rob_writes 636875907 # The number of ROB writes
-system.cpu.timesIdled 13847 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 77275 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 420594313 # The number of ROB reads
+system.cpu.rob.rob_writes 636885752 # The number of ROB writes
+system.cpu.timesIdled 13744 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 78072 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
-system.cpu.cpi 0.835892 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.835892 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.196327 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.196327 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 592882448 # number of integer regfile reads
-system.cpu.int_regfile_writes 300260228 # number of integer regfile writes
-system.cpu.fp_regfile_reads 139 # number of floating regfile reads
-system.cpu.fp_regfile_writes 69 # number of floating regfile writes
-system.cpu.misc_regfile_reads 192732445 # number of misc regfile reads
+system.cpu.cpi 0.835705 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.835705 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.196594 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.196594 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 592843050 # number of integer regfile reads
+system.cpu.int_regfile_writes 300182545 # number of integer regfile writes
+system.cpu.fp_regfile_reads 134 # number of floating regfile reads
+system.cpu.fp_regfile_writes 63 # number of floating regfile writes
+system.cpu.misc_regfile_reads 192703630 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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-system.cpu.dcache.blocked_cycles::no_mshrs 32091 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 74669662 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 74669662 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 74669662 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 74669662 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060772 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.060772 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.036497 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.036497 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.036497 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.036497 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11926.786684 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11926.786684 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21541.187563 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21541.187563 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12272.579710 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12272.579710 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32228 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9458 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 9462 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.393001 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.406045 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066502 # number of writebacks
-system.cpu.dcache.writebacks::total 2066502 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631907 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631907 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16126 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16126 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 648033 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 648033 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 648033 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 648033 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994024 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994024 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82155 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82155 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076179 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076179 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076179 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076179 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982252000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982252000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1835038498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1835038498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23817290498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23817290498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817290498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23817290498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046108 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046108 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 2066214 # number of writebacks
+system.cpu.dcache.writebacks::total 2066214 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 633159 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 633159 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15862 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 15862 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 649021 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 649021 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 649021 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 649021 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994027 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1994027 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82153 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 82153 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2076180 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2076180 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2076180 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2076180 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983040000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983040000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1837362499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1837362499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820402499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 23820402499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820402499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 23820402499 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.027799 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027799 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.065909 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.065909 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22336.297219 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22336.297219 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.444504 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.444504 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22365.129685 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22365.129685 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
+warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
hack: be nice to actually delete the event here
+Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:21:53
-gem5 started Mar 4 2013 00:58:30
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 01:41:39
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 199930442500 because target called exit()
+Exiting @ tick 199986318000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.199979 # Number of seconds simulated
-sim_ticks 199978768500 # Number of ticks simulated
-final_tick 199978768500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.199986 # Number of seconds simulated
+sim_ticks 199986318000 # Number of ticks simulated
+final_tick 199986318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109627 # Simulator instruction rate (inst/s)
-host_op_rate 123597 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43391530 # Simulator tick rate (ticks/s)
-host_mem_usage 297064 # Number of bytes of host memory used
-host_seconds 4608.71 # Real time elapsed on the host
+host_inst_rate 53828 # Simulator instruction rate (inst/s)
+host_op_rate 60688 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21306693 # Simulator tick rate (ticks/s)
+host_mem_usage 292380 # Number of bytes of host memory used
+host_seconds 9386.08 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9257984 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9474688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9268096 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9484800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6246208 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6246208 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 6249408 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6249408 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144656 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148042 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97597 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97597 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1083635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 46294835 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47378470 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1083635 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1083635 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 31234356 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 31234356 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 31234356 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1083635 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 46294835 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 78612825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148043 # Total number of read requests seen
-system.physmem.writeReqs 97597 # Total number of write requests seen
-system.physmem.cpureqs 245655 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9474688 # Total number of bytes read from memory
-system.physmem.bytesWritten 6246208 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9474688 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6246208 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 8 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9161 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9178 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 9858 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9513 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 9525 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9082 # Track reads on a per bank basis
+system.physmem.num_reads::cpu.data 144814 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148200 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97647 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97647 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1083594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 46343650 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47427244 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1083594 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1083594 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 31249178 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 31249178 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 31249178 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1083594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 46343650 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 78676422 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148200 # Total number of read requests seen
+system.physmem.writeReqs 97647 # Total number of write requests seen
+system.physmem.cpureqs 245864 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9484800 # Total number of bytes read from memory
+system.physmem.bytesWritten 6249408 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9484800 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6249408 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9181 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9533 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 9493 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9413 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 9073 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 9249 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9050 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9211 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 9024 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9010 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5953 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6271 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6483 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 6237 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6224 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6034 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5978 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6180 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5903 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6100 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 5977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 5948 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 6051 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6106 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::9 9296 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 8842 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9072 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9240 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 9010 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9027 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 9230 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5960 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 5978 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6283 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6480 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6185 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6216 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6227 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6210 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5897 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6108 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6001 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 5939 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 6059 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6112 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
-system.physmem.totGap 199978745500 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
+system.physmem.totGap 199986294500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148043 # Categorize read packet sizes
+system.physmem.readPktSize::6 148200 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 97597 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 138031 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 97647 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 138069 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9399 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4231 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4232 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4229 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4235 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
-system.physmem.totQLat 1694406500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4963552750 # Sum of mem lat for all requests
-system.physmem.totBusLat 739875000 # Total cycles spent in databus access
-system.physmem.totBankLat 2529271250 # Total cycles spent in bank access
-system.physmem.avgQLat 11450.63 # Average queueing delay per request
-system.physmem.avgBankLat 17092.56 # Average bank access latency per request
+system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
+system.physmem.totQLat 1719312500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4989180000 # Sum of mem lat for all requests
+system.physmem.totBusLat 740610000 # Total cycles spent in databus access
+system.physmem.totBankLat 2529257500 # Total cycles spent in bank access
+system.physmem.avgQLat 11607.41 # Average queueing delay per request
+system.physmem.avgBankLat 17075.50 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33543.18 # Average memory access latency
-system.physmem.avgRdBW 47.38 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 31.23 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 47.38 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 31.23 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 33682.91 # Average memory access latency
+system.physmem.avgRdBW 47.43 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 47.43 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.16 # Average write queue length over time
-system.physmem.readRowHits 125326 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52813 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 54.11 # Row buffer hit rate for writes
-system.physmem.avgGap 814113.11 # Average gap between requests
-system.cpu.branchPred.lookups 182790798 # Number of BP lookups
-system.cpu.branchPred.condPredicted 143104560 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7266331 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 93146978 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 87211884 # Number of BTB hits
+system.physmem.avgWrQLen 8.37 # Average write queue length over time
+system.physmem.readRowHits 125428 # Number of row buffer hits during reads
+system.physmem.writeRowHits 52865 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 54.14 # Row buffer hit rate for writes
+system.physmem.avgGap 813458.35 # Average gap between requests
+system.cpu.branchPred.lookups 182823475 # Number of BP lookups
+system.cpu.branchPred.condPredicted 143127293 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7270205 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 92181207 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 87235258 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.628248 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12679404 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 115837 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.634537 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12683949 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 116293 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 399957538 # number of cpu cycles simulated
+system.cpu.numCycles 399972637 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 119379666 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 761592104 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182790798 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 99891288 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170154666 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35685574 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 75463742 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 612 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 114537866 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2438685 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 392618085 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.175656 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.990351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 119392306 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 761693904 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182823475 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 99919207 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170173986 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35705843 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 75415774 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 554 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 114545284 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2440918 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 392617380 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.175996 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.990505 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 222476087 56.66% 56.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14184800 3.61% 60.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22904886 5.83% 66.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22739285 5.79% 71.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20904776 5.32% 77.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 11596191 2.95% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13057185 3.33% 83.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11992863 3.05% 86.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52762012 13.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 222455990 56.66% 56.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14183959 3.61% 60.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22907819 5.83% 66.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22738821 5.79% 71.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20904503 5.32% 77.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11594029 2.95% 80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13063211 3.33% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12002083 3.06% 86.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52766965 13.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 392618085 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.457026 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.904182 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129039701 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 70981785 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158852483 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6198857 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27545259 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26125355 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76645 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 825586648 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 296519 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27545259 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135624497 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9643215 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46459353 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158288427 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15057334 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 800646746 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1025 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3043913 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8811846 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 273 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 954314143 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3500751257 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3500749947 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 392617380 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.457090 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.904365 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129046079 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 70945312 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158884174 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6181299 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27560516 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26130325 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76946 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 825690179 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 295591 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27560516 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135633063 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9642191 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46463188 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158301033 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15017389 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 800753920 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1207 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3038316 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8776785 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 223 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 954449423 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3501232166 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3501230756 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1410 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288061852 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2293040 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2293037 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 41604001 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170281813 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 73487632 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28633593 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 16029977 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 755108515 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 665313430 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1367099 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187428477 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 480217782 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 392618085 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.694556 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.735285 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 288197132 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2293078 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2293075 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 41509096 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170293066 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 73496638 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 28553519 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15543647 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 755184516 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775403 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 665423791 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1392561 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187499467 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 480050290 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 797771 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 392617380 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.694840 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.736370 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 137184245 34.94% 34.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 69848764 17.79% 52.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71484982 18.21% 70.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53385142 13.60% 84.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31215558 7.95% 92.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16050252 4.09% 96.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8736886 2.23% 98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2893580 0.74% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1818676 0.46% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 137266683 34.96% 34.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 69764327 17.77% 52.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 71469341 18.20% 70.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53405229 13.60% 84.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31142767 7.93% 92.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16033920 4.08% 96.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8799646 2.24% 98.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2917185 0.74% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1818282 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 392618085 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 392617380 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 479033 5.02% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6517674 68.35% 73.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2539591 26.63% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 479464 4.97% 4.97% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6557477 68.01% 72.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2605087 27.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 447798832 67.31% 67.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383465 0.06% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 447824113 67.30% 67.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383504 0.06% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 98 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 153381199 23.05% 90.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 63749839 9.58% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 153397745 23.05% 90.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 63818328 9.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 665313430 # Type of FU issued
-system.cpu.iq.rate 1.663460 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9536298 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014334 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1734148123 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 947118126 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 646033691 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 665423791 # Type of FU issued
+system.cpu.iq.rate 1.663673 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9642028 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014490 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1734499320 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 947266498 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 646124282 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 674849617 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8562339 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 675065702 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8583068 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44252258 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 42000 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 809672 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16627155 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44263511 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 42384 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 811218 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16636161 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19517 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4404 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19502 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4251 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27545259 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5023337 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 374520 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 760443219 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1117317 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170281813 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 73487632 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 218824 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12460 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 809672 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4339991 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4001230 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8341221 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 655886711 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150097752 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9426719 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27560516 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5033845 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 374098 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 760518622 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1117950 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170293066 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 73496638 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2286861 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 218393 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11953 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 811218 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4001637 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8344571 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 655982546 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150110737 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9441245 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1559311 # number of nop insts executed
-system.cpu.iew.exec_refs 212556043 # number of memory reference insts executed
-system.cpu.iew.exec_branches 138504207 # Number of branches executed
-system.cpu.iew.exec_stores 62458291 # Number of stores executed
-system.cpu.iew.exec_rate 1.639891 # Inst execution rate
-system.cpu.iew.wb_sent 651006973 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 646033707 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 374766500 # num instructions producing a value
-system.cpu.iew.wb_consumers 646470459 # num instructions consuming a value
+system.cpu.iew.exec_nop 1558703 # number of nop insts executed
+system.cpu.iew.exec_refs 212627196 # number of memory reference insts executed
+system.cpu.iew.exec_branches 138502657 # Number of branches executed
+system.cpu.iew.exec_stores 62516459 # Number of stores executed
+system.cpu.iew.exec_rate 1.640069 # Inst execution rate
+system.cpu.iew.wb_sent 651101010 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 646124298 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 374793054 # num instructions producing a value
+system.cpu.iew.wb_consumers 646490687 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.615256 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579712 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.615421 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579735 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189501793 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 189577075 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7192333 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 365072826 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.563984 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.233117 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7196029 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 365056864 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.564053 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.233130 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 157316892 43.09% 43.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 98576092 27.00% 70.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33819222 9.26% 79.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18783601 5.15% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16197747 4.44% 88.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7430684 2.04% 90.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6971298 1.91% 92.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3187688 0.87% 93.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22789602 6.24% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 157408999 43.12% 43.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 98427012 26.96% 70.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33819592 9.26% 79.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18764553 5.14% 84.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16211195 4.44% 88.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7486266 2.05% 90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7003829 1.92% 92.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3174116 0.87% 93.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22761302 6.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 365072826 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 365056864 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22789602 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22761302 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1102746046 # The number of ROB reads
-system.cpu.rob.rob_writes 1548606173 # The number of ROB writes
-system.cpu.timesIdled 308814 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7339453 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1102833666 # The number of ROB reads
+system.cpu.rob.rob_writes 1548772691 # The number of ROB writes
+system.cpu.timesIdled 308172 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7355257 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
-system.cpu.cpi 0.791622 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.791622 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.263228 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.263228 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3058599019 # number of integer regfile reads
-system.cpu.int_regfile_writes 752005627 # number of integer regfile writes
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-system.cpu.dcache.WriteReq_misses::cpu.data 3247481 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3247481 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 187201931 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187201931 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187201931 # number of overall hits
+system.cpu.dcache.overall_hits::total 187201931 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1698949 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1698949 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3247674 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3247674 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4944384 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4944384 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4944384 # number of overall misses
-system.cpu.dcache.overall_misses::total 4944384 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 26525701000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 26525701000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57242727951 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57242727951 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1087000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 1087000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83768428951 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83768428951 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83768428951 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83768428951 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137917490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137917490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 4946623 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4946623 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4946623 # number of overall misses
+system.cpu.dcache.overall_misses::total 4946623 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 26713032500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 26713032500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57280936446 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57280936446 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 664500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 664500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 83993968946 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 83993968946 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 83993968946 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 83993968946 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137909248 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137909248 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488847 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488847 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488864 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488864 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192156796 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192156796 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192156796 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192156796 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012304 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012304 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059873 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059873 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 192148554 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192148554 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192148554 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192148554 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012319 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012319 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025731 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025731 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025731 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025731 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15631.831048 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15631.831048 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17626.809195 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17626.809195 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26512.195122 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26512.195122 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16942.136564 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16942.136564 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 18871 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 17919 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1660 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 609 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.368072 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 29.423645 # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15723.269209 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15723.269209 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17637.526564 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17637.526564 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16207.317073 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16207.317073 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16980.062751 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16980.062751 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 15427 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 16116 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1677 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 607 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.199165 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26.550247 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1111118 # number of writebacks
-system.cpu.dcache.writebacks::total 1111118 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 848410 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 848410 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899112 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2899112 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1110717 # number of writebacks
+system.cpu.dcache.writebacks::total 1110717 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850753 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 850753 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899322 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2899322 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3747522 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3747522 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3747522 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3747522 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848493 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848493 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348369 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348369 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196862 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196862 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196862 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196862 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11822842000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11822842000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8101779997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8101779997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19924621997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19924621997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19924621997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19924621997 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 3750075 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3750075 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3750075 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3750075 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848196 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848196 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348352 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348352 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196548 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196548 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196548 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196548 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853689000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853689000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8094107996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8094107996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19947796996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 19947796996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19947796996 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 19947796996 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13933.929920 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13933.929920 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23256.317287 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23256.317287 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13975.176728 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13975.176728 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23235.428521 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23235.428521 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 27 2013 00:05:57
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 434778577000 because target called exit()
+Exiting @ tick 434516346000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.434779 # Number of seconds simulated
-sim_ticks 434778577000 # Number of ticks simulated
-final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.434516 # Number of seconds simulated
+sim_ticks 434516346000 # Number of ticks simulated
+final_tick 434516346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92341 # Simulator instruction rate (inst/s)
-host_op_rate 170748 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48553388 # Simulator tick rate (ticks/s)
-host_mem_usage 422424 # Number of bytes of host memory used
-host_seconds 8954.65 # Real time elapsed on the host
+host_inst_rate 41156 # Simulator instruction rate (inst/s)
+host_op_rate 76102 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21627180 # Simulator tick rate (ticks/s)
+host_mem_usage 403680 # Number of bytes of host memory used
+host_seconds 20091.22 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24480192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24687808 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 207616 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 207616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18793792 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18793792 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3244 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382503 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385747 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293653 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293653 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 477521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 56304964 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 56782485 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 477521 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 477521 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 43226122 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 43226122 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 43226122 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 477521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 56304964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385749 # Total number of read requests seen
-system.physmem.writeReqs 293653 # Total number of write requests seen
-system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 24687808 # Total number of bytes read from memory
-system.physmem.bytesWritten 18793792 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 18793792 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 215914 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 23310 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 24517 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 23767 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 22579 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 23602 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24804 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 24363 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 24233 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 24554 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 24709 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 24156 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 24303 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 24582 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 23494 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 24683 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 23927 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 18810 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 18279 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 17552 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 18029 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 18664 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 18338 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 18780 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 18770 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 18402 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 18539 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 18562 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 17888 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis
+system.physmem.bytes_read::cpu.inst 207552 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24467712 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24675264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 207552 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 207552 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18791168 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18791168 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3243 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 382308 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385551 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293612 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293612 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 477662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 56310222 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 56787884 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 477662 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 477662 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 43246171 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 43246171 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 43246171 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 477662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 56310222 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 100034055 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385553 # Total number of read requests seen
+system.physmem.writeReqs 293612 # Total number of write requests seen
+system.physmem.cpureqs 889187 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 24675264 # Total number of bytes read from memory
+system.physmem.bytesWritten 18791168 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 24675264 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 18791168 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 209992 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 23303 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 24507 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 23750 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 22586 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 23590 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24765 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 24370 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 24220 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 24533 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 24693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 24138 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 24300 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 24598 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 23473 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 24673 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 23908 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 17801 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 18813 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 18266 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 17554 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 18027 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 18651 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 18325 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 18330 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 18772 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 18767 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 18400 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 18544 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 18575 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 17879 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 18803 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 18105 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry
-system.physmem.totGap 434778560000 # Total gap between requests
+system.physmem.totGap 434516329000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 385749 # Categorize read packet sizes
+system.physmem.readPktSize::6 385553 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 293653 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 380888 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4255 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 362 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 63 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 293612 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 380638 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4317 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 385 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 12710 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 12723 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 12724 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 12726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 12730 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 12731 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 12734 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 12734 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 12736 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see
-system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests
-system.physmem.totBusLat 1927915000 # Total cycles spent in databus access
-system.physmem.totBankLat 6665037500 # Total cycles spent in bank access
-system.physmem.avgQLat 8905.40 # Average queueing delay per request
-system.physmem.avgBankLat 17285.61 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 12716 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 12716 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 12716 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 12720 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 12725 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 12730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 12735 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31 # What write queue length does an incoming req see
+system.physmem.totQLat 3419098500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12003058500 # Sum of mem lat for all requests
+system.physmem.totBusLat 1927035000 # Total cycles spent in databus access
+system.physmem.totBankLat 6656925000 # Total cycles spent in bank access
+system.physmem.avgQLat 8871.40 # Average queueing delay per request
+system.physmem.avgBankLat 17272.45 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31191.01 # Average memory access latency
-system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 43.23 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31143.85 # Average memory access latency
+system.physmem.avgRdBW 56.79 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 56.79 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.78 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 9.96 # Average write queue length over time
-system.physmem.readRowHits 331863 # Number of row buffer hits during reads
-system.physmem.writeRowHits 191855 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.33 # Row buffer hit rate for writes
-system.physmem.avgGap 639943.01 # Average gap between requests
-system.cpu.branchPred.lookups 214994146 # Number of BP lookups
-system.cpu.branchPred.condPredicted 214994146 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 13135298 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 150584792 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 147887338 # Number of BTB hits
+system.physmem.avgWrQLen 9.12 # Average write queue length over time
+system.physmem.readRowHits 331790 # Number of row buffer hits during reads
+system.physmem.writeRowHits 191871 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 65.35 # Row buffer hit rate for writes
+system.physmem.avgGap 639780.21 # Average gap between requests
+system.cpu.branchPred.lookups 214953506 # Number of BP lookups
+system.cpu.branchPred.condPredicted 214953506 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13134677 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 150549169 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 147861057 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.208681 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 98.214462 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 869557155 # number of cpu cycles simulated
+system.cpu.numCycles 869032693 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 180620519 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1193264599 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 214994146 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 180543347 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1193643366 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 214953506 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 147861057 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 371295648 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83421023 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 231519953 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 318682 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 173452328 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3838970 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 853739491 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.595744 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.389493 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 18461820 2.16% 68.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 24636038 2.88% 71.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30640475 3.59% 75.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28823425 3.37% 78.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 486849125 57.03% 57.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24709977 2.89% 59.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 27353576 3.20% 63.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28812018 3.37% 66.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 18473026 2.16% 68.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 24594053 2.88% 71.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30667708 3.59% 75.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28872353 3.38% 78.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183407655 21.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2166915251 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2120054204 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 31988 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21457173 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 101130762 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 79 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2216502453 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5356043513 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5355912931 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 130582 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 853739491 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.247348 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.373531 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 237039901 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 188071412 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 313434986 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 45163547 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 70029645 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2166977882 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 70029645 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 270401805 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 53948111 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16882 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 322744473 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 136598575 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2120230208 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 31449 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 21240578 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 101108934 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 75 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2216675851 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5356592687 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5356461793 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 130894 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 602461599 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1415 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1390 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 330161364 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 512694390 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 204951429 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 196255090 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55443674 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2034023079 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 23697 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1808317213 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 841556 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 602634997 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1357 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 330209766 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 512741559 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 204921816 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 196294424 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 55462952 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2034039963 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22861 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1808186247 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 841927 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 499552997 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 818679497 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 22309 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 853739491 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.117960 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.887291 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 95894144 11.23% 87.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 58820201 6.89% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34887177 4.08% 98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12062824 1.41% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 233388219 27.34% 27.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 145263278 17.01% 44.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 138308175 16.20% 60.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 133084460 15.59% 76.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 96060946 11.25% 87.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 58814461 6.89% 94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 34920030 4.09% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 11982406 1.40% 99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1917516 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 853739491 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7752013 50.74% 83.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2567167 16.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4979468 32.47% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 7769551 50.66% 83.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2586637 16.87% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2720919 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1190891827 65.86% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2717049 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1190849468 65.86% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 438957859 24.27% 90.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 175746607 9.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 438947652 24.28% 90.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 175672078 9.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1808317213 # Type of FU issued
-system.cpu.iq.rate 2.079584 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 1808186247 # Type of FU issued
+system.cpu.iq.rate 2.080688 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 15335656 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008481 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4486267345 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2533832707 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1768692964 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 42394 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 5084 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1820864137 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 10431 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 170575963 # Number of loads that had data forwarded from stores
+system.cpu.iq.fp_inst_queue_writes 41984 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 4908 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1820794592 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 10262 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 170635682 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 128592233 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 466094 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 268512 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 55791476 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 128639402 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 477025 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 270655 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 55762006 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12171 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 512694390 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 204951662 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6140 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1820618 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 76746 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 268512 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 9116558 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4489858 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 13606416 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1780627625 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 431426006 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 27689588 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 70029645 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 16354856 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2869041 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2034062824 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2371349 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 512741559 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 204922192 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5971 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1818134 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 76688 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 270655 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 9112390 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4491959 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 13604349 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1780493134 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 431419821 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 27693113 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 602161774 # number of memory reference insts executed
-system.cpu.iew.exec_branches 169273752 # Number of branches executed
-system.cpu.iew.exec_stores 170735768 # Number of stores executed
-system.cpu.iew.exec_rate 2.047741 # Inst execution rate
-system.cpu.iew.wb_sent 1775545178 # cumulative count of insts sent to commit
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25071827 3.20% 84.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 28246222 3.60% 88.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9385684 1.20% 89.71% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
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-system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
-system.cpu.cpi 1.051616 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.051616 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.950917 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.950917 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3357648579 # number of integer regfile reads
-system.cpu.int_regfile_writes 1848573449 # number of integer regfile writes
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+system.cpu.cpi 1.050982 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.050982 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.951491 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.951491 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.overall_miss_latency::cpu.inst 1447936998 # number of overall miss cycles
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-system.cpu.icache.overall_miss_rate::total 0.001308 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.882072 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6380.882072 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 6380.882072 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6380.882072 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1948 # number of cycles access was blocked
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-system.cpu.icache.ReadReq_mshr_misses::total 224580 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 224580 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 224580 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4129.492827 # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency
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-system.cpu.l2cache.ReadReq_hits::total 1590474 # number of ReadReq hits
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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21973.932832 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21973.932832 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:48:30
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:39
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.066667
-Exiting @ tick 77336466500 because target called exit()
+Exiting @ tick 77333664500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.077334 # Number of seconds simulated
-sim_ticks 77333663500 # Number of ticks simulated
-final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 77333664500 # Number of ticks simulated
+final_tick 77333664500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 154881 # Simulator instruction rate (inst/s)
-host_op_rate 154881 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31891174 # Simulator tick rate (ticks/s)
-host_mem_usage 232452 # Number of bytes of host memory used
-host_seconds 2424.92 # Real time elapsed on the host
+host_inst_rate 71983 # Simulator instruction rate (inst/s)
+host_op_rate 71983 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14821773 # Simulator tick rate (ticks/s)
+host_mem_usage 278592 # Number of bytes of host memory used
+host_seconds 5217.57 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 77333595000 # Total gap between requests
+system.physmem.totGap 77333596000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 53845750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests
+system.physmem.totQLat 53843750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 206982500 # Sum of mem lat for all requests
system.physmem.totBusLat 37240000 # Total cycles spent in databus access
system.physmem.totBankLat 115898750 # Total cycles spent in bank access
-system.physmem.avgQLat 7229.56 # Average queueing delay per request
+system.physmem.avgQLat 7229.29 # Average queueing delay per request
system.physmem.avgBankLat 15561.06 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27790.61 # Average memory access latency
+system.physmem.avgMemAccLat 27790.35 # Average memory access latency
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 10383135.74 # Average gap between requests
-system.cpu.branchPred.lookups 50250166 # Number of BP lookups
-system.cpu.branchPred.condPredicted 29237479 # Number of conditional branches predicted
+system.physmem.avgGap 10383135.88 # Average gap between requests
+system.cpu.branchPred.lookups 50250164 # Number of BP lookups
+system.cpu.branchPred.condPredicted 29237478 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 25926395 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 25926393 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.591056 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 89.591063 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.data_misses 79544 # DTB misses
system.cpu.dtb.data_acv 48609 # DTB access violations
system.cpu.dtb.data_accesses 180298837 # DTB accesses
-system.cpu.itb.fetch_hits 50219857 # ITB hits
+system.cpu.itb.fetch_hits 50219856 # ITB hits
system.cpu.itb.fetch_misses 371 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 50220228 # ITB accesses
+system.cpu.itb.fetch_accesses 50220227 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 154667329 # number of cpu cycles simulated
+system.cpu.numCycles 154667331 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles 51106135 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 448668997 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 50250164 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 78764976 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 19721558 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 50219856 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 154473494 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 75708518 49.01% 49.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35257808 22.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 154473494 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running
+system.cpu.decode.IdleCycles 56459568 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 15066335 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 74129389 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9471001 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4302 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode
+system.cpu.decode.BranchResolved 9471000 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4301 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 444763316 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 59590781 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles 403368 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 75043533 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 9691219 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 440325289 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups
+system.cpu.rename.IQFullEvents 19776 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8008631 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 287258502 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 578891140 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 306269617 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 27726173 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 27858969 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 154473494 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 28241556 18.28% 18.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24263581 15.71% 67.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 21289314 13.78% 81.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8473784 5.49% 96.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154473494 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 34111 0.29% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5072340 42.83% 74.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
system.cpu.iq.rate 2.597191 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 11841749 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_reads 633918873 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 260111128 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 241419357 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 15066518 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 48930 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.memOrderViolation 48929 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 48930 # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents 48929 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_rate 2.574493 # Inst execution rate
system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 193534237 # num instructions producing a value
-system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value
+system.cpu.iew.wb_producers 193534239 # num instructions producing a value
+system.cpu.iew.wb_consumers 271064266 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 149606507 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.199553 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38148.684515 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47553.986063 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.950649 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.039911 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.039911 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 780 # number of replacements
-system.cpu.dcache.tagsinuse 3297.047136 # Cycle average of tags in use
-system.cpu.dcache.total_refs 159960719 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3297.047137 # Cycle average of tags in use
+system.cpu.dcache.total_refs 159960717 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 38249.813247 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 38249.812769 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3297.047136 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 3297.047137 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 86459753 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86459753 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 86459751 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 86459751 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 159960713 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 159960713 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 159960713 # number of overall hits
-system.cpu.dcache.overall_hits::total 159960713 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 159960711 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 159960711 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 159960711 # number of overall hits
+system.cpu.dcache.overall_hits::total 159960711 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses
system.cpu.dcache.overall_misses::total 21580 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 89990500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 89990500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566610 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 779566610 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 869557110 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 869557110 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 869557110 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 869557110 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 86461564 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 86461564 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566110 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 779566110 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 869553610 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 869553610 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 869553610 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 869553610 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 86461562 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 86461562 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 159982293 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 159982293 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 159982293 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 159982293 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 159982291 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 159982291 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 159982291 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 159982291 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49691.054666 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49691.054666 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.790784 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.790784 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40294.583411 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40294.583411 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 28158 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.765491 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.765491 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40294.421223 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40294.421223 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 28157 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.624406 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.622821 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53866000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 53866000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53865000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 53865000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221121500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 221121500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221121500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 221121500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54409.090909 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54409.090909 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:21:53
-gem5 started Mar 4 2013 01:05:57
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 03:18:38
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.060000
-Exiting @ tick 68244180000 because target called exit()
+Exiting @ tick 68258363000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.068244 # Number of seconds simulated
-sim_ticks 68244180000 # Number of ticks simulated
-final_tick 68244180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.068258 # Number of seconds simulated
+sim_ticks 68258363000 # Number of ticks simulated
+final_tick 68258363000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 137663 # Simulator instruction rate (inst/s)
-host_op_rate 175996 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34408261 # Simulator tick rate (ticks/s)
-host_mem_usage 247964 # Number of bytes of host memory used
-host_seconds 1983.37 # Real time elapsed on the host
+host_inst_rate 73419 # Simulator instruction rate (inst/s)
+host_op_rate 93863 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18354583 # Simulator tick rate (ticks/s)
+host_mem_usage 296524 # Number of bytes of host memory used
+host_seconds 3718.87 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 194624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272640 # Number of bytes read from this memory
-system.physmem.bytes_read::total 467264 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 194624 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 194624 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3041 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4260 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7301 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2851877 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3995066 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6846943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2851877 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2851877 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2851877 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3995066 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6846943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7301 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 465984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4253 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7281 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2839095 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3987673 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6826768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2839095 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2839095 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2839095 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3987673 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6826768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7281 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 7303 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 467264 # Total number of bytes read from memory
+system.physmem.cpureqs 7284 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 465984 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 467264 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 465984 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 415 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 411 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 480 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 506 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 490 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 545 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 589 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 404 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 433 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 454 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 412 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 408 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 483 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 476 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 509 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 487 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 544 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 590 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 432 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 417 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 414 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 450 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 416 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 68243977000 # Total gap between requests
+system.physmem.totGap 68258164000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 7301 # Categorize read packet sizes
+system.physmem.readPktSize::6 7281 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2170 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 604 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4267 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2163 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 187 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 46265250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 192440250 # Sum of mem lat for all requests
-system.physmem.totBusLat 36505000 # Total cycles spent in databus access
-system.physmem.totBankLat 109670000 # Total cycles spent in bank access
-system.physmem.avgQLat 6336.84 # Average queueing delay per request
-system.physmem.avgBankLat 15021.23 # Average bank access latency per request
+system.physmem.totQLat 45271500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 191126500 # Sum of mem lat for all requests
+system.physmem.totBusLat 36405000 # Total cycles spent in databus access
+system.physmem.totBankLat 109450000 # Total cycles spent in bank access
+system.physmem.avgQLat 6217.76 # Average queueing delay per request
+system.physmem.avgBankLat 15032.28 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26358.07 # Average memory access latency
-system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26250.03 # Average memory access latency
+system.physmem.avgRdBW 6.83 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 6.83 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6086 # Number of row buffer hits during reads
+system.physmem.readRowHits 6071 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9347209.56 # Average gap between requests
-system.cpu.branchPred.lookups 35347226 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21179372 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1632309 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18774732 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 16740348 # Number of BTB hits
+system.physmem.avgGap 9374833.68 # Average gap between requests
+system.cpu.branchPred.lookups 35375534 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21203624 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1636565 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18693932 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 16765511 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.164245 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6786825 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 8584 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 89.684241 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 6786649 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 8328 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 136488361 # number of cpu cycles simulated
+system.cpu.numCycles 136516727 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 38874281 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 317253074 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 35347226 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23527173 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 70748427 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6762105 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21521098 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37491442 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 499448 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136264051 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.985356 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.454882 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 38896982 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 317376259 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 35375534 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 23552160 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 70779245 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6771648 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 21491054 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1891 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 37519444 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 509386 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 136293047 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.985311 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.454516 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66141604 48.54% 48.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6763728 4.96% 53.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5687382 4.17% 57.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6073172 4.46% 62.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4900819 3.60% 65.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4081259 3.00% 68.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3178170 2.33% 71.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4143187 3.04% 74.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35294730 25.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66138904 48.53% 48.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6767660 4.97% 53.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5699163 4.18% 57.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6081886 4.46% 62.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4905828 3.60% 65.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4088301 3.00% 68.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3176914 2.33% 71.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4135950 3.03% 74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35298441 25.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136264051 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258976 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.324397 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45367973 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16681900 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 66615179 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2549386 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5049613 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7322660 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69153 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 400837616 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 209818 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5049613 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50901379 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1945385 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 310174 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63573069 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14484431 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 393292714 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1657143 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10217675 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 990 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 431691317 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2328660715 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1256261052 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1072399663 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 136293047 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.259130 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.324816 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45396979 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16650013 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 66644263 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2546649 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5055143 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7329146 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 69002 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 400901285 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 213083 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 5055143 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50932623 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1928706 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 309700 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 63595700 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14471175 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 393334802 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1658050 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10199893 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1072 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 431829381 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2328856465 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1256465206 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1072391259 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 47125124 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11983 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11982 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 36474755 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 103439968 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 91241620 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4261673 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5285781 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 383905556 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22939 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 373879260 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1212222 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34116216 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 85509152 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136264051 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.743785 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.022773 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 47263188 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 11836 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11835 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 36477776 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 103434690 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 91236939 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4267637 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5260584 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 383959282 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 373920129 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1206190 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 34165918 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 85628063 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 136293047 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.743501 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.023111 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24800729 18.20% 18.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19931248 14.63% 32.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20555324 15.08% 47.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18170547 13.33% 61.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 24015276 17.62% 78.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15694879 11.52% 90.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8802527 6.46% 96.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3373106 2.48% 99.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 920415 0.68% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24835944 18.22% 18.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19923821 14.62% 32.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 20538519 15.07% 47.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18169219 13.33% 61.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 24028277 17.63% 78.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15701712 11.52% 90.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8800214 6.46% 96.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3374067 2.48% 99.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 921274 0.68% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136264051 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 136293047 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8942 0.05% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8902 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4689 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 45953 0.26% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 46241 0.26% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 7540 0.04% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 377 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 190605 1.08% 1.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 3637 0.02% 1.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 241259 1.36% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 7650 0.04% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 432 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 190629 1.08% 1.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 3972 0.02% 1.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241372 1.36% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9279550 52.34% 55.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7945926 44.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9278872 52.34% 55.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 7944742 44.82% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 126287490 33.78% 33.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2175875 0.58% 34.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 126315653 33.78% 33.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2175866 0.58% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6775486 1.81% 36.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8466993 2.26% 38.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3427515 0.92% 39.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1596271 0.43% 39.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20850336 5.58% 45.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7171756 1.92% 47.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125550 1.91% 49.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101538371 27.16% 76.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88288328 23.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6776888 1.81% 36.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8468895 2.26% 38.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3427953 0.92% 39.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1595639 0.43% 39.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20851093 5.58% 45.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7171347 1.92% 47.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7126740 1.91% 49.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101555976 27.16% 76.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88278790 23.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 373879260 # Type of FU issued
-system.cpu.iq.rate 2.739276 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17728490 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047418 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653579688 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 287780184 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 249896445 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 249383595 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 130278814 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118034540 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 263004554 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128603196 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 11120232 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 373920129 # Type of FU issued
+system.cpu.iq.rate 2.739006 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17727503 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 653684952 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 287885544 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 249920404 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 249382046 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 130276634 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118031995 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 263048449 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 128599183 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 11100195 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8791220 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 109151 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14386 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 8866037 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8785942 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 109607 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14276 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8861356 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 183726 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1452 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 182774 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1441 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5049613 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 296711 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 36519 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 383930075 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 867040 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 103439968 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 91241620 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11905 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 346 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14386 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1268963 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 369292 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1638255 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 369960329 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100240998 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3918931 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5055143 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 284926 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 36749 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 383983637 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 873190 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 103434690 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 91236939 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 337 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14276 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1271835 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 367005 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1638840 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 369984044 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100253903 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3936085 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1580 # number of nop insts executed
-system.cpu.iew.exec_refs 187474433 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31994663 # Number of branches executed
-system.cpu.iew.exec_stores 87233435 # Number of stores executed
-system.cpu.iew.exec_rate 2.710563 # Inst execution rate
-system.cpu.iew.wb_sent 368586369 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 367930985 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 182884452 # num instructions producing a value
-system.cpu.iew.wb_consumers 363518435 # num instructions consuming a value
+system.cpu.iew.exec_nop 1567 # number of nop insts executed
+system.cpu.iew.exec_refs 187478745 # number of memory reference insts executed
+system.cpu.iew.exec_branches 32002404 # Number of branches executed
+system.cpu.iew.exec_stores 87224842 # Number of stores executed
+system.cpu.iew.exec_rate 2.710174 # Inst execution rate
+system.cpu.iew.wb_sent 368608393 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 367952399 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 182920147 # num instructions producing a value
+system.cpu.iew.wb_consumers 363541669 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.695695 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.503095 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.695292 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.503161 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34865105 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 34918645 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1563496 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131214438 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.660264 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.659830 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1567905 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 131237904 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.659788 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.659697 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 34444562 26.25% 26.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 28434634 21.67% 47.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13308561 10.14% 58.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11464288 8.74% 66.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13753280 10.48% 77.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7411902 5.65% 82.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3868194 2.95% 85.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3893489 2.97% 88.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14635528 11.15% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 34480622 26.27% 26.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 28416799 21.65% 47.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13301568 10.14% 58.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11461353 8.73% 66.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13768973 10.49% 77.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7415781 5.65% 82.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 3872079 2.95% 85.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3892036 2.97% 88.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14628693 11.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131214438 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 131237904 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037337 # Number of instructions committed
system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 14635528 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14628693 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 500506553 # The number of ROB reads
-system.cpu.rob.rob_writes 772913753 # The number of ROB writes
-system.cpu.timesIdled 6384 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 224310 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 500590394 # The number of ROB reads
+system.cpu.rob.rob_writes 773026490 # The number of ROB writes
+system.cpu.timesIdled 6380 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 223680 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273036725 # Number of Instructions Simulated
system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
-system.cpu.cpi 0.499890 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.499890 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.000440 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.000440 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1768566472 # number of integer regfile reads
-system.cpu.int_regfile_writes 232719908 # number of integer regfile writes
-system.cpu.fp_regfile_reads 188077369 # number of floating regfile reads
-system.cpu.fp_regfile_writes 132460333 # number of floating regfile writes
-system.cpu.misc_regfile_reads 566743063 # number of misc regfile reads
+system.cpu.cpi 0.499994 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.499994 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.000024 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.000024 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1768667875 # number of integer regfile reads
+system.cpu.int_regfile_writes 232756138 # number of integer regfile writes
+system.cpu.fp_regfile_reads 188077365 # number of floating regfile reads
+system.cpu.fp_regfile_writes 132460015 # number of floating regfile writes
+system.cpu.misc_regfile_reads 566729148 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
-system.cpu.icache.replacements 13969 # number of replacements
-system.cpu.icache.tagsinuse 1853.582812 # Cycle average of tags in use
-system.cpu.icache.total_refs 37474292 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15862 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2362.519985 # Average number of references to valid blocks.
+system.cpu.icache.replacements 13935 # number of replacements
+system.cpu.icache.tagsinuse 1853.031974 # Cycle average of tags in use
+system.cpu.icache.total_refs 37502330 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 15827 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2369.516017 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1853.582812 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.905070 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.905070 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 37474292 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 37474292 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 37474292 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 37474292 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 37474292 # number of overall hits
-system.cpu.icache.overall_hits::total 37474292 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 17149 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 17149 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 17149 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 17149 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 17149 # number of overall misses
-system.cpu.icache.overall_misses::total 17149 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 365626498 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 365626498 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 365626498 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 365626498 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 365626498 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 365626498 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 37491441 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 37491441 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 37491441 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 37491441 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 37491441 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 37491441 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21320.572512 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21320.572512 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21320.572512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21320.572512 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 571 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1853.031974 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.904801 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.904801 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 37502330 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 37502330 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 37502330 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 37502330 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 37502330 # number of overall hits
+system.cpu.icache.overall_hits::total 37502330 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 17113 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17113 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17113 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17113 # number of demand (read+write) misses
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44080.219233 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 44080.219233 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.684817 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.684817 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43735.830458 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 43735.830458 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389647 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389647 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41809.188574 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41809.188574 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 15380 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 834 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 443 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41825.518489 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41825.518489 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 15191 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 833 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 436 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.717833 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 64.153846 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.841743 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 64.076923 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks
-system.cpu.dcache.writebacks::total 1038 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2216 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2216 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18359 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18359 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks
+system.cpu.dcache.writebacks::total 1043 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2254 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2254 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18357 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18357 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20575 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20575 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20575 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20575 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1798 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1798 # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 20611 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20611 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 20611 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 20611 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1804 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1804 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4614 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4614 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4614 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4614 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138581500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 138581500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224843000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 224843000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224843000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 224843000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138898000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 138898000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225159000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 225159000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225159000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 225159000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47976.362625 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47976.362625 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49212.180398 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49212.180398 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47816.518847 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47816.518847 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49324.573864 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49324.573864 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:57:22
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 626365181000 because target called exit()
+Exiting @ tick 626014950000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.629620 # Number of seconds simulated
-sim_ticks 629619966000 # Number of ticks simulated
-final_tick 629619966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.626015 # Number of seconds simulated
+sim_ticks 626014950000 # Number of ticks simulated
+final_tick 626014950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 178339 # Simulator instruction rate (inst/s)
-host_op_rate 178339 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61592425 # Simulator tick rate (ticks/s)
-host_mem_usage 247872 # Number of bytes of host memory used
-host_seconds 10222.36 # Real time elapsed on the host
+host_inst_rate 71515 # Simulator instruction rate (inst/s)
+host_op_rate 71515 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24557485 # Simulator tick rate (ticks/s)
+host_mem_usage 282608 # Number of bytes of host memory used
+host_seconds 25491.82 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 176384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 176384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 176384 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30295808 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30471744 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2756 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 473372 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476121 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 280144 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48117813 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48397957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 280144 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 280144 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6801106 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6801106 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6801106 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 280144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48117813 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55199063 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476130 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 281041 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48394704 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48675745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 281041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 281041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6840271 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6840271 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6840271 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 281041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48394704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55516016 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476121 # Total number of read requests seen
system.physmem.writeReqs 66908 # Total number of write requests seen
-system.physmem.cpureqs 543038 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30472320 # Total number of bytes read from memory
+system.physmem.cpureqs 543029 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30471744 # Total number of bytes read from memory
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30472320 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30471744 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29664 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29737 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29644 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29817 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 29662 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29647 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29658 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29696 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29813 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29790 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29703 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29697 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29783 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29762 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29859 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29815 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 629619903500 # Total gap between requests
+system.physmem.totGap 626014887500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 476130 # Categorize read packet sizes
+system.physmem.readPktSize::6 476121 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66908 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 406575 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66997 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2280 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 167 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 406557 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66998 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 164 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2394780250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 20405886500 # Sum of mem lat for all requests
-system.physmem.totBusLat 2380230000 # Total cycles spent in databus access
-system.physmem.totBankLat 15630876250 # Total cycles spent in bank access
-system.physmem.avgQLat 5030.56 # Average queueing delay per request
-system.physmem.avgBankLat 32834.80 # Average bank access latency per request
+system.physmem.totQLat 3500552500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 21508187500 # Sum of mem lat for all requests
+system.physmem.totBusLat 2380155000 # Total cycles spent in databus access
+system.physmem.totBankLat 15627480000 # Total cycles spent in bank access
+system.physmem.avgQLat 7353.62 # Average queueing delay per request
+system.physmem.avgBankLat 32828.70 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 42865.37 # Average memory access latency
-system.physmem.avgRdBW 48.40 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.40 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 45182.33 # Average memory access latency
+system.physmem.avgRdBW 48.68 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.68 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
system.physmem.avgWrQLen 11.00 # Average write queue length over time
-system.physmem.readRowHits 143857 # Number of row buffer hits during reads
-system.physmem.writeRowHits 46184 # Number of row buffer hits during writes
+system.physmem.readRowHits 143853 # Number of row buffer hits during reads
+system.physmem.writeRowHits 46182 # Number of row buffer hits during writes
system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes
-system.physmem.avgGap 1159439.86 # Average gap between requests
-system.cpu.branchPred.lookups 389447649 # Number of BP lookups
-system.cpu.branchPred.condPredicted 255913711 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25827412 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 318653162 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 258406685 # Number of BTB hits
+system.physmem.writeRowHitRate 69.02 # Row buffer hit rate for writes
+system.physmem.avgGap 1152820.36 # Average gap between requests
+system.cpu.branchPred.lookups 388875863 # Number of BP lookups
+system.cpu.branchPred.condPredicted 256999007 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25264722 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 310547770 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 257563099 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.093401 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 57304748 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 7060 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 82.938319 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 56744188 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6782 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 523436365 # DTB read hits
-system.cpu.dtb.read_misses 589877 # DTB read misses
+system.cpu.dtb.read_hits 519038391 # DTB read hits
+system.cpu.dtb.read_misses 606346 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 524026242 # DTB read accesses
-system.cpu.dtb.write_hits 283043527 # DTB write hits
-system.cpu.dtb.write_misses 50254 # DTB write misses
+system.cpu.dtb.read_accesses 519644737 # DTB read accesses
+system.cpu.dtb.write_hits 282491025 # DTB write hits
+system.cpu.dtb.write_misses 50159 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 283093781 # DTB write accesses
-system.cpu.dtb.data_hits 806479892 # DTB hits
-system.cpu.dtb.data_misses 640131 # DTB misses
+system.cpu.dtb.write_accesses 282541184 # DTB write accesses
+system.cpu.dtb.data_hits 801529416 # DTB hits
+system.cpu.dtb.data_misses 656505 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 807120023 # DTB accesses
-system.cpu.itb.fetch_hits 394546295 # ITB hits
-system.cpu.itb.fetch_misses 717 # ITB misses
+system.cpu.dtb.data_accesses 802185921 # DTB accesses
+system.cpu.itb.fetch_hits 390623308 # ITB hits
+system.cpu.itb.fetch_misses 546 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 394547012 # ITB accesses
+system.cpu.itb.fetch_accesses 390623854 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1259239933 # number of cpu cycles simulated
+system.cpu.numCycles 1252029901 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 410282333 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3275811622 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 389447649 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 315711433 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 630410102 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 157985911 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 72865288 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7390 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 394546295 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10716533 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1245235231 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.630677 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.141977 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 405523870 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3256215701 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 388875863 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 314307287 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 626203619 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 155794648 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 73991596 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 6471 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 390623308 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10992432 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1235766511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.634976 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.141364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614825129 49.37% 49.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 58056687 4.66% 54.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43354375 3.48% 57.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 71856761 5.77% 63.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 128610709 10.33% 73.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 45745044 3.67% 77.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41218746 3.31% 80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7546870 0.61% 81.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 234020910 18.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 609562892 49.33% 49.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 56929322 4.61% 53.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 42752934 3.46% 57.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71333026 5.77% 63.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 128895698 10.43% 73.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 44916877 3.63% 77.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41222080 3.34% 80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8947680 0.72% 81.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 231206002 18.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1245235231 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.309272 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.601420 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 438008414 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 59262942 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 607236165 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9069872 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 131657838 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 32266957 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12470 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3196223031 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46480 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 131657838 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 467254081 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 24463646 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 27494 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 586711565 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 35120607 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3098173488 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 98 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 15446 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 28849573 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2055567023 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3582389843 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3461627532 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 120762311 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1235766511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.310596 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.600749 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 434050234 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 59825791 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 602225660 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9636107 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 130028719 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 31692009 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12420 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3180730731 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46427 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 130028719 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 463334620 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 24461750 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27280 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 582229724 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 35684418 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3082031269 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 15345 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 29415634 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2044995723 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3566316890 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3445638932 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 120677958 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 670597953 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4242 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 109579430 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 745093938 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 351398329 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68579657 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8864385 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2626006003 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2162044617 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17925122 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 802898808 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 727596475 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1245235231 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.736254 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.804060 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 660026653 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 110158163 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 738560803 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 349770872 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 68005426 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8800641 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2612267018 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2153832750 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17944057 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 789157528 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 720017007 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1235766511 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.742912 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.802932 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 447917303 35.97% 35.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 197535103 15.86% 51.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 251432136 20.19% 72.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 120080138 9.64% 81.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 104735346 8.41% 90.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 79904704 6.42% 96.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 24241740 1.95% 98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17620604 1.42% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1768157 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 442318037 35.79% 35.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 194738197 15.76% 51.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 250284254 20.25% 71.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 121277806 9.81% 81.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 105807762 8.56% 90.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 77171137 6.24% 96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 25347258 2.05% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17054134 1.38% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1767926 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1245235231 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1235766511 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1146296 3.12% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 25620524 69.67% 72.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 10007560 27.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1146289 3.17% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25061435 69.20% 72.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 10007223 27.63% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1235570303 57.15% 57.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 27851417 1.29% 58.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 590015596 27.29% 86.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 293128107 13.56% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1231694482 57.19% 57.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 17093 0.00% 57.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27851386 1.29% 58.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 586233325 27.22% 86.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 292574368 13.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2162044617 # Type of FU issued
-system.cpu.iq.rate 1.716944 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36774380 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.017009 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5472922147 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3340796044 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1991352678 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 151101820 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 88182161 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 73610057 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2121366202 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 77450043 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63177927 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2153832750 # Type of FU issued
+system.cpu.iq.rate 1.720273 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36214947 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016814 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5446489367 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3313484734 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1984683423 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 151101648 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88013502 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 73610007 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2112595001 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 77449944 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62149579 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 234023912 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 1058362 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 75850 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 140603433 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 227490777 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 22685 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 76128 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 138975976 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2424 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2362 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 131657838 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 10420983 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 524239 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2989422700 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 731121 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 745093938 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 351398329 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 100 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 195339 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 75850 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 25820235 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 27779 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25848014 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2068492319 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 524026374 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 93552298 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 130028719 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 10422536 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 524259 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2975772151 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 731348 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 738560803 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 349770872 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 195346 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 76128 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 25258103 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 28541 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25286644 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2060237153 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 519644898 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 93595597 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 363416597 # number of nop insts executed
-system.cpu.iew.exec_refs 807120680 # number of memory reference insts executed
-system.cpu.iew.exec_branches 278196977 # Number of branches executed
-system.cpu.iew.exec_stores 283094306 # Number of stores executed
-system.cpu.iew.exec_rate 1.642651 # Inst execution rate
-system.cpu.iew.wb_sent 2067333908 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2064962735 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1181126750 # num instructions producing a value
-system.cpu.iew.wb_consumers 1753498514 # num instructions consuming a value
+system.cpu.iew.exec_nop 363505042 # number of nop insts executed
+system.cpu.iew.exec_refs 802186536 # number of memory reference insts executed
+system.cpu.iew.exec_branches 277071948 # Number of branches executed
+system.cpu.iew.exec_stores 282541638 # Number of stores executed
+system.cpu.iew.exec_rate 1.645518 # Inst execution rate
+system.cpu.iew.wb_sent 2060115451 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2058293430 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1179460731 # num instructions producing a value
+system.cpu.iew.wb_consumers 1750814151 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.639849 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.673583 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.643965 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.673664 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 963484022 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 949829893 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25815357 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1113577393 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.804084 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.508160 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25252672 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1105737792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.816875 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.519271 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 494309525 44.39% 44.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 228815920 20.55% 64.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 119838693 10.76% 75.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 58859369 5.29% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 50684004 4.55% 85.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24146580 2.17% 87.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19115188 1.72% 89.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 16708765 1.50% 90.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101099349 9.08% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 488711252 44.20% 44.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 226575390 20.49% 64.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 120398789 10.89% 75.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 59423757 5.37% 80.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 48998760 4.43% 85.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 24145631 2.18% 87.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 18552721 1.68% 89.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 16148092 1.46% 90.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102783400 9.30% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1113577393 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1105737792 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 101099349 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 102783400 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3979313260 # The number of ROB reads
-system.cpu.rob.rob_writes 6076602940 # The number of ROB writes
-system.cpu.timesIdled 331541 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14004702 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3956135479 # The number of ROB reads
+system.cpu.rob.rob_writes 6047665736 # The number of ROB writes
+system.cpu.timesIdled 331504 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 16263390 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.690735 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.690735 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.447733 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.447733 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2629807592 # number of integer regfile reads
-system.cpu.int_regfile_writes 1497388428 # number of integer regfile writes
-system.cpu.fp_regfile_reads 78811502 # number of floating regfile reads
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+system.cpu.dcache.overall_accesses::cpu.data 667677080 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 667677080 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004215 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004215 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.037037 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.037037 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33643.463338 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 33643.463338 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33361.772941 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33361.772941 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33543.352622 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33543.352622 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 14428 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004475 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004475 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004475 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004475 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34229.233426 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34229.233426 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33348.464628 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33348.464628 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33916.205570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33916.205570 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13719 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 387 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 382 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.281654 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.913613 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks
system.cpu.dcache.writebacks::total 95989 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465591 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 465591 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990129 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 990129 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1455720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1455720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1455720 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1455720 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460239 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460239 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1531882 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1531882 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1531882 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1531882 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39489667000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 39489667000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43389200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 43389200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43389200000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 43389200000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003173 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003173 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465539 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 465539 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990134 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 990134 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1455673 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1455673 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1455673 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1455673 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460212 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460212 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1531854 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1531854 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1531854 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1531854 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40615263000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 40615263000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3896657000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3896657000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44511920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 44511920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44511920000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 44511920000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003196 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003196 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.037037 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.037037 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27043.290174 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27043.290174 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54430.062951 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54430.062951 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002294 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002294 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27814.634450 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27814.634450 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54390.678652 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54390.678652 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:21:53
-gem5 started Mar 4 2013 01:12:21
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:55:03
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 627439125000 because target called exit()
+Exiting @ tick 627426486000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.627439 # Number of seconds simulated
-sim_ticks 627439125000 # Number of ticks simulated
-final_tick 627439125000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.627426 # Number of seconds simulated
+sim_ticks 627426486000 # Number of ticks simulated
+final_tick 627426486000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 96597 # Simulator instruction rate (inst/s)
-host_op_rate 131552 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43780556 # Simulator tick rate (ticks/s)
-host_mem_usage 260984 # Number of bytes of host memory used
-host_seconds 14331.46 # Real time elapsed on the host
+host_inst_rate 65805 # Simulator instruction rate (inst/s)
+host_op_rate 89618 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29824381 # Simulator tick rate (ticks/s)
+host_mem_usage 297136 # Number of bytes of host memory used
+host_seconds 21037.37 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30242368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30397376 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 154240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30242112 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30396352 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 154240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 154240 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472537 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474959 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2410 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472533 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 474943 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 247049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48199685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48446733 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 247049 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 247049 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6742123 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6742123 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6742123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 247049 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48199685 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55188857 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474959 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 245830 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48200248 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48446077 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 245830 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 245830 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6742259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6742259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6742259 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 245830 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48200248 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55188336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 474944 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30397376 # Total number of bytes read from memory
+system.physmem.cpureqs 545373 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30396352 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30397376 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30396352 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4291 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29712 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29706 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29691 # Track reads on a per bank basis
+system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4331 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 29709 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29700 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29689 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29689 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29747 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29640 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29682 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29719 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29749 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29652 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29679 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29602 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29628 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29649 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29599 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29613 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29623 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29684 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29651 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 627439056500 # Total gap between requests
+system.physmem.totGap 627426443000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 474959 # Categorize read packet sizes
+system.physmem.readPktSize::6 474944 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66098 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 405906 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2122 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 405886 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3462811500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 21441489000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2374050000 # Total cycles spent in databus access
-system.physmem.totBankLat 15604627500 # Total cycles spent in bank access
-system.physmem.avgQLat 7293.05 # Average queueing delay per request
-system.physmem.avgBankLat 32864.99 # Average bank access latency per request
+system.physmem.totQLat 3439648250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 21418222000 # Sum of mem lat for all requests
+system.physmem.totBusLat 2373960000 # Total cycles spent in databus access
+system.physmem.totBankLat 15604613750 # Total cycles spent in bank access
+system.physmem.avgQLat 7244.54 # Average queueing delay per request
+system.physmem.avgBankLat 32866.21 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 45158.04 # Average memory access latency
+system.physmem.avgMemAccLat 45110.75 # Average memory access latency
system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
system.physmem.avgWrQLen 17.42 # Average write queue length over time
-system.physmem.readRowHits 143341 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45511 # Number of row buffer hits during writes
+system.physmem.readRowHits 143318 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45505 # Number of row buffer hits during writes
system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 68.85 # Row buffer hit rate for writes
-system.physmem.avgGap 1159654.26 # Average gap between requests
-system.cpu.branchPred.lookups 440649573 # Number of BP lookups
-system.cpu.branchPred.condPredicted 353682166 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30631043 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 252533039 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 230279415 # Number of BTB hits
+system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes
+system.physmem.avgGap 1159663.10 # Average gap between requests
+system.cpu.branchPred.lookups 441070019 # Number of BP lookups
+system.cpu.branchPred.condPredicted 353935839 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30635394 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 253577570 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 230740155 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 91.187837 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 51764959 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2806562 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 90.993914 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 51827244 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2806499 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1254878251 # number of cpu cycles simulated
+system.cpu.numCycles 1254852973 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 354654463 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2286055838 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 440649573 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 282044374 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 601927539 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 156613440 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 130193180 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 10572 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 335557697 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11970074 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1212716808 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.588686 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.181757 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 354891147 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2286425176 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 441070019 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 282567399 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 601918215 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 156601137 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 130017521 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 563 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11246 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 335797832 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11972922 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1212752602 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.588148 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.180737 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 610833811 50.37% 50.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 43093126 3.55% 53.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 96161904 7.93% 61.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 57061464 4.71% 66.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 71748155 5.92% 72.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 43390011 3.58% 76.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30893705 2.55% 78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 32839857 2.71% 81.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 226694775 18.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 610879185 50.37% 50.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42915841 3.54% 53.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 96172627 7.93% 61.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 57091199 4.71% 66.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 71993232 5.94% 72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 43518781 3.59% 76.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30912276 2.55% 78.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 32947513 2.72% 81.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 226321948 18.66% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1212716808 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.351149 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.821735 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 405646781 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 102637713 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561793047 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16722466 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 125916801 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44665335 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 13931 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3029413956 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 28108 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 125916801 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 441580002 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34476908 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 437379 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540507560 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 69798158 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2946364126 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4812832 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 54672934 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2931066413 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14023290204 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13452684524 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 570605680 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1212752602 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.351491 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.822066 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 405845320 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 102427093 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 561818768 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 16761536 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 125899885 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 44789430 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 14217 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3028082478 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 30107 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 125899885 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 441818256 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 34409054 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 439229 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 540562916 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 69623262 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2944183318 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4821524 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 54501316 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2929324563 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14012451828 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13441344414 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 571107414 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 937926323 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 22415 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 19926 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 179121288 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 970649993 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 487168712 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36377618 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40069949 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2792240287 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 29328 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2432835777 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13263841 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 894381457 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2312630775 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 7944 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1212716808 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.006104 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 936184473 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 21713 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 19183 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 177423093 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 969808911 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 487407647 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36223294 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 40155637 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2791556624 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 29091 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2432817301 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13264046 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 893693392 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2309057295 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 7707 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1212752602 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.006029 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.872054 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 376728714 31.06% 31.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183811265 15.16% 46.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 203907049 16.81% 63.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169580498 13.98% 77.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132860198 10.96% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 92416507 7.62% 95.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37964146 3.13% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12426731 1.02% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3021700 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 376736827 31.06% 31.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183745627 15.15% 46.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 204018800 16.82% 63.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 169675350 13.99% 77.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 132825359 10.95% 87.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 92323584 7.61% 95.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37944626 3.13% 98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12438520 1.03% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 3043909 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1212716808 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1212752602 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 716116 0.82% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24381 0.03% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55122687 62.92% 63.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31746374 36.24% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 715136 0.82% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55109735 62.90% 63.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 31764891 36.26% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1103971506 45.38% 45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11223452 0.46% 45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1103878887 45.37% 45.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11223380 0.46% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502427 0.23% 46.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5503230 0.23% 46.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23409752 0.96% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838269607 34.46% 81.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442207267 18.18% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23422628 0.96% 47.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 838195655 34.45% 81.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 442341757 18.18% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2432835777 # Type of FU issued
-system.cpu.iq.rate 1.938703 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87609558 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.036011 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6056740662 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3603968769 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2248867979 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122521099 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82749412 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56444030 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2457121441 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63323894 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84335781 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2432817301 # Type of FU issued
+system.cpu.iq.rate 1.938727 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 87614143 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.036013 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6056711081 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3602481479 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2248827251 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 122554312 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82864717 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56458852 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2457090579 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63340865 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 84315452 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 339262812 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8485 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1431215 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 210173415 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 338421730 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8530 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1429952 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 210412350 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 257 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 125916801 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12646480 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1559895 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2792282007 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1384453 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 970649993 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 487168712 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19342 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1555909 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1431215 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32433063 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1530059 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33963122 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2358070725 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792574818 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 74765052 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 125899885 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 12642453 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1559188 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2791598235 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1393439 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 969808911 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 487407647 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 19105 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1555218 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1429952 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 32462166 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1535020 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 33997186 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2358042615 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 792538170 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 74774686 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12392 # number of nop insts executed
-system.cpu.iew.exec_refs 1216182478 # number of memory reference insts executed
-system.cpu.iew.exec_branches 319878188 # Number of branches executed
-system.cpu.iew.exec_stores 423607660 # Number of stores executed
-system.cpu.iew.exec_rate 1.879123 # Inst execution rate
-system.cpu.iew.wb_sent 2331089515 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2305312009 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347373640 # num instructions producing a value
-system.cpu.iew.wb_consumers 2522763992 # num instructions consuming a value
+system.cpu.iew.exec_nop 12520 # number of nop insts executed
+system.cpu.iew.exec_refs 1216339727 # number of memory reference insts executed
+system.cpu.iew.exec_branches 319851158 # Number of branches executed
+system.cpu.iew.exec_stores 423801557 # Number of stores executed
+system.cpu.iew.exec_rate 1.879139 # Inst execution rate
+system.cpu.iew.wb_sent 2331014082 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2305286103 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1347320139 # num instructions producing a value
+system.cpu.iew.wb_consumers 2523004414 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.837080 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.534086 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.837097 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.534014 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 906945779 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 906262003 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30617374 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1086800007 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.734759 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.398832 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 30621444 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1086852717 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.734675 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.398797 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 446471329 41.08% 41.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288644992 26.56% 67.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95109223 8.75% 76.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70211025 6.46% 82.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46444999 4.27% 87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22203598 2.04% 89.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15846659 1.46% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10983551 1.01% 91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90884631 8.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 446522418 41.08% 41.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288653852 26.56% 67.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95098505 8.75% 76.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 70200543 6.46% 82.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46464549 4.28% 87.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22199454 2.04% 89.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15846996 1.46% 90.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10984775 1.01% 91.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90881625 8.36% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1086800007 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1086852717 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90884631 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90881625 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3788179168 # The number of ROB reads
-system.cpu.rob.rob_writes 5710492063 # The number of ROB writes
-system.cpu.timesIdled 353297 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 42161443 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3787551108 # The number of ROB reads
+system.cpu.rob.rob_writes 5709107671 # The number of ROB writes
+system.cpu.timesIdled 353124 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 42100371 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.906461 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.906461 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.103191 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.103191 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11756795674 # number of integer regfile reads
-system.cpu.int_regfile_writes 2218922402 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68796713 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49556201 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1363984791 # number of misc regfile reads
+system.cpu.cpi 0.906443 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.906443 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.103213 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.103213 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11756785732 # number of integer regfile reads
+system.cpu.int_regfile_writes 2218462767 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68799116 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49570496 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1364149303 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.icache.replacements 22806 # number of replacements
-system.cpu.icache.tagsinuse 1643.708828 # Cycle average of tags in use
-system.cpu.icache.total_refs 335522072 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24489 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13700.929887 # Average number of references to valid blocks.
+system.cpu.icache.replacements 22544 # number of replacements
+system.cpu.icache.tagsinuse 1643.593682 # Cycle average of tags in use
+system.cpu.icache.total_refs 335759855 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 24228 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 13858.339731 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1643.708828 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.802592 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.802592 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 335526084 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 335526084 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 335526084 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 335526084 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 335526084 # number of overall hits
-system.cpu.icache.overall_hits::total 335526084 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 31612 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 31612 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 31612 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 31612 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 31612 # number of overall misses
-system.cpu.icache.overall_misses::total 31612 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 479792499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 479792499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 479792499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 479792499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 479792499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 479792499 # number of overall miss cycles
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+system.cpu.dcache.ReadReq_accesses::total 695776642 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972718361 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972718361 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972718361 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972718361 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 972712320 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 972712320 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 972712320 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 972712320 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003041 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003041 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34179.513545 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34179.513545 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46830.979061 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46830.979061 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34165.458237 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34165.458237 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46827.311914 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46827.311914 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37990.062107 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37990.062107 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 726 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37979.274551 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37979.274551 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 1535 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 741 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 8.157303 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.425926 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 8.325843 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96323 # number of writebacks
-system.cpu.dcache.writebacks::total 96323 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488688 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 488688 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765077 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 765077 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
+system.cpu.dcache.writebacks::total 96322 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488793 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 488793 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765175 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 765175 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1253765 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1253765 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1253765 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1253765 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464588 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464588 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76810 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76810 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541398 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541398 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541398 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541398 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41111704000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 41111704000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3408970500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3408970500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44520674500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 44520674500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44520674500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 44520674500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 1253968 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1253968 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1253968 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1253968 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464706 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464706 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76852 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76852 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541558 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541558 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541558 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541558 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41088591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 41088591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3410048000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3410048000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44498639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 44498639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44498639000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 44498639000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28070.490814 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28070.490814 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44381.857831 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44381.857831 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28052.449434 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28052.449434 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44371.623380 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44371.623380 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:34:49
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 43266024500 because target called exit()
+Exiting @ tick 42725646500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.042726 # Number of seconds simulated
-sim_ticks 42726055500 # Number of ticks simulated
-final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 42725646500 # Number of ticks simulated
+final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80618 # Simulator instruction rate (inst/s)
-host_op_rate 80618 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38990762 # Simulator tick rate (ticks/s)
-host_mem_usage 257380 # Number of bytes of host memory used
-host_seconds 1095.80 # Real time elapsed on the host
+host_inst_rate 44211 # Simulator instruction rate (inst/s)
+host_op_rate 44211 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21382391 # Simulator tick rate (ticks/s)
+host_mem_usage 280712 # Number of bytes of host memory used
+host_seconds 1998.17 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 165519 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 165514 # Total number of read requests seen
system.physmem.writeReqs 113997 # Total number of write requests seen
-system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 10593216 # Total number of bytes read from memory
+system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10592896 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
-system.physmem.totGap 42726035000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 42725626000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 165519 # Categorize read packet sizes
+system.physmem.readPktSize::6 165514 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
-system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests
-system.physmem.totBusLat 827595000 # Total cycles spent in databus access
-system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
-system.physmem.avgQLat 42616.45 # Average queueing delay per request
-system.physmem.avgBankLat 10669.27 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests
+system.physmem.totBusLat 827570000 # Total cycles spent in databus access
+system.physmem.totBankLat 1763822500 # Total cycles spent in bank access
+system.physmem.avgQLat 42764.74 # Average queueing delay per request
+system.physmem.avgBankLat 10656.64 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58285.72 # Average memory access latency
+system.physmem.avgMemAccLat 58421.38 # Average memory access latency
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.27 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.23 # Average read queue length over time
-system.physmem.avgWrQLen 10.42 # Average write queue length over time
-system.physmem.readRowHits 148856 # Number of row buffer hits during reads
-system.physmem.writeRowHits 71619 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
-system.physmem.avgGap 152857.21 # Average gap between requests
-system.cpu.branchPred.lookups 18742591 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits
+system.physmem.avgWrQLen 10.41 # Average write queue length over time
+system.physmem.readRowHits 148885 # Number of row buffer hits during reads
+system.physmem.writeRowHits 71702 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes
+system.physmem.avgGap 152858.48 # Average gap between requests
+system.cpu.branchPred.lookups 18741806 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20277550 # DTB read hits
+system.cpu.dtb.read_hits 20277542 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20367698 # DTB read accesses
-system.cpu.dtb.write_hits 14728779 # DTB write hits
+system.cpu.dtb.read_accesses 20367690 # DTB read accesses
+system.cpu.dtb.write_hits 14728781 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14736031 # DTB write accesses
-system.cpu.dtb.data_hits 35006329 # DTB hits
+system.cpu.dtb.write_accesses 14736033 # DTB write accesses
+system.cpu.dtb.data_hits 35006323 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 35103729 # DTB accesses
-system.cpu.itb.fetch_hits 12368275 # ITB hits
-system.cpu.itb.fetch_misses 11063 # ITB misses
+system.cpu.dtb.data_accesses 35103723 # DTB accesses
+system.cpu.itb.fetch_hits 12368482 # ITB hits
+system.cpu.itb.fetch_misses 10998 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 12379338 # ITB accesses
+system.cpu.itb.fetch_accesses 12379480 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 85452112 # number of cpu cycles simulated
+system.cpu.numCycles 85451294 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 35060657 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 35060353 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
-system.cpu.activity 81.422683 # Percentage of cycles cpu is active
+system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed.
+system.cpu.activity 81.416087 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
-system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.967293 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.967293 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.033813 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements 84308 # number of replacements
-system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use
-system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
+system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 32800214 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 52651080 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 61.615310 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 42999576 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 42451718 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 49.679433 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 42421796 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 43029498 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 50.355584 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 63338785 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 22112509 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 25.877325 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 39402182 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 46049112 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 53.889309 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 84283 # number of replacements
+system.cpu.icache.tagsinuse 1908.281182 # Cycle average of tags in use
+system.cpu.icache.total_refs 12251335 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 86329 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 141.914478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits
-system.cpu.icache.overall_hits::total 12251160 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
-system.cpu.icache.overall_misses::total 117106 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1908.281182 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.931778 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.931778 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 12251335 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 12251335 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 12251335 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 12251335 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 12251335 # number of overall hits
+system.cpu.icache.overall_hits::total 12251335 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 117137 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 117137 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 117137 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 117137 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 117137 # number of overall misses
+system.cpu.icache.overall_misses::total 117137 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1898913500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:35:07
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:39
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 24414646000 because target called exit()
+Exiting @ tick 23931821000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023888 # Number of seconds simulated
-sim_ticks 23888231000 # Number of ticks simulated
-final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023932 # Number of seconds simulated
+sim_ticks 23931821000 # Number of ticks simulated
+final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 183235 # Simulator instruction rate (inst/s)
-host_op_rate 183235 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54995028 # Simulator tick rate (ticks/s)
-host_mem_usage 260452 # Number of bytes of host memory used
-host_seconds 434.37 # Real time elapsed on the host
+host_inst_rate 61921 # Simulator instruction rate (inst/s)
+host_op_rate 61921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18618559 # Simulator tick rate (ticks/s)
+host_mem_usage 281736 # Number of bytes of host memory used
+host_seconds 1285.37 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10154112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10645056 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 490944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 490944 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7671 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158658 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166329 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 20551710 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 425067557 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 445619267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 20551710 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 20551710 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 305457194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 305457194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 305457194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 20551710 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 425067557 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 751076461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166329 # Total number of read requests seen
-system.physmem.writeReqs 114013 # Total number of write requests seen
-system.physmem.cpureqs 280342 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 10645056 # Total number of bytes read from memory
-system.physmem.bytesWritten 7296832 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 10645056 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7296832 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166313 # Total number of read requests seen
+system.physmem.writeReqs 114015 # Total number of write requests seen
+system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10644032 # Total number of bytes read from memory
+system.physmem.bytesWritten 7296960 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 10521 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10326 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 10267 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 10582 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 10798 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 10408 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 10348 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 10490 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10474 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10565 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 10397 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 10153 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 10116 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7244 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7026 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23888198000 # Total gap between requests
+system.physmem.totGap 23931788000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 166329 # Categorize read packet sizes
+system.physmem.readPktSize::6 166313 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 114013 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 67947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 63103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 27555 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7700 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 114015 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3016 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4341 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4857 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4925 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4946 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1942 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 617 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7273642250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9818352250 # Sum of mem lat for all requests
-system.physmem.totBusLat 831625000 # Total cycles spent in databus access
-system.physmem.totBankLat 1713085000 # Total cycles spent in bank access
-system.physmem.avgQLat 43731.50 # Average queueing delay per request
-system.physmem.avgBankLat 10299.62 # Average bank access latency per request
+system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests
+system.physmem.totBusLat 831555000 # Total cycles spent in databus access
+system.physmem.totBankLat 1715463750 # Total cycles spent in bank access
+system.physmem.avgQLat 43564.80 # Average queueing delay per request
+system.physmem.avgBankLat 10314.79 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 59031.13 # Average memory access latency
-system.physmem.avgRdBW 445.62 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 305.46 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 445.62 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 305.46 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 58879.59 # Average memory access latency
+system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 5.87 # Data bus utilization in percentage
+system.physmem.busUtil 5.86 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.41 # Average read queue length over time
-system.physmem.avgWrQLen 10.09 # Average write queue length over time
-system.physmem.readRowHits 149212 # Number of row buffer hits during reads
-system.physmem.writeRowHits 70966 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.24 # Row buffer hit rate for writes
-system.physmem.avgGap 85210.91 # Average gap between requests
-system.cpu.branchPred.lookups 16542734 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10685518 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 416834 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11542683 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7340422 # Number of BTB hits
+system.physmem.avgWrQLen 9.84 # Average write queue length over time
+system.physmem.readRowHits 149147 # Number of row buffer hits during reads
+system.physmem.writeRowHits 70867 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes
+system.physmem.avgGap 85370.67 # Average gap between requests
+system.cpu.branchPred.lookups 16571170 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 63.593724 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1986948 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 41598 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22395624 # DTB read hits
-system.cpu.dtb.read_misses 219289 # DTB read misses
-system.cpu.dtb.read_acv 61 # DTB read access violations
-system.cpu.dtb.read_accesses 22614913 # DTB read accesses
-system.cpu.dtb.write_hits 15707380 # DTB write hits
-system.cpu.dtb.write_misses 41224 # DTB write misses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_accesses 15748604 # DTB write accesses
-system.cpu.dtb.data_hits 38103004 # DTB hits
-system.cpu.dtb.data_misses 260513 # DTB misses
-system.cpu.dtb.data_acv 62 # DTB access violations
-system.cpu.dtb.data_accesses 38363517 # DTB accesses
-system.cpu.itb.fetch_hits 13912342 # ITB hits
-system.cpu.itb.fetch_misses 34675 # ITB misses
+system.cpu.dtb.read_hits 22414538 # DTB read hits
+system.cpu.dtb.read_misses 219003 # DTB read misses
+system.cpu.dtb.read_acv 44 # DTB read access violations
+system.cpu.dtb.read_accesses 22633541 # DTB read accesses
+system.cpu.dtb.write_hits 15711620 # DTB write hits
+system.cpu.dtb.write_misses 41172 # DTB write misses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_accesses 15752792 # DTB write accesses
+system.cpu.dtb.data_hits 38126158 # DTB hits
+system.cpu.dtb.data_misses 260175 # DTB misses
+system.cpu.dtb.data_acv 46 # DTB access violations
+system.cpu.dtb.data_accesses 38386333 # DTB accesses
+system.cpu.itb.fetch_hits 13959521 # ITB hits
+system.cpu.itb.fetch_misses 35718 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13947017 # ITB accesses
+system.cpu.itb.fetch_accesses 13995239 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 47776465 # number of cpu cycles simulated
+system.cpu.numCycles 47863646 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15792140 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 105356372 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16542734 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9327370 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 19544101 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1999173 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 6408053 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 7580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 309115 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13912342 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 209427 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 43512690 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.421279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.137905 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total)
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+system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23968589 55.08% 55.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1529417 3.51% 58.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1370330 3.15% 61.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1513065 3.48% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4135878 9.50% 74.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1846880 4.24% 78.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 674126 1.55% 80.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1070808 2.46% 82.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7403597 17.01% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43512690 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.346253 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.205194 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16866618 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5950644 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18537765 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 810794 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1346869 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3745393 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 107096 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 103623154 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 304519 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1346869 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 17322284 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3660735 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 85948 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18844978 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2251876 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102372237 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 493 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2125269 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 61644392 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 123362389 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 122911717 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 450672 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename
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+system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed
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+system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups
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system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9097511 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5543 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5541 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 4645908 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23234130 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16272775 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1204976 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 463178 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 90743430 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5284 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 88424765 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 96747 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10698511 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4674782 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed
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-system.cpu.iq.issued_per_cycle::stdev 2.108847 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing
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+system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer
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+system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued
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+system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::3 4759728 10.94% 74.77% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::5 2652660 6.10% 91.62% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::7 1300380 2.99% 99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 414364 0.95% 100.00% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 785994 42.27% 49.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 947743 50.97% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.FU_type_0::IntMult 43912 0.05% 55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121242 0.14% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 121107 0.14% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 38943 0.04% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 22848081 25.84% 82.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 88424765 # Type of FU issued
-system.cpu.iq.rate 1.850802 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1859292 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.021027 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 221714954 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 101050466 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86544122 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 603305 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 414877 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 294005 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 89982323 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 301734 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1469012 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued
+system.cpu.iq.rate 1.849142 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2957492 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4689 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18546 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1659398 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2825 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 92449 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1346869 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2686448 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 74137 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100230193 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 219543 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23234130 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16272775 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5284 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 60080 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 507 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18546 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 196235 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 160668 # Number of branches that were predicted not taken incorrectly
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-system.cpu.iew.iewExecutedInsts 87583307 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22618160 # Number of load instructions executed
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+system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::0 19296165 45.76% 45.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7025692 16.66% 62.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3426859 8.13% 70.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2055479 4.87% 75.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2052042 4.87% 80.29% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::6 1093221 2.59% 85.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 720657 1.71% 87.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5334734 12.65% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.rob.rob_writes 195808907 # The number of ROB writes
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-system.cpu.idleCycles 4263775 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.600269 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.600269 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.665920 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.665920 # IPC: Total IPC of All Threads
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+system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_reads 38020 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]
hack: be nice to actually delete the event here
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:21:53
-gem5 started Mar 4 2013 01:35:26
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 02:50:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 25578307500 because target called exit()
+Exiting @ tick 25534556000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.025579 # Number of seconds simulated
-sim_ticks 25578679000 # Number of ticks simulated
-final_tick 25578679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.025535 # Number of seconds simulated
+sim_ticks 25534556000 # Number of ticks simulated
+final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 106593 # Simulator instruction rate (inst/s)
-host_op_rate 151269 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38451628 # Simulator tick rate (ticks/s)
-host_mem_usage 298528 # Number of bytes of host memory used
-host_seconds 665.22 # Real time elapsed on the host
+host_inst_rate 42425 # Simulator instruction rate (inst/s)
+host_op_rate 60207 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15277801 # Simulator tick rate (ticks/s)
+host_mem_usage 296924 # Number of bytes of host memory used
+host_seconds 1671.35 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11654707 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 310553645 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 322208352 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11654707 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11654707 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 210029924 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 210029924 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 210029924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11654707 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 310553645 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 532238275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128777 # Total number of read requests seen
-system.physmem.writeReqs 83942 # Total number of write requests seen
-system.physmem.cpureqs 213038 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 8241664 # Total number of bytes read from memory
-system.physmem.bytesWritten 5372288 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 311085260 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 322737548 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 311085260 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 533137917 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128766 # Total number of read requests seen
+system.physmem.writeReqs 83945 # Total number of write requests seen
+system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 8240960 # Total number of bytes read from memory
+system.physmem.bytesWritten 5372480 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 8240960 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 8192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 8047 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 7986 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 7948 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 25578660500 # Total gap between requests
+system.physmem.totGap 25534539500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 128777 # Categorize read packet sizes
+system.physmem.readPktSize::6 128766 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 83942 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 70048 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56559 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2088 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 83945 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 70151 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3210060500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 5252104250 # Sum of mem lat for all requests
-system.physmem.totBusLat 643875000 # Total cycles spent in databus access
-system.physmem.totBankLat 1398168750 # Total cycles spent in bank access
-system.physmem.avgQLat 24927.67 # Average queueing delay per request
-system.physmem.avgBankLat 10857.45 # Average bank access latency per request
+system.physmem.totQLat 3209266500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 5253345250 # Sum of mem lat for all requests
+system.physmem.totBusLat 643820000 # Total cycles spent in databus access
+system.physmem.totBankLat 1400258750 # Total cycles spent in bank access
+system.physmem.avgQLat 24923.63 # Average queueing delay per request
+system.physmem.avgBankLat 10874.61 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40785.12 # Average memory access latency
-system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 40798.25 # Average memory access latency
+system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 4.16 # Data bus utilization in percentage
+system.physmem.busUtil 4.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.21 # Average read queue length over time
-system.physmem.avgWrQLen 9.59 # Average write queue length over time
-system.physmem.readRowHits 116755 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52878 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes
-system.physmem.avgGap 120246.24 # Average gap between requests
-system.cpu.branchPred.lookups 16623550 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12760225 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 602776 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10462790 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7764993 # Number of BTB hits
+system.physmem.avgWrQLen 9.90 # Average write queue length over time
+system.physmem.readRowHits 116738 # Number of row buffer hits during reads
+system.physmem.writeRowHits 52892 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes
+system.physmem.avgGap 120043.34 # Average gap between requests
+system.cpu.branchPred.lookups 16612549 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 74.215319 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1825730 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 51157359 # number of cpu cycles simulated
+system.cpu.numCycles 51069113 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12528196 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 85178151 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16623550 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9590723 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21186766 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2362966 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10580824 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 65 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 592 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11675240 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 179625 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46030286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.591135 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.335079 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12514698 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 10532726 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24863758 54.02% 54.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2136664 4.64% 58.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1964751 4.27% 62.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2042058 4.44% 67.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1465237 3.18% 70.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1378794 3.00% 73.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 958007 2.08% 75.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1192757 2.59% 78.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10028260 21.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46030286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.324949 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.665022 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14611843 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8929429 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19464778 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1393400 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1630836 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3329843 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 104767 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116826409 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 364015 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1630836 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16323672 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2560343 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 881200 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19095931 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5538304 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 114955778 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 16357 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4684077 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115266627 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529628092 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529622760 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14598305 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8880724 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16304725 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 873067 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16133955 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20202 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20198 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13085199 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29620303 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22433978 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3897320 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4410132 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111515414 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 35833 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107233709 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 271611 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10777789 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 25822592 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2047 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46030286 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.329634 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.987559 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit.
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+system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 107205683 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 272681 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 25689486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed
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+system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 8089494 17.57% 40.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7436899 16.16% 57.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7132502 15.50% 72.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5411548 11.76% 84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3908660 8.49% 92.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1839023 4.00% 96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 868143 1.89% 98.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 571535 1.24% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10727081 23.35% 23.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8071190 17.57% 40.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7423915 16.16% 57.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5405073 11.76% 84.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3914653 8.52% 92.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1842463 4.01% 96.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 872331 1.90% 98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 570973 1.24% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46030286 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 112260 4.55% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1357456 55.03% 59.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 996870 40.41% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1365116 55.14% 59.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 998484 40.33% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56624482 52.80% 52.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91603 0.09% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 56613299 52.81% 52.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28897893 26.95% 79.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21619537 20.16% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107233709 # Type of FU issued
-system.cpu.iq.rate 2.096154 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2466586 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023002 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263235386 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 122356888 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105553525 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109700035 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2179098 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 107205683 # Type of FU issued
+system.cpu.iq.rate 2.099227 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2475632 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263108179 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 105531184 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 109681022 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2313195 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6752 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29821 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1878240 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 512 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1630836 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1047773 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 45606 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 111560996 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 293586 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29620303 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22433978 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19913 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6800 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5244 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29821 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 391475 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 181717 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 573192 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106207305 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28598865 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1026404 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 106181677 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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-system.cpu.iew.exec_refs 49933799 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14599943 # Number of branches executed
-system.cpu.iew.exec_stores 21334934 # Number of stores executed
-system.cpu.iew.exec_rate 2.076090 # Inst execution rate
-system.cpu.iew.wb_sent 105772568 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105553695 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53290851 # num instructions producing a value
-system.cpu.iew.wb_consumers 103571318 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.063314 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::1 11640372 26.22% 60.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3466304 7.81% 68.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2879944 6.49% 75.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1880994 4.24% 79.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1947998 4.39% 83.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 685125 1.54% 85.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 565076 1.27% 86.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6011171 13.54% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::2 3461272 7.81% 68.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2876318 6.49% 74.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1875937 4.23% 79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1955484 4.41% 83.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6011171 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6014208 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.rob.rob_writes 224763597 # The number of ROB writes
-system.cpu.timesIdled 74024 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5127073 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 149798719 # The number of ROB reads
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+system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
-system.cpu.cpi 0.721465 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.721465 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.386069 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.386069 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511541679 # number of integer regfile reads
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+system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.overall_mshr_misses::total 162751 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878666500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878666500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6813869491 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6813869491 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8692535991 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8692535991 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8692535991 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8692535991 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33900.544959 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33900.544959 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63482.861824 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63482.861824 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks
+system.cpu.dcache.writebacks::total 129075 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55396 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55396 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162738 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162738 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162738 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162738 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878391000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878391000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809216990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809216990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687607990 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8687607990 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687607990 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8687607990 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33908.422991 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33908.422991 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.787781 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.787781 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:25
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 985089830500 because target called exit()
+Exiting @ tick 993429839500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.993559 # Number of seconds simulated
-sim_ticks 993559170500 # Number of ticks simulated
-final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.993430 # Number of seconds simulated
+sim_ticks 993429839500 # Number of ticks simulated
+final_tick 993429839500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 90803 # Simulator instruction rate (inst/s)
-host_op_rate 90803 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49576515 # Simulator tick rate (ticks/s)
-host_mem_usage 449304 # Number of bytes of host memory used
-host_seconds 20040.92 # Real time elapsed on the host
+host_inst_rate 61068 # Simulator instruction rate (inst/s)
+host_op_rate 61068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33337374 # Simulator tick rate (ticks/s)
+host_mem_usage 271484 # Number of bytes of host memory used
+host_seconds 29799.28 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 55340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 126194172 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 126249512 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 55340 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 55340 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 65586498 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 65586498 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 65586498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 55340 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 126194172 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 191836009 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1959688 # Total number of read requests seen
-system.physmem.writeReqs 1018058 # Total number of write requests seen
-system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady
+system.physmem.writeReqs 1018056 # Total number of write requests seen
+system.physmem.cpureqs 2977747 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 125420032 # Total number of bytes read from memory
-system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
+system.physmem.bytesWritten 65155584 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q
+system.physmem.bytesConsumedWr 65155584 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 583 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 122178 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 121799 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 121645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 123762 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 123293 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 122178 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 121053 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 121197 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 121887 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 121114 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 125176 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 123788 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 122723 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 123934 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 63646 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64277 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
-system.physmem.totGap 993559118500 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
+system.physmem.totGap 993429787500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1018056 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1630073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 205372 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 87756 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 35903 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 41526 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 44237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 44257 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 44260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 44261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 44261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 44260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 44260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
-system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
-system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
-system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
-system.physmem.avgQLat 18295.82 # Average queueing delay per request
-system.physmem.avgBankLat 29934.69 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 2738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 503 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
+system.physmem.totQLat 35756114000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 104195196500 # Sum of mem lat for all requests
+system.physmem.totBusLat 9795525000 # Total cycles spent in databus access
+system.physmem.totBankLat 58643557500 # Total cycles spent in bank access
+system.physmem.avgQLat 18251.25 # Average queueing delay per request
+system.physmem.avgBankLat 29933.85 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 53230.51 # Average memory access latency
-system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 53185.10 # Average memory access latency
+system.physmem.avgRdBW 126.25 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 65.59 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 126.25 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 65.59 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
-system.physmem.avgWrQLen 10.46 # Average write queue length over time
-system.physmem.readRowHits 770937 # Number of row buffer hits during reads
-system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 10.25 # Average write queue length over time
+system.physmem.readRowHits 770910 # Number of row buffer hits during reads
+system.physmem.writeRowHits 285915 # Number of row buffer hits during writes
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
-system.physmem.avgGap 333661.47 # Average gap between requests
-system.cpu.branchPred.lookups 326540496 # Number of BP lookups
-system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
+system.physmem.writeRowHitRate 28.08 # Row buffer hit rate for writes
+system.physmem.avgGap 333618.27 # Average gap between requests
+system.cpu.branchPred.lookups 326686623 # Number of BP lookups
+system.cpu.branchPred.condPredicted 252728421 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 138236618 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 220072192 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 135769528 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 61.693177 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444796009 # DTB read hits
+system.cpu.dtb.read_hits 444795652 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449693087 # DTB read accesses
-system.cpu.dtb.write_hits 160833358 # DTB write hits
+system.cpu.dtb.read_accesses 449692730 # DTB read accesses
+system.cpu.dtb.write_hits 160833314 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162534662 # DTB write accesses
-system.cpu.dtb.data_hits 605629367 # DTB hits
+system.cpu.dtb.write_accesses 162534618 # DTB write accesses
+system.cpu.dtb.data_hits 605628966 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612227749 # DTB accesses
-system.cpu.itb.fetch_hits 232025963 # ITB hits
+system.cpu.dtb.data_accesses 612227348 # DTB accesses
+system.cpu.itb.fetch_hits 231949721 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 232025985 # ITB accesses
+system.cpu.itb.fetch_accesses 231949743 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1987118342 # number of cpu cycles simulated
+system.cpu.numCycles 1986859680 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 172586758 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 154099865 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1667601840 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 3043804457 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617884569 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 651738878 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617884917 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 120537665 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 11100495 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 131638160 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 83561944 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 61.170119 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1139346059 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1741702087 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
-system.cpu.activity 79.100705 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7484450 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 415164157 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1571695523 # Number of cycles cpu stages are processed.
+system.cpu.activity 79.104505 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
-system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 1.091813 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 1.091813 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.915908 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.915908 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 800109422 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1186750258 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 59.729948 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1053226597 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 933633083 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 46.990389 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 1014475629 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 972384051 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 48.940751 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1577240024 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409619656 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.616436 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 965534852 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1021324828 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 51.403974 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
-system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 667.831181 # Cycle average of tags in use
+system.cpu.icache.total_refs 231948615 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 270021.670547 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits
-system.cpu.icache.overall_hits::total 232024854 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
-system.cpu.icache.overall_misses::total 1109 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 667.831181 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.326089 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.326089 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 231948615 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 231948615 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 231948615 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 231948615 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 231948615 # number of overall hits
+system.cpu.icache.overall_hits::total 231948615 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1106 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1106 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1106 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1106 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1106 # number of overall misses
+system.cpu.icache.overall_misses::total 1106 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 62073500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 62073500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 62073500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 62073500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 62073500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 62073500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 231949721 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 231949721 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 231949721 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 231949721 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 231949721 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 231949721 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56124.321881 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56124.321881 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56124.321881 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56124.321881 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 247 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 247 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 247 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 247 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 247 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 247 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51214500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 51214500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51214500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 51214500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51214500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 51214500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
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-system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 156243796 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 156243796 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 593512555 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 593512555 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 593512555 # number of overall hits
+system.cpu.dcache.overall_hits::total 593512555 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 4484706 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 4484706 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 11811610 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 11811610 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 11811610 # number of overall misses
+system.cpu.dcache.overall_misses::total 11811610 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 167226851000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 167226851000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 202255523500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 202255523500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 369482374500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 369482374500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 369482374500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 369482374500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027902 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.027902 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.019513 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.019513 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.019513 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.019513 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22823.671635 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22823.671635 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45098.948181 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45098.948181 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31281.288029 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31281.288029 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13468960 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4773919 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 372025 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65739 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.204449 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 72.619282 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
-system.cpu.dcache.writebacks::total 3693293 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 3693289 # number of writebacks
+system.cpu.dcache.writebacks::total 3693289 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595524 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2595524 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2700148 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2700148 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2700148 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2700148 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150904604500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 150904604500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79287604500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 79287604500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230192209000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 230192209000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230192209000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230192209000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20894.316545 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20894.316545 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41969.277973 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41969.277973 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:57:42
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:58:12
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 655919824500 because target called exit()
+Exiting @ tick 665534636500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.665696 # Number of seconds simulated
-sim_ticks 665695988500 # Number of ticks simulated
-final_tick 665695988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.665535 # Number of seconds simulated
+sim_ticks 665534636500 # Number of ticks simulated
+final_tick 665534636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 147850 # Simulator instruction rate (inst/s)
-host_op_rate 147850 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56693787 # Simulator tick rate (ticks/s)
-host_mem_usage 452372 # Number of bytes of host memory used
-host_seconds 11741.96 # Real time elapsed on the host
+host_inst_rate 68112 # Simulator instruction rate (inst/s)
+host_op_rate 68112 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26111525 # Simulator tick rate (ticks/s)
+host_mem_usage 272636 # Number of bytes of host memory used
+host_seconds 25488.16 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125794176 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125855680 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65263360 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65263360 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1965534 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1966495 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1019740 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1019740 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92391 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 188966402 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 189058793 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92391 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92391 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 98037785 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 98037785 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 98037785 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 188966402 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 287096578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1966495 # Total number of read requests seen
-system.physmem.writeReqs 1019740 # Total number of write requests seen
-system.physmem.cpureqs 2986251 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 125855680 # Total number of bytes read from memory
-system.physmem.bytesWritten 65263360 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 125855680 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65263360 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 570 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 62080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125797184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125859264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 62080 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 62080 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65262656 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65262656 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 970 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965581 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1966551 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1019729 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1019729 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 93278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 189016735 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 189110013 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 93278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 93278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 98060495 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 98060495 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 98060495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 93278 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 189016735 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 287170509 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1966551 # Total number of read requests seen
+system.physmem.writeReqs 1019729 # Total number of write requests seen
+system.physmem.cpureqs 2986294 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 125859264 # Total number of bytes read from memory
+system.physmem.bytesWritten 65262656 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 125859264 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 65262656 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 565 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122637 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 122329 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 122200 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 124178 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123636 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122601 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121425 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 121612 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 122670 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 122308 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 124219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 123641 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 122574 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 120687 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 121413 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 121604 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 123448 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125589 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 124287 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 123163 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 124393 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 63486 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 62408 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 63108 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 63839 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 64141 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 63880 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::10 121464 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 123454 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 125591 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 124312 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 123151 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 124443 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 63482 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 62396 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 63113 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 63858 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 63872 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 63456 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 63488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 63819 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 64238 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 64665 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 64277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64358 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 63448 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 63476 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 63820 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 63370 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 64242 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 64662 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 64289 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 63740 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64359 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry
-system.physmem.totGap 665695920000 # Total gap between requests
+system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
+system.physmem.totGap 665534568000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 1966495 # Categorize read packet sizes
+system.physmem.readPktSize::6 1966551 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1019740 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1625686 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 234777 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 77588 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 27855 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1019729 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1625924 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 234682 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 77512 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 27850 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 42341 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44298 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43951 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 44243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 44297 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 44314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 44319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 44321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1996 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 382 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2055 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 385 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
-system.physmem.totQLat 34438847000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102566423250 # Sum of mem lat for all requests
-system.physmem.totBusLat 9829625000 # Total cycles spent in databus access
-system.physmem.totBankLat 58297951250 # Total cycles spent in bank access
-system.physmem.avgQLat 17517.88 # Average queueing delay per request
-system.physmem.avgBankLat 29654.21 # Average bank access latency per request
+system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
+system.physmem.totQLat 34329674750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 102455589750 # Sum of mem lat for all requests
+system.physmem.totBusLat 9829930000 # Total cycles spent in databus access
+system.physmem.totBankLat 58295985000 # Total cycles spent in bank access
+system.physmem.avgQLat 17461.81 # Average queueing delay per request
+system.physmem.avgBankLat 29652.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52172.09 # Average memory access latency
-system.physmem.avgRdBW 189.06 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 98.04 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 189.06 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 98.04 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 52114.10 # Average memory access latency
+system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.24 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 10.61 # Average write queue length over time
-system.physmem.readRowHits 776012 # Number of row buffer hits during reads
-system.physmem.writeRowHits 286087 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.05 # Row buffer hit rate for writes
-system.physmem.avgGap 222921.48 # Average gap between requests
-system.cpu.branchPred.lookups 381386947 # Number of BP lookups
-system.cpu.branchPred.condPredicted 296385810 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16088637 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 262415494 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 259543645 # Number of BTB hits
+system.physmem.avgWrQLen 10.52 # Average write queue length over time
+system.physmem.readRowHits 776084 # Number of row buffer hits during reads
+system.physmem.writeRowHits 286116 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 39.48 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
+system.physmem.avgGap 222864.09 # Average gap between requests
+system.cpu.branchPred.lookups 381314788 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296330051 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16069549 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 262009169 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259516575 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.905610 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 24703591 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3035 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.048662 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24704658 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2987 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613791968 # DTB read hits
-system.cpu.dtb.read_misses 11248781 # DTB read misses
+system.cpu.dtb.read_hits 613784934 # DTB read hits
+system.cpu.dtb.read_misses 11255491 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 625040749 # DTB read accesses
-system.cpu.dtb.write_hits 212266069 # DTB write hits
-system.cpu.dtb.write_misses 7139950 # DTB write misses
+system.cpu.dtb.read_accesses 625040425 # DTB read accesses
+system.cpu.dtb.write_hits 212268072 # DTB write hits
+system.cpu.dtb.write_misses 7147147 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 219406019 # DTB write accesses
-system.cpu.dtb.data_hits 826058037 # DTB hits
-system.cpu.dtb.data_misses 18388731 # DTB misses
+system.cpu.dtb.write_accesses 219415219 # DTB write accesses
+system.cpu.dtb.data_hits 826053006 # DTB hits
+system.cpu.dtb.data_misses 18402638 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 844446768 # DTB accesses
-system.cpu.itb.fetch_hits 390789739 # ITB hits
+system.cpu.dtb.data_accesses 844455644 # DTB accesses
+system.cpu.itb.fetch_hits 390718533 # ITB hits
system.cpu.itb.fetch_misses 44 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 390789783 # ITB accesses
+system.cpu.itb.fetch_accesses 390718577 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1331391978 # number of cpu cycles simulated
+system.cpu.numCycles 1331069274 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 402247693 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3159701831 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381386947 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 284247236 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 574240478 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 140323731 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 173777898 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1315 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 390789739 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8060023 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1266766339 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.494305 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152696 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 402166078 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3159376011 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 381314788 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 284221233 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 574162316 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 140275246 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 173581201 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1319 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 390718533 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8058234 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1266376452 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.494816 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.152860 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 692525861 54.67% 54.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42625697 3.36% 58.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21759185 1.72% 59.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 39691714 3.13% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129252182 10.20% 73.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 61534262 4.86% 77.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38544537 3.04% 80.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28127846 2.22% 83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 212705055 16.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 692214136 54.66% 54.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42617572 3.37% 58.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21747694 1.72% 59.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 39672890 3.13% 62.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129244053 10.21% 73.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 61517613 4.86% 77.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38549434 3.04% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28120980 2.22% 83.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 212692080 16.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1266766339 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.286457 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.373232 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 433937783 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 155286584 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542483654 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 18560300 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 116498018 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 58313191 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3087105649 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2059 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 116498018 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 456816204 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 101540810 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 6220 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 535489445 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 56415642 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3005086963 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 566623 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1738834 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 50324811 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2246778226 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3897347889 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3896105158 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1242731 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1266376452 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.286473 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.373562 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 433844233 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 155093027 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 542385824 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 18588672 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 116464696 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 58295749 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 820 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3086840549 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2050 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 116464696 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 456708081 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 101341646 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 4855 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 535414758 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 56442416 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3004830564 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 566431 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1735808 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 50354826 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2246618583 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3897053047 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3895813174 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1239873 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 870575263 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 167 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 121265991 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 679360736 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 255356957 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68007624 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 36872048 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2723554804 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 129 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2508984537 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3092752 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 978311226 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 415025058 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 100 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1266766339 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.980621 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.972970 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 870415620 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 152 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 150 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 121369541 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 679327249 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 255330910 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 67787749 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 36895317 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2723405811 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 116 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2508867042 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3090361 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 978262694 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 414978517 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 87 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1266376452 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.981138 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.973034 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 426534847 33.67% 33.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 201890440 15.94% 49.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 185333352 14.63% 64.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153215856 12.10% 76.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 133163574 10.51% 86.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 81070069 6.40% 93.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 65235911 5.15% 98.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 15218602 1.20% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5103688 0.40% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 426237987 33.66% 33.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 201818534 15.94% 49.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 185298881 14.63% 64.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153239824 12.10% 76.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 133194400 10.52% 86.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 81007004 6.40% 93.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 65236623 5.15% 98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 15246676 1.20% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5096523 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1266766339 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1266376452 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2143232 11.63% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11878025 64.46% 76.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4404432 23.90% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2152645 11.65% 11.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11915798 64.49% 76.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4409146 23.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1643533281 65.51% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 268 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 192 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 641423714 25.57% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 224026917 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1643427997 65.50% 65.50% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 257 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 24 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 641412571 25.57% 91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 224025892 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2508984537 # Type of FU issued
-system.cpu.iq.rate 1.884482 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18425689 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007344 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6304354052 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3700755338 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2412575558 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1899802 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1217218 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 851053 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2526471243 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 938983 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62590757 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2508867042 # Type of FU issued
+system.cpu.iq.rate 1.884851 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18477589 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007365 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6303778600 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3700560143 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2412458758 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1899886 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1215836 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 851322 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2526405516 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 939115 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62596425 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 234765073 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 264281 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 108176 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94628455 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 234731586 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 264011 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 109067 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 94602408 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 156 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1505453 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 66 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1508918 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 116498018 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 45291754 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1153048 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2865571059 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8871235 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 679360736 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 255356957 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 129 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 296395 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17051 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 108176 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10360108 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8562955 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18923063 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2461579211 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 625041270 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 47405326 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 116464696 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 45220798 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1155063 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2865407567 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewDispLoadInsts 679327249 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 255330910 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 116 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 297140 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 16951 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 109067 # Number of memory order violations
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+system.cpu.iew.branchMispredicts 18902653 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2461486866 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142016126 # number of nop insts executed
-system.cpu.iew.exec_refs 844447329 # number of memory reference insts executed
-system.cpu.iew.exec_branches 300798489 # Number of branches executed
-system.cpu.iew.exec_stores 219406059 # Number of stores executed
-system.cpu.iew.exec_rate 1.848876 # Inst execution rate
-system.cpu.iew.wb_sent 2441376362 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2413426611 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1388583006 # num instructions producing a value
-system.cpu.iew.wb_consumers 1764301470 # num instructions consuming a value
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+system.cpu.iew.wb_sent 2441275432 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2413310080 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1388594213 # num instructions producing a value
+system.cpu.iew.wb_consumers 1764461796 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.812709 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.787044 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.813061 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.786979 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 824638318 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16087839 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1150268321 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.582048 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.512804 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16068781 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.582539 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 636823398 55.36% 55.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174498580 15.17% 70.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86188355 7.49% 78.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53663047 4.67% 82.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34548846 3.00% 85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25343487 2.20% 87.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 21850232 1.90% 89.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22917524 1.99% 91.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 94434852 8.21% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 636560643 55.36% 55.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174447924 15.17% 70.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 86151555 7.49% 78.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53744022 4.67% 82.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 34427444 2.99% 85.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25274936 2.20% 87.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 21893247 1.90% 89.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22942792 2.00% 91.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 94469193 8.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::total 1149911756 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 94434852 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 94469193 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3614472713 # The number of ROB reads
-system.cpu.rob.rob_writes 5405435258 # The number of ROB writes
-system.cpu.timesIdled 818038 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64625639 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3613950126 # The number of ROB reads
+system.cpu.rob.rob_writes 5405135678 # The number of ROB writes
+system.cpu.timesIdled 818095 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 64692822 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.766912 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.766912 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.303931 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.303931 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3317336179 # number of integer regfile reads
-system.cpu.int_regfile_writes 1931663734 # number of integer regfile writes
-system.cpu.fp_regfile_reads 30582 # number of floating regfile reads
-system.cpu.fp_regfile_writes 562 # number of floating regfile writes
+system.cpu.cpi 0.766726 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.766726 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.304248 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.304248 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3317233936 # number of integer regfile reads
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+system.cpu.fp_regfile_reads 30073 # number of floating regfile reads
+system.cpu.fp_regfile_writes 508 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 772.833210 # Cycle average of tags in use
-system.cpu.icache.total_refs 390788277 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 406647.530697 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 775.031780 # Cycle average of tags in use
+system.cpu.icache.total_refs 390717051 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 402801.083505 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 772.833210 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.377360 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.377360 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 390788277 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 390788277 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 390788277 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 390788277 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1461 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1461 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1461 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1461 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1461 # number of overall misses
-system.cpu.icache.overall_misses::total 1461 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 84586499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 84586499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 84586499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 84586499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 84586499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 84586499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 390789738 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 390789738 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 390789738 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 390789738 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 390789738 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 775.031780 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.378433 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.378433 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 390717051 # number of ReadReq hits
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+system.cpu.icache.overall_hits::total 390717051 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses
+system.cpu.icache.overall_misses::total 1482 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 88954499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 88954499 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total 88954499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 390718533 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57896.303217 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 57896.303217 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 57896.303217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 57896.303217 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1190 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60023.278677 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 60023.278677 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 60023.278677 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 60023.278677 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 60023.278677 # average overall miss latency
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+system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 238 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 288 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 500 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 500 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 500 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 500 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 500 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59834499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 59834499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59834499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 59834499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59834499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 59834499 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 512 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62262.746098 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62262.746098 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62262.746098 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62262.746098 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62262.746098 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62262.746098 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62519.586598 # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62519.586598 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 62519.586598 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62519.586598 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 62519.586598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 1933792 # number of replacements
-system.cpu.l2cache.tagsinuse 31417.715901 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9058149 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 1963570 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 4.613102 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 1933850 # number of replacements
+system.cpu.l2cache.tagsinuse 31417.586282 # Cycle average of tags in use
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62909.582587 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9176040 # number of replacements
-system.cpu.dcache.tagsinuse 4087.524129 # Cycle average of tags in use
-system.cpu.dcache.total_refs 694346796 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9180136 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 75.635785 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 9176393 # number of replacements
+system.cpu.dcache.tagsinuse 4087.522074 # Cycle average of tags in use
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+system.cpu.dcache.avg_refs 75.631028 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.524129 # Average occupied blocks per requestor
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-system.cpu.dcache.occ_percent::total 0.997931 # Average percentage of cache occupancy
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-system.cpu.dcache.ReadReq_hits::total 538700284 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 155646508 # number of WriteReq hits
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-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
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-system.cpu.dcache.ReadReq_misses::cpu.data 11280990 # number of ReadReq misses
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+system.cpu.dcache.occ_blocks::cpu.data 4087.522074 # Average occupied blocks per requestor
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system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.913100 # average ReadReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 31732.644407 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31732.644407 # average overall miss latency
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-system.cpu.dcache.blocked_cycles::no_targets 5806156 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 735074 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.660859 # average number of cycles each access was blocked
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+system.cpu.dcache.demand_avg_miss_latency::total 31732.303366 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.303366 # average overall miss latency
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.659195 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 89.273440 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3724734 # number of writebacks
-system.cpu.dcache.writebacks::total 3724734 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3984427 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3984427 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883572 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1883572 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 3725155 # number of writebacks
+system.cpu.dcache.writebacks::total 3725155 # number of writebacks
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system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 159317479500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 230821736901 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230821736901 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230821736901 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.demand_mshr_miss_latency::total 230721382950 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230721382950 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230721382950 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21834.592465 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21834.592465 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37962.051571 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37962.051571 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
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+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.012918 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.422969 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.422969 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37940.280442 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37940.280442 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 3 2013 21:21:53
-gem5 started Mar 4 2013 01:41:28
-gem5 executing on zizzer
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 01:49:26
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 517371024000 because target called exit()
+Exiting @ tick 517355353500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517386 # Number of seconds simulated
-sim_ticks 517386284000 # Number of ticks simulated
-final_tick 517386284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.517355 # Number of seconds simulated
+sim_ticks 517355353500 # Number of ticks simulated
+final_tick 517355353500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 116249 # Simulator instruction rate (inst/s)
-host_op_rate 129685 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38940374 # Simulator tick rate (ticks/s)
-host_mem_usage 515484 # Number of bytes of host memory used
-host_seconds 13286.63 # Real time elapsed on the host
+host_inst_rate 80961 # Simulator instruction rate (inst/s)
+host_op_rate 90318 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27118174 # Simulator tick rate (ticks/s)
+host_mem_usage 288124 # Number of bytes of host memory used
+host_seconds 19077.81 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143753728 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143802048 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70452928 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70452928 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2246152 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246907 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100827 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100827 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 93393 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 277846036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 277939428 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 93393 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 93393 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 136170846 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 136170846 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 136170846 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 93393 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 277846036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 414110274 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246907 # Total number of read requests seen
-system.physmem.writeReqs 1100827 # Total number of write requests seen
-system.physmem.cpureqs 3347751 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143802048 # Total number of bytes read from memory
-system.physmem.bytesWritten 70452928 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143802048 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70452928 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 626 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143726656 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143774272 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70431232 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70431232 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2245729 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2246473 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100488 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100488 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 92037 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 277810319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 277902357 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 92037 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 92037 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 136137051 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 136137051 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 136137051 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 92037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 277810319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 414039407 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2246473 # Total number of read requests seen
+system.physmem.writeReqs 1100488 # Total number of write requests seen
+system.physmem.cpureqs 3346979 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143774272 # Total number of bytes read from memory
+system.physmem.bytesWritten 70431232 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143774272 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70431232 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 670 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 141345 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 139694 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141615 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 141701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 142344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 140081 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141241 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 140671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 138680 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 136252 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140704 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140722 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 141030 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 139261 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 139241 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 141699 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69025 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 68435 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69163 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 69463 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 69359 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 68971 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 69032 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68404 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 67870 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 66992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 69579 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 69317 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 69127 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 68645 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 68513 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68932 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 141489 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 139656 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 141525 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 141936 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 142251 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 140152 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 141094 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 140745 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 138661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 136342 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 140561 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 140724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 141098 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 138976 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 138964 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 141629 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69092 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 68439 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 69113 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 69523 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 69288 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 69039 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 68977 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68383 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 67923 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 67021 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 69461 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 69311 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 69094 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 68543 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 68433 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 68848 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 17 # Number of times wr buffer was full causing retry
-system.physmem.totGap 517386204500 # Total gap between requests
+system.physmem.numWrRetry 18 # Number of times wr buffer was full causing retry
+system.physmem.totGap 517355284500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246907 # Categorize read packet sizes
+system.physmem.readPktSize::6 2246473 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1100827 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1563682 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 451240 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 162530 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68808 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1100488 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1563773 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 450876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 162701 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 68433 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 44008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 47105 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 47731 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 47807 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 47830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 47841 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 47842 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 47862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3855 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 757 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 44051 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 47144 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 47800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 47824 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 47829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 47830 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 47829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 47829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 47847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3797 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 704 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 118 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 48 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
-system.physmem.totQLat 51773260500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 131271366750 # Sum of mem lat for all requests
-system.physmem.totBusLat 11231405000 # Total cycles spent in databus access
-system.physmem.totBankLat 68266701250 # Total cycles spent in bank access
-system.physmem.avgQLat 23048.43 # Average queueing delay per request
-system.physmem.avgBankLat 30390.99 # Average bank access latency per request
+system.physmem.totQLat 51860326500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 131350914000 # Sum of mem lat for all requests
+system.physmem.totBusLat 11229015000 # Total cycles spent in databus access
+system.physmem.totBankLat 68261572500 # Total cycles spent in bank access
+system.physmem.avgQLat 23092.11 # Average queueing delay per request
+system.physmem.avgBankLat 30395.17 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58439.42 # Average memory access latency
-system.physmem.avgRdBW 277.94 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 136.17 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 277.94 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 136.17 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 58487.28 # Average memory access latency
+system.physmem.avgRdBW 277.90 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 277.90 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.24 # Data bus utilization in percentage
+system.physmem.busUtil 3.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.25 # Average read queue length over time
-system.physmem.avgWrQLen 10.87 # Average write queue length over time
-system.physmem.readRowHits 827731 # Number of row buffer hits during reads
-system.physmem.writeRowHits 271594 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.85 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 24.67 # Row buffer hit rate for writes
-system.physmem.avgGap 154548.18 # Average gap between requests
-system.cpu.branchPred.lookups 303270186 # Number of BP lookups
-system.cpu.branchPred.condPredicted 249470609 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15218764 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 173872286 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 161453824 # Number of BTB hits
+system.physmem.avgWrQLen 11.18 # Average write queue length over time
+system.physmem.readRowHits 827290 # Number of row buffer hits during reads
+system.physmem.writeRowHits 270800 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 24.61 # Row buffer hit rate for writes
+system.physmem.avgGap 154574.64 # Average gap between requests
+system.cpu.branchPred.lookups 303238356 # Number of BP lookups
+system.cpu.branchPred.condPredicted 249416285 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15213179 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 173189005 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 161485027 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.857711 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 17556602 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 209 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.242078 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17562220 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1034772569 # number of cpu cycles simulated
+system.cpu.numCycles 1034710708 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 298199766 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2186256801 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303270186 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 179010426 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 435094842 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 87837458 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 155394915 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 268 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 288550611 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5724997 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 958581863 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.523504 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.213349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 298243506 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2186139129 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 303238356 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 179047247 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 435102558 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 87842368 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 155357657 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 150 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 288597285 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5732219 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 958597013 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 523487088 54.61% 54.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25513973 2.66% 57.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39086986 4.08% 61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48352591 5.04% 66.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43006673 4.49% 70.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46441362 4.84% 75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38409512 4.01% 79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18721015 1.95% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175562663 18.31% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 523494535 54.61% 54.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25506855 2.66% 57.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39100627 4.08% 61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48361324 5.05% 66.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 43019358 4.49% 70.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46453211 4.85% 75.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38427133 4.01% 79.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18718773 1.95% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 175515197 18.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 958581863 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.293079 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.112790 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 329745900 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 133661747 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 405202825 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20079986 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69891405 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46059780 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 688 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2367115109 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2459 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69891405 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 353286700 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 63436503 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16572 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 400214250 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71736433 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2304580712 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 133421 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5040530 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58596294 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2279975350 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10642754356 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10642751444 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2912 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 958597013 # Number of instructions fetched each cycle (Total)
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+system.cpu.fetch.rate 2.112802 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 329802987 # Number of cycles decode is idle
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+system.cpu.decode.RunCycles 405201175 # Number of cycles decode is running
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+system.cpu.decode.BranchResolved 46072656 # Number of times decode resolved a branch
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+system.cpu.decode.SquashedInsts 2456 # Number of squashed instructions handled by decode
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system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 573655420 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 616 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 613 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158838581 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624481317 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220982521 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86134760 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71220480 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2201443562 # Number of instructions added to the IQ (excludes non-spec)
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-system.cpu.iq.iqInstsIssued 2018130110 # Number of instructions issued
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-system.cpu.iq.iqSquashedInstsExamined 473800004 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1125761712 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 470 # Number of squashed non-spec instructions that were removed
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-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.72% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18296872 76.51% 80.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4728009 19.77% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1236676135 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925418 0.05% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1236704914 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 925192 0.05% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 42 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 4 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587478696 29.11% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193049790 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 587491999 29.11% 90.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193051561 9.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2018130110 # Type of FU issued
-system.cpu.iq.rate 1.950313 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23883468 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011834 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5022727533 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2675434216 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1957455216 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 532 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2042013436 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 142 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64634043 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2018173722 # Type of FU issued
+system.cpu.iq.rate 1.950471 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23914793 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011850 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5022872024 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2675402581 # Number of integer instruction queue writes
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+system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138554548 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 275107 # Number of memory responses ignored because the instruction is squashed
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-system.cpu.iew.lsq.thread0.squashedStores 46135476 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
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+system.cpu.iew.lsq.thread0.cacheBlocked 4683320 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69891405 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28868892 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1502139 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2201444330 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6139194 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624481317 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220982521 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 578 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 475852 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 89903 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.predictedTakenIncorrect 8153538 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9615023 # Number of branches that were predicted not taken incorrectly
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-system.cpu.iew.iewExecutedInsts 1988122287 # Number of executed instructions
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+system.cpu.iew.iewExecutedInsts 1988146149 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 128 # number of nop insts executed
-system.cpu.iew.exec_refs 764057589 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238332739 # Number of branches executed
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-system.cpu.iew.exec_rate 1.921313 # Inst execution rate
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-system.cpu.iew.wb_count 1957455330 # cumulative count of insts written-back
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+system.cpu.iew.exec_nop 97 # number of nop insts executed
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+system.cpu.iew.wb_sent 1965914335 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1957468025 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1296382145 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.891677 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628964 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.891802 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.628969 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 401243318 45.15% 45.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192174198 21.62% 66.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72553521 8.16% 74.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35226900 3.96% 78.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18988678 2.14% 81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30770684 3.46% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20065099 2.26% 86.76% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::0 401292741 45.15% 45.15% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::2 72538162 8.16% 74.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35233922 3.96% 78.90% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::5 30755514 3.46% 84.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20061647 2.26% 86.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11460153 1.29% 88.05% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106236767 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106237292 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2983995614 # The number of ROB reads
-system.cpu.rob.rob_writes 4473124072 # The number of ROB writes
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-system.cpu.idleCycles 76190706 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2983974098 # The number of ROB reads
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+system.cpu.idleCycles 76113695 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
-system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.492659 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.492659 # IPC: Total IPC of All Threads
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+system.cpu.cpi 0.669905 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.669905 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 1.492749 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 124 # number of misc regfile writes
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+system.cpu.icache.replacements 21 # number of replacements
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24154.910057 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24154.910057 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.300453 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.300453 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24151.014528 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24151.014528 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44207.908802 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44207.908802 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:27
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 23:05:23
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 41615049000 because target called exit()
+122 123 124 Exiting @ tick 41622221000 because target called exit()
sim_ticks 41622221000 # Number of ticks simulated
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75517 # Simulator instruction rate (inst/s)
-host_op_rate 75517 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34200879 # Simulator tick rate (ticks/s)
-host_mem_usage 228092 # Number of bytes of host memory used
-host_seconds 1216.99 # Real time elapsed on the host
+host_inst_rate 47594 # Simulator instruction rate (inst/s)
+host_op_rate 47594 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21554846 # Simulator tick rate (ticks/s)
+host_mem_usage 275256 # Number of bytes of host memory used
+host_seconds 1930.99 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 23405750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests
+system.physmem.totQLat 23362750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
-system.physmem.totBankLat 74071250 # Total cycles spent in bank access
-system.physmem.avgQLat 4739.93 # Average queueing delay per request
-system.physmem.avgBankLat 15000.25 # Average bank access latency per request
+system.physmem.totBankLat 74057500 # Total cycles spent in bank access
+system.physmem.avgQLat 4731.22 # Average queueing delay per request
+system.physmem.avgBankLat 14997.47 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24740.18 # Average memory access latency
+system.physmem.avgMemAccLat 24728.69 # Average memory access latency
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.826152 # Percentage of cycles cpu is active
+system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed.
+system.cpu.activity 90.826155 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7635 # number of replacements
-system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
system.cpu.icache.overall_misses::total 11365 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22804.707435 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22804.707435 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22804.707435 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22804.707435 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209599500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 209599500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209599500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 209599500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209599500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 209599500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209587500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209587500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 209587500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209587500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 209587500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22016.754202 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22016.754202 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22015.493697 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22015.493697 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 2190.263404 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2190.263303 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1821.325190 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 351.099202 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132543500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 156612500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132531500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24055000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 156586500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 132543500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 108217000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 240760500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 132543500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 108217000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 240760500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 132531500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 108203000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 240734500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 132531500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 108203000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 240734500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47438.618468 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48697.916667 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47434.323550 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57002.369668 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48689.832090 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 48756.682868 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 48756.682868 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 48751.417578 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 48751.417578 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97826921 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18811852 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116638773 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63182194 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63182194 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97826921 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81994046 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 179820967 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97826921 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81994046 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 179820967 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97814921 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18797852 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116612773 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63183937 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63183937 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97814921 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81981789 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 179796710 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97814921 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81981789 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 179796710 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35013.214388 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44577.848341 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36268.275187 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36691.169570 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36691.169570 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35008.919470 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44544.672986 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36260.190609 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36692.181765 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36692.181765 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.tagsinuse 1441.801521 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1441.801521 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses
system.cpu.dcache.overall_misses::total 8676 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31369500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 377432000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 377432000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 377432000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 377432000 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 377418000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 377418000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 377418000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 377418000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 43502.996773 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 43502.996773 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111258000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 111258000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111258000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 111258000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:04:24
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 23:10:12
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 23378067000 because target called exit()
+122 123 124 Exiting @ tick 23379948000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023427 # Number of seconds simulated
-sim_ticks 23426793000 # Number of ticks simulated
-final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023380 # Number of seconds simulated
+sim_ticks 23379948000 # Number of ticks simulated
+final_tick 23379948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 128339 # Simulator instruction rate (inst/s)
-host_op_rate 128339 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35715987 # Simulator tick rate (ticks/s)
-host_mem_usage 230140 # Number of bytes of host memory used
-host_seconds 655.92 # Real time elapsed on the host
+host_inst_rate 61366 # Simulator instruction rate (inst/s)
+host_op_rate 61366 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17043654 # Simulator tick rate (ticks/s)
+host_mem_usage 277304 # Number of bytes of host memory used
+host_seconds 1371.77 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory
-system.physmem.bytes_read::total 334592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8365123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5917327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14282450 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8365123 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8365123 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8365123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5917327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 14282450 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5228 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 195840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory
+system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 195840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 195840 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3060 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 8376409 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5931921 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14308330 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8376409 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8376409 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8376409 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5931921 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 14308330 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5227 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 334592 # Total number of bytes read from memory
+system.physmem.cpureqs 5227 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 334528 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 334592 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 334528 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 325 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 327 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 326 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 312 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 285 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 246 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 327 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 311 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 297 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 281 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 376 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 379 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 398 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 374 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 377 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 354 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 400 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23426687000 # Total gap between requests
+system.physmem.totGap 23379842000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5228 # Categorize read packet sizes
+system.physmem.readPktSize::6 5227 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3175 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3182 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 28652250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 133882250 # Sum of mem lat for all requests
-system.physmem.totBusLat 26140000 # Total cycles spent in databus access
-system.physmem.totBankLat 79090000 # Total cycles spent in bank access
-system.physmem.avgQLat 5480.54 # Average queueing delay per request
-system.physmem.avgBankLat 15128.16 # Average bank access latency per request
+system.physmem.totQLat 29390250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 134711500 # Sum of mem lat for all requests
+system.physmem.totBusLat 26135000 # Total cycles spent in databus access
+system.physmem.totBankLat 79186250 # Total cycles spent in bank access
+system.physmem.avgQLat 5622.78 # Average queueing delay per request
+system.physmem.avgBankLat 15149.46 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25608.69 # Average memory access latency
-system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25772.24 # Average memory access latency
+system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.11 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4452 # Number of row buffer hits during reads
+system.physmem.readRowHits 4448 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.16 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 85.10 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4481003.63 # Average gap between requests
-system.cpu.branchPred.lookups 14862899 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10784279 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 925607 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8448126 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6969256 # Number of BTB hits
+system.physmem.avgGap 4472898.79 # Average gap between requests
+system.cpu.branchPred.lookups 14842140 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10766991 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 921197 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8255704 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6953438 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 82.494698 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1468807 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3068 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 84.225864 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1467825 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3067 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 23133213 # DTB read hits
-system.cpu.dtb.read_misses 193272 # DTB read misses
+system.cpu.dtb.read_hits 23110097 # DTB read hits
+system.cpu.dtb.read_misses 194589 # DTB read misses
system.cpu.dtb.read_acv 2 # DTB read access violations
-system.cpu.dtb.read_accesses 23326485 # DTB read accesses
-system.cpu.dtb.write_hits 7072266 # DTB write hits
-system.cpu.dtb.write_misses 1114 # DTB write misses
-system.cpu.dtb.write_acv 4 # DTB write access violations
-system.cpu.dtb.write_accesses 7073380 # DTB write accesses
-system.cpu.dtb.data_hits 30205479 # DTB hits
-system.cpu.dtb.data_misses 194386 # DTB misses
-system.cpu.dtb.data_acv 6 # DTB access violations
-system.cpu.dtb.data_accesses 30399865 # DTB accesses
-system.cpu.itb.fetch_hits 14751258 # ITB hits
+system.cpu.dtb.read_accesses 23304686 # DTB read accesses
+system.cpu.dtb.write_hits 7067053 # DTB write hits
+system.cpu.dtb.write_misses 1113 # DTB write misses
+system.cpu.dtb.write_acv 6 # DTB write access violations
+system.cpu.dtb.write_accesses 7068166 # DTB write accesses
+system.cpu.dtb.data_hits 30177150 # DTB hits
+system.cpu.dtb.data_misses 195702 # DTB misses
+system.cpu.dtb.data_acv 8 # DTB access violations
+system.cpu.dtb.data_accesses 30372852 # DTB accesses
+system.cpu.itb.fetch_hits 14723480 # ITB hits
system.cpu.itb.fetch_misses 97 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 14751355 # ITB accesses
+system.cpu.itb.fetch_accesses 14723577 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 46853587 # number of cpu cycles simulated
+system.cpu.numCycles 46759897 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15478226 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127086204 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14862899 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 8438063 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22152522 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4487790 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5536762 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 83 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2724 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 15452025 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 126885771 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14842140 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 8421263 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22118402 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4462593 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5523983 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2725 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 14751258 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 326039 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46698540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.721417 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.376215 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 14723480 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 324121 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46604653 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.722599 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.376512 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24546018 52.56% 52.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2363136 5.06% 57.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1191999 2.55% 60.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1747286 3.74% 63.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2758963 5.91% 69.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1151332 2.47% 72.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1219220 2.61% 74.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 775308 1.66% 76.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10945278 23.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24486251 52.54% 52.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2361565 5.07% 57.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1190149 2.55% 60.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1742976 3.74% 63.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2754417 5.91% 69.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1149365 2.47% 72.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1217917 2.61% 74.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 773119 1.66% 76.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10928894 23.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46698540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.317220 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.712411 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17303274 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4237001 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20547487 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1094236 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3516542 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2516790 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12060 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 124092936 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 31896 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3516542 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18446150 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 953596 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7276 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20476535 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3298441 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 121253427 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 399455 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2423561 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 89048453 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 157563733 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 147863840 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9699893 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 46604653 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.317412 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.713560 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17272805 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4225851 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20520611 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1089695 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3495691 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2514029 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12278 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 123910172 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 32104 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3495691 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18413803 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 951839 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7350 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20446933 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3289037 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 121090735 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 399536 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2410998 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 88918567 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 157348562 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 147674536 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9674026 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 20621092 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 715 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8762124 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 25385907 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8248290 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2586709 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 908922 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 105520430 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1810 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 96627173 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 179301 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20866432 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15656081 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1421 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46698540 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.069169 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.876778 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 20491206 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 720 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 712 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 8742624 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 25345876 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8236695 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2569867 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 913943 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 105383195 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1656 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 96551560 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 178239 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20729473 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 15559619 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1267 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 46604653 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.071715 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.877215 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 12145462 26.01% 26.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 9347287 20.02% 46.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8392983 17.97% 64.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6295181 13.48% 77.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4922186 10.54% 88.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2865412 6.14% 94.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1725444 3.69% 97.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 796771 1.71% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 207814 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12094878 25.95% 25.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 9328666 20.02% 45.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8376475 17.97% 63.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6286526 13.49% 77.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4922367 10.56% 87.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2863469 6.14% 94.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1727619 3.71% 97.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 799385 1.72% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 205268 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46698540 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46604653 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 188040 12.01% 12.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 12.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 12.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 192 0.01% 12.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 7132 0.46% 12.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 5753 0.37% 12.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 842663 53.82% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 443560 28.33% 95.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78346 5.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 187515 11.95% 11.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 174 0.01% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 7228 0.46% 12.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 5644 0.36% 12.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 843061 53.75% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 446254 28.45% 94.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78748 5.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58768195 60.82% 60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 479903 0.50% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58727382 60.82% 60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 479803 0.50% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2800414 2.90% 64.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115399 0.12% 64.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2387049 2.47% 66.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 311103 0.32% 67.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 759957 0.79% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23849343 24.68% 92.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7155484 7.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2798335 2.90% 64.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 115384 0.12% 64.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2386573 2.47% 66.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 311072 0.32% 67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 760041 0.79% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 23822951 24.67% 92.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7149693 7.41% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 96627173 # Type of FU issued
-system.cpu.iq.rate 2.062322 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1565686 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 226574505 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 117655638 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87117393 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15123368 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 8767383 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7066303 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90201258 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7991594 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1516780 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 96551560 # Type of FU issued
+system.cpu.iq.rate 2.064837 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1568624 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016246 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 226343159 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 117415886 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87055232 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 15111477 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 8732806 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7062055 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90134309 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 7985868 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1517472 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5389709 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18571 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34473 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1747187 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5349678 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18734 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34491 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1735592 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10549 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1581 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 10525 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1599 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3516542 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 131686 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 18180 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 115763317 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 371525 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 25385907 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8248290 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1810 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2912 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34473 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 538490 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 495901 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1034391 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 95392807 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23326978 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1234366 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3495691 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 132330 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18056 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 115618245 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 370442 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 25345876 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 8236695 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1656 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2792 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34491 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 533607 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 495069 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1028676 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 95323071 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23305173 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1228489 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10241077 # number of nop insts executed
-system.cpu.iew.exec_refs 30400564 # number of memory reference insts executed
-system.cpu.iew.exec_branches 12029650 # Number of branches executed
-system.cpu.iew.exec_stores 7073586 # Number of stores executed
-system.cpu.iew.exec_rate 2.035977 # Inst execution rate
-system.cpu.iew.wb_sent 94705450 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 94183696 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 64505139 # num instructions producing a value
-system.cpu.iew.wb_consumers 89892889 # num instructions consuming a value
+system.cpu.iew.exec_nop 10233394 # number of nop insts executed
+system.cpu.iew.exec_refs 30373541 # number of memory reference insts executed
+system.cpu.iew.exec_branches 12020857 # Number of branches executed
+system.cpu.iew.exec_stores 7068368 # Number of stores executed
+system.cpu.iew.exec_rate 2.038565 # Inst execution rate
+system.cpu.iew.wb_sent 94638543 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 94117287 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 64469301 # num instructions producing a value
+system.cpu.iew.wb_consumers 89849772 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.010170 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.717578 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.012778 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.717523 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23861264 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 23716139 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 913934 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 43181998 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.128272 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.745397 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 909447 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 43108962 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.131878 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.747863 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16729209 38.74% 38.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9919354 22.97% 61.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4482137 10.38% 72.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2267062 5.25% 77.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1606601 3.72% 81.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1122793 2.60% 83.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 721285 1.67% 85.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 818294 1.89% 87.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5515263 12.77% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16687185 38.71% 38.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 9891500 22.95% 61.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4481461 10.40% 72.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2260770 5.24% 77.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1601496 3.71% 81.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1124303 2.61% 83.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 719465 1.67% 85.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 820222 1.90% 87.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5522560 12.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 43181998 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 43108962 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
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-system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004329 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 236 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 28081617 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 28081617 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 28081617 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 28081617 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004237 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004237 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50286.354582 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50286.354582 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44024.490429 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44024.490429 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50570.009930 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50570.009930 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44042.207582 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44042.207582 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 44715.283925 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 44715.283925 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 14195 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 44764.173202 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 44764.173202 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 14165 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 327 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 330 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.409786 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.924242 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
system.cpu.dcache.writebacks::total 109 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 489 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6366 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6366 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 6855 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 6855 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 6855 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 6855 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 491 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 491 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6367 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6367 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 6858 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 6858 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 6858 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 6858 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 516 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 516 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30190000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 30190000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88528998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 88528998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30419500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 30419500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88590998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 88590998 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118718998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 118718998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118718998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 118718998 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119010498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 119010498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119010498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 119010498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004329 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004329 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004237 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004237 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58621.359223 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58621.359223 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51143.268631 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51143.268631 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58952.519380 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58952.519380 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51179.086077 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51179.086077 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:30:01
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 27 2013 03:01:21
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74148853000 because target called exit()
+122 123 124 Exiting @ tick 74157495500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.074156 # Number of seconds simulated
-sim_ticks 74155951500 # Number of ticks simulated
-final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.074157 # Number of seconds simulated
+sim_ticks 74157495500 # Number of ticks simulated
+final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 102580 # Simulator instruction rate (inst/s)
-host_op_rate 112316 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44148416 # Simulator tick rate (ticks/s)
-host_mem_usage 245240 # Number of bytes of host memory used
-host_seconds 1679.70 # Real time elapsed on the host
+host_inst_rate 51189 # Simulator instruction rate (inst/s)
+host_op_rate 56047 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 22031117 # Simulator tick rate (ticks/s)
+host_mem_usage 291420 # Number of bytes of host memory used
+host_seconds 3366.03 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 112064 # Number of bytes read from this memory
-system.physmem.bytes_read::total 243840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory
+system.physmem.bytes_read::total 243712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1751 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3810 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1777012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1511194 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3288205 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1777012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1777012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1777012 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1511194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3288205 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3811 # Total number of read requests seen
+system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3809 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 243840 # Total number of bytes read from memory
+system.physmem.bytesRead 243712 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 243840 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 322 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 207 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 246 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 203 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 247 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 74155933000 # Total gap between requests
+system.physmem.totGap 74157477000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 3811 # Categorize read packet sizes
+system.physmem.readPktSize::6 3809 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 17809500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 103882000 # Sum of mem lat for all requests
-system.physmem.totBusLat 19055000 # Total cycles spent in databus access
-system.physmem.totBankLat 67017500 # Total cycles spent in bank access
-system.physmem.avgQLat 4673.18 # Average queueing delay per request
-system.physmem.avgBankLat 17585.28 # Average bank access latency per request
+system.physmem.totQLat 17510750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests
+system.physmem.totBusLat 19045000 # Total cycles spent in databus access
+system.physmem.totBankLat 66880000 # Total cycles spent in bank access
+system.physmem.avgQLat 4597.20 # Average queueing delay per request
+system.physmem.avgBankLat 17558.41 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27258.46 # Average memory access latency
+system.physmem.avgMemAccLat 27155.62 # Average memory access latency
system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 3029 # Number of row buffer hits during reads
+system.physmem.readRowHits 3021 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19458392.29 # Average gap between requests
-system.cpu.branchPred.lookups 94769609 # Number of BP lookups
-system.cpu.branchPred.condPredicted 74778233 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6277605 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 44694278 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 43050555 # Number of BTB hits
+system.physmem.avgGap 19469014.70 # Average gap between requests
+system.cpu.branchPred.lookups 94703867 # Number of BP lookups
+system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 96.322297 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 4352672 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 88403 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 148311904 # number of cpu cycles simulated
+system.cpu.numCycles 148314992 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 39646309 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 380172339 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 94769609 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 47403227 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80367500 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 27273234 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7195566 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 5621 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 36841499 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1830160 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 148194878 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.802185 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152973 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67997083 45.88% 45.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5272996 3.56% 49.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10535975 7.11% 56.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10290073 6.94% 63.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8651484 5.84% 69.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6547502 4.42% 73.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6243559 4.21% 77.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8000119 5.40% 83.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 24656087 16.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 148194878 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.638989 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.563330 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45496007 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5866375 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74802564 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1203257 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 20826675 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14321536 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 392763604 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 730055 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 20826675 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50882111 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 721217 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 592672 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70557397 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4614806 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 371296733 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 341377 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3661217 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 631671723 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1581648558 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1564322118 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17326440 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 333627584 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25019 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 25015 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13027360 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 43001248 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16425649 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5676819 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3663476 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 329185491 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 47072 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249459953 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 787409 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 139507738 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 361963164 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 148194878 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.683324 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.761955 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56034848 37.81% 37.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22634456 15.27% 53.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24811776 16.74% 69.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20313354 13.71% 83.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12551343 8.47% 92.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6515797 4.40% 96.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4037298 2.72% 99.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1114310 0.75% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 181696 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 148194878 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 964655 38.37% 38.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5597 0.22% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 47 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1171629 46.60% 85.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 372002 14.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 194901733 78.13% 78.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 979970 0.39% 78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33123 0.01% 78.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164480 0.07% 78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 254950 0.10% 78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 465883 0.19% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206474 0.08% 79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38354449 15.37% 94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13950286 5.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249459953 # Type of FU issued
-system.cpu.iq.rate 1.681995 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2514028 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010078 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 646678377 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 466567894 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237899290 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3737844 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2190776 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1842401 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 250099013 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1874968 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2006458 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued
+system.cpu.iq.rate 1.681779 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13151764 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11904 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18813 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3781015 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 20826675 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 16651 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 839 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 329249613 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 779131 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 43001248 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16425649 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 24664 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18813 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3890202 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3759917 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7650119 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 242971028 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 36855113 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6488925 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 17050 # number of nop insts executed
-system.cpu.iew.exec_refs 50502517 # number of memory reference insts executed
-system.cpu.iew.exec_branches 53426440 # Number of branches executed
-system.cpu.iew.exec_stores 13647404 # Number of stores executed
-system.cpu.iew.exec_rate 1.638244 # Inst execution rate
-system.cpu.iew.wb_sent 240798946 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239741691 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 148482444 # num instructions producing a value
-system.cpu.iew.wb_consumers 267276214 # num instructions consuming a value
+system.cpu.iew.exec_nop 16978 # number of nop insts executed
+system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed
+system.cpu.iew.exec_branches 53412943 # Number of branches executed
+system.cpu.iew.exec_stores 13648437 # Number of stores executed
+system.cpu.iew.exec_rate 1.637967 # Inst execution rate
+system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 148457899 # num instructions producing a value
+system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.616470 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 140578703 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6124430 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 127368203 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.481303 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.186211 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 127378611 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 57677570 45.28% 45.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 31688766 24.88% 70.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13782136 10.82% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7629564 5.99% 86.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4377691 3.44% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1320690 1.04% 91.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1704652 1.34% 92.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1310037 1.03% 93.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7877097 6.18% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 127368203 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 127378611 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
system.cpu.commit.int_insts 150106217 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 7877097 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 448735499 # The number of ROB reads
-system.cpu.rob.rob_writes 679435154 # The number of ROB writes
-system.cpu.timesIdled 2602 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 117026 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 448668532 # The number of ROB reads
+system.cpu.rob.rob_writes 679284219 # The number of ROB writes
+system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
-system.cpu.cpi 0.860762 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.860762 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.161761 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.161761 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1079459412 # number of integer regfile reads
-system.cpu.int_regfile_writes 384885584 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2914044 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2498648 # number of floating regfile writes
-system.cpu.misc_regfile_reads 54505090 # number of misc regfile reads
+system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads
+system.cpu.int_regfile_writes 384845307 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2496150 # number of floating regfile writes
+system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
-system.cpu.icache.replacements 2367 # number of replacements
-system.cpu.icache.tagsinuse 1349.329106 # Cycle average of tags in use
-system.cpu.icache.total_refs 36836268 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4097 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8991.034415 # Average number of references to valid blocks.
+system.cpu.icache.replacements 2376 # number of replacements
+system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use
+system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1349.329106 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.658852 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.658852 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 36836269 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 36836269 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 36836269 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 36836269 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 36836269 # number of overall hits
-system.cpu.icache.overall_hits::total 36836269 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5230 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5230 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5230 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5230 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5230 # number of overall misses
-system.cpu.icache.overall_misses::total 5230 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 167188500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 167188500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 167188500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 167188500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 167188500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 167188500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 36841499 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 36841499 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 36841499 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 36841499 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 36841499 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 36841499 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1350.566241 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.659456 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.659456 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 36852123 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 36852123 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 36852123 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 36852123 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 36852123 # number of overall hits
+system.cpu.icache.overall_hits::total 36852123 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5235 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5235 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5235 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5235 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5235 # number of overall misses
+system.cpu.icache.overall_misses::total 5235 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 167149000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 167149000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 167149000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 167149000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 167149000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 167149000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 36857358 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 36857358 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 36857358 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 36857358 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 36857358 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 36857358 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31967.208413 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31967.208413 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31967.208413 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31967.208413 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1127 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 19 # number of writebacks
+system.cpu.dcache.writebacks::total 19 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6648 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6648 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7770 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7770 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7770 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7770 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41603000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 41603000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50879498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 50879498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92482498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 92482498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92482498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 92482498 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 7776 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7776 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7776 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7776 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41130000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 41130000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50620998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 50620998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 91750998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 91750998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 91750998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 91750998 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53543.114543 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53543.114543 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46807.265869 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46807.265869 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 26 2013 23:44:56
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 82877188500 because target called exit()
+122 123 124 Exiting @ tick 82784332500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.082877 # Number of seconds simulated
-sim_ticks 82877188500 # Number of ticks simulated
-final_tick 82877188500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.082784 # Number of seconds simulated
+sim_ticks 82784332500 # Number of ticks simulated
+final_tick 82784332500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45467 # Simulator instruction rate (inst/s)
-host_op_rate 76207 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28531656 # Simulator tick rate (ticks/s)
-host_mem_usage 321540 # Number of bytes of host memory used
-host_seconds 2904.75 # Real time elapsed on the host
+host_inst_rate 28862 # Simulator instruction rate (inst/s)
+host_op_rate 48376 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18091276 # Simulator tick rate (ticks/s)
+host_mem_usage 321848 # Number of bytes of host memory used
+host_seconds 4575.93 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 218496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 343040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218496 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218496 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3414 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2636383 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1502754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4139137 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2636383 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2636383 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2636383 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1502754 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4139137 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5362 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 342080 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1943 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5345 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2630063 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1502120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4132183 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2630063 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2630063 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2630063 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1502120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4132183 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5347 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 343040 # Total number of bytes read from memory
+system.physmem.cpureqs 5510 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 342080 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 343040 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 342080 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 157 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 163 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 274 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 293 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 289 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 273 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 378 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 374 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 370 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 378 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 366 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 358 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 339 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 356 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 353 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 82877158000 # Total gap between requests
+system.physmem.totGap 82784303000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5362 # Categorize read packet sizes
+system.physmem.readPktSize::6 5347 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 940 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4168 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 927 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 16751250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 133128750 # Sum of mem lat for all requests
-system.physmem.totBusLat 26810000 # Total cycles spent in databus access
-system.physmem.totBankLat 89567500 # Total cycles spent in bank access
-system.physmem.avgQLat 3124.07 # Average queueing delay per request
-system.physmem.avgBankLat 16704.12 # Average bank access latency per request
+system.physmem.totQLat 15985000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 132177500 # Sum of mem lat for all requests
+system.physmem.totBusLat 26735000 # Total cycles spent in databus access
+system.physmem.totBankLat 89457500 # Total cycles spent in bank access
+system.physmem.avgQLat 2989.53 # Average queueing delay per request
+system.physmem.avgBankLat 16730.41 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24828.19 # Average memory access latency
-system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24719.94 # Average memory access latency
+system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4540 # Number of row buffer hits during reads
+system.physmem.readRowHits 4531 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 84.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 15456389.03 # Average gap between requests
-system.cpu.branchPred.lookups 19990631 # Number of BP lookups
-system.cpu.branchPred.condPredicted 19990631 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2016236 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 13900591 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13121041 # Number of BTB hits
+system.physmem.avgGap 15482383.21 # Average gap between requests
+system.cpu.branchPred.lookups 19946660 # Number of BP lookups
+system.cpu.branchPred.condPredicted 19946660 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2010176 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 13817098 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13100139 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.391965 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 94.811074 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 165754378 # number of cpu cycles simulated
+system.cpu.numCycles 165568666 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 25900956 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 219294156 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 19990631 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 13121041 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 57660261 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17705629 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 66643848 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1767 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24505830 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 429319 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 165627301 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.187204 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.326012 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 25865179 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 219003921 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 19946660 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 13100139 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 57576020 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 17616732 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 66658067 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 301 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2079 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 100 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 24478210 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 431162 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 165440333 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.186068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.325239 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 109570790 66.16% 66.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3065879 1.85% 68.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2385245 1.44% 69.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2897287 1.75% 71.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3451303 2.08% 73.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3579914 2.16% 75.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4327523 2.61% 78.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2732307 1.65% 79.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33617053 20.30% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 109457492 66.16% 66.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3058910 1.85% 68.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2395088 1.45% 69.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2913515 1.76% 71.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3447820 2.08% 73.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3570209 2.16% 75.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4310601 2.61% 78.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2725404 1.65% 79.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 33561294 20.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 165627301 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.120604 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.323007 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38796677 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 56675107 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44775430 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9959956 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 15420131 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 354106901 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 15420131 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 46276497 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14977058 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 23177 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 46586117 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 42344321 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 345709417 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 18016892 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22216647 # Number of times rename has blocked due to LSQ full
+system.cpu.fetch.rateDist::total 165440333 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.120474 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.322738 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38757375 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 56681760 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44701919 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9960692 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 15338587 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 353512832 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 15338587 # Number of cycles rename is squashing
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+system.cpu.rename.BlockCycles 14972536 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 23135 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.IQFullEvents 18050300 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 22188357 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 399350509 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 961743278 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 951847615 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9895663 # Number of floating rename lookups
+system.cpu.rename.RenamedOperands 398793355 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 959907307 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 950110032 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9797275 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 139921903 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1677 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1668 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 90545817 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 86819200 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 31825632 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 57864226 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 18806791 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 334068514 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3610 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 267647923 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 253259 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 112254554 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 230842120 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2365 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 165627301 # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::stdev 1.504012 # Number of insts issued each cycle
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-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.94% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.94% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.94% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.94% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1212174 0.45% 0.45% # Type of FU issued
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-system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 67254766 25.13% 91.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 23288946 8.70% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 174223829 65.13% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1597035 0.60% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 67207754 25.12% 91.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 23264904 8.70% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 267647923 # Type of FU issued
-system.cpu.iq.rate 1.614726 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2656461 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009925 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 698473214 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 441941062 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 260395422 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 5359653 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4679108 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2580004 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266396647 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2695563 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 19008282 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 267505666 # Type of FU issued
+system.cpu.iq.rate 1.615678 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2670707 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 698027148 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 440935220 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 260272326 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 5352020 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4598390 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2575188 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266272654 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2691575 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 19010388 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 30169613 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 29317 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 298845 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11309915 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 29975814 # Number of loads squashed
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+system.cpu.iew.lsq.thread0.memOrderViolation 297064 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11247755 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49334 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 49364 # Number of loads that were rescheduled
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 15420131 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 575337 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 259825 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 334072124 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 191879 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 86819200 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 31825632 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1661 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 148151 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 27876 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 298845 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1178996 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 920787 # Number of branches that were predicted not taken incorrectly
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-system.cpu.iew.iewExecutedInsts 264757229 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 66265318 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2890694 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 15338587 # Number of cycles IEW is squashing
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+system.cpu.iew.iewUnblockCycles 254753 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 333528399 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 142182 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 30086 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 1176748 # Number of branches that were predicted taken incorrectly
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+system.cpu.iew.branchMispredicts 2092356 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 264614762 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 89162320 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14609733 # Number of branches executed
-system.cpu.iew.exec_stores 22897002 # Number of stores executed
-system.cpu.iew.exec_rate 1.597286 # Inst execution rate
-system.cpu.iew.wb_sent 263814551 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 262975426 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 212208096 # num instructions producing a value
-system.cpu.iew.wb_consumers 375332869 # num instructions consuming a value
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+system.cpu.iew.wb_sent 263675320 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 262847514 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 212089133 # num instructions producing a value
+system.cpu.iew.wb_consumers 375086159 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.586537 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.565386 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.587544 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.565441 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 112746099 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2016423 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 150207170 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.473718 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.941598 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 1.474753 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.942108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 50947202 33.92% 33.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57273647 38.13% 72.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13797241 9.19% 81.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12067854 8.03% 89.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4154161 2.77% 92.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2974218 1.98% 94.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1064553 0.71% 94.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1010133 0.67% 95.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6918161 4.61% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 50823152 33.86% 33.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57296396 38.17% 72.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13814368 9.20% 81.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12061169 8.04% 89.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4147019 2.76% 92.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2963443 1.97% 94.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1057939 0.70% 94.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1004682 0.67% 95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6933578 4.62% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6918161 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6933578 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 477398070 # The number of ROB reads
-system.cpu.rob.rob_writes 683673273 # The number of ROB writes
-system.cpu.timesIdled 2993 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 127077 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 476733976 # The number of ROB reads
+system.cpu.rob.rob_writes 682504424 # The number of ROB writes
+system.cpu.timesIdled 2963 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 128333 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
-system.cpu.cpi 1.255038 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.255038 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.796789 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.796789 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 562793335 # number of integer regfile reads
-system.cpu.int_regfile_writes 298868750 # number of integer regfile writes
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-system.cpu.fp_regfile_writes 2239527 # number of floating regfile writes
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+system.cpu.cpi 1.253632 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.253632 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.797682 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.797682 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 562551000 # number of integer regfile reads
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system.cpu.misc_regfile_writes 845 # number of misc regfile writes
-system.cpu.icache.replacements 4944 # number of replacements
-system.cpu.icache.tagsinuse 1623.744998 # Cycle average of tags in use
-system.cpu.icache.total_refs 24496606 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 6912 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3544.069155 # Average number of references to valid blocks.
+system.cpu.icache.replacements 4809 # number of replacements
+system.cpu.icache.tagsinuse 1620.816173 # Cycle average of tags in use
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+system.cpu.icache.avg_refs 3611.686790 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::cpu.inst 0.792844 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.792844 # Average percentage of cache occupancy
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-system.cpu.icache.demand_hits::total 24496606 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 24496606 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 9224 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 9224 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 9224 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 9224 # number of overall misses
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-system.cpu.icache.ReadReq_accesses::total 24505830 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000376 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000376 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000376 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.000376 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29695.468018 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29695.468018 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 29695.468018 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29695.468018 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29695.468018 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked
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+system.cpu.icache.overall_miss_latency::total 270256997 # number of overall miss cycles
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29922.165301 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29922.165301 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 31 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 34.814815 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_mshr_hits::total 2153 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 7071 # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total 7071 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 7071 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 7071 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206824497 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58324.228029 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58324.228029 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42941.603719 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42941.603719 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57559.808612 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57559.808612 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42756.952491 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42756.952491 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:42
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:13
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 608846000
-Exiting @ tick 1950813955500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 614109000
+Exiting @ tick 1955749107000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.954691 # Number of seconds simulated
-sim_ticks 1954691371500 # Number of ticks simulated
-final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.955749 # Number of seconds simulated
+sim_ticks 1955749107000 # Number of ticks simulated
+final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1268205 # Simulator instruction rate (inst/s)
-host_op_rate 1268205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41788272650 # Simulator tick rate (ticks/s)
-host_mem_usage 331540 # Number of bytes of host memory used
-host_seconds 46.78 # Real time elapsed on the host
-sim_insts 59321614 # Number of instructions simulated
-sim_ops 59321614 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory
+host_inst_rate 473674 # Simulator instruction rate (inst/s)
+host_op_rate 473674 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15599111797 # Simulator tick rate (ticks/s)
+host_mem_usage 350548 # Number of bytes of host memory used
+host_seconds 125.38 # Real time elapsed on the host
+sim_insts 59387196 # Number of instructions simulated
+sim_ops 59387196 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 447836 # Total number of read requests seen
-system.physmem.writeReqs 119953 # Total number of write requests seen
-system.physmem.cpureqs 570963 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28661504 # Total number of bytes read from memory
-system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
+system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 447817 # Total number of read requests seen
+system.physmem.writeReqs 120035 # Total number of write requests seen
+system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28660288 # Total number of bytes read from memory
+system.physmem.bytesWritten 7682240 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3162 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 12 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1954684300500 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1955741979500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 447836 # Categorize read packet sizes
+system.physmem.readPktSize::6 447817 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 119953 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 407019 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4805 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2220 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2702 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2596 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 120035 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1427 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1370 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1349 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1510 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 781 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3708 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4324 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4841 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5200 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see
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system.cpu0.dtb.write_accesses 187452 # DTB write accesses
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system.cpu0.dtb.data_acv 344 # DTB access violations
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system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
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system.cpu0.itb.data_misses 0 # DTB misses
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-system.cpu0.num_store_insts 6059322 # Number of store instructions
-system.cpu0.num_idle_cycles 3679287255.686766 # Number of idle cycles
-system.cpu0.num_busy_cycles 228924280.313234 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
+system.cpu0.committedInsts 54125350 # Number of instructions committed
+system.cpu0.committedOps 54125350 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 50093853 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 294168 # Number of float alu accesses
+system.cpu0.num_func_calls 1428171 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 6241814 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 50093853 # number of integer instructions
+system.cpu0.num_fp_insts 294168 # number of float instructions
+system.cpu0.num_int_register_reads 68603455 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 37120934 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 143452 # number of times the floating registers were read
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+system.cpu0.num_mem_refs 14736943 # number of memory refs
+system.cpu0.num_load_insts 8672910 # Number of load instructions
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+system.cpu0.num_busy_cycles 230937650.547156 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.059061 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.940939 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 203014 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 72751 40.62% 40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1898301427500 97.14% 97.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
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-system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 54943825500 2.81% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed
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system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
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system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
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-system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
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system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 188224 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
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-system.cpu0.kern.mode_good::kernel 1283
-system.cpu0.kern.mode_good::user 1283
+system.cpu0.kern.mode_good::kernel 1284
+system.cpu0.kern.mode_good::user 1284
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
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-system.cpu0.kern.mode_ticks::kernel 1950347158000 99.82% 99.82% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3898 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 915312 # number of replacements
-system.cpu0.icache.tagsinuse 509.170564 # Cycle average of tags in use
-system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.170564 # Average occupied blocks per requestor
+system.cpu0.icache.replacements 915791 # number of replacements
+system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use
+system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks.
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+system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor
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system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.735273 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 13805.735273 # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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-system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.735273 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.dcache.demand_avg_miss_latency::total 23046.718238 # average overall miss latency
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+system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 23023.251252 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.writebacks::total 791336 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291308 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 291308 # number of WriteReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1327950 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327950 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7610535000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181379000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1681500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27917826500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 27917826500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27917826500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 27917826500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465371000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465371000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092831000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092831000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3558202000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3558202000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122461 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049743 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049743 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002264 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.092726 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26125.389622 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11082.671392 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3865.517241 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1047086 # DTB read hits
+system.cpu1.dtb.read_hits 1047303 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 650181 # DTB write hits
+system.cpu1.dtb.write_hits 650380 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 1697267 # DTB hits
+system.cpu1.dtb.data_hits 1697683 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1487534 # ITB hits
+system.cpu1.itb.fetch_hits 1487846 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1488750 # ITB accesses
+system.cpu1.itb.fetch_accesses 1489062 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3909382743 # number of cpu cycles simulated
+system.cpu1.numCycles 3911498214 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 5259785 # Number of instructions committed
-system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses
+system.cpu1.committedInsts 5261846 # Number of instructions committed
+system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
-system.cpu1.num_func_calls 156703 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 4928462 # number of integer instructions
+system.cpu1.num_func_calls 156775 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 4930311 # number of integer instructions
system.cpu1.num_fp_insts 34031 # number of float instructions
-system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1706720 # number of memory refs
-system.cpu1.num_load_insts 1053093 # Number of load instructions
-system.cpu1.num_store_insts 653627 # Number of store instructions
-system.cpu1.num_idle_cycles 3890042730.998010 # Number of idle cycles
-system.cpu1.num_busy_cycles 19340012.001990 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
+system.cpu1.num_mem_refs 1707139 # number of memory refs
+system.cpu1.num_load_insts 1053310 # Number of load instructions
+system.cpu1.num_store_insts 653829 # Number of store instructions
+system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles
+system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1917858601000 98.12% 98.12% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 36066950000 1.85% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
+system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
-system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed
+system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed
system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 28898 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches
+system.cpu1.kern.callpal::total 28917 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 477
system.cpu1.kern.mode_good::user 464
system.cpu1.kern.mode_good::idle 13
-system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_switch_good::idle 0.006286 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 338 # number of times the context was actually changed
-system.cpu1.icache.replacements 86368 # number of replacements
-system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits
-system.cpu1.icache.overall_hits::total 5176232 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses
-system.cpu1.icache.overall_misses::total 86916 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175956500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 1175956500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 1175956500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 1175956500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 1175956500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 1175956500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.804639 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.804639 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13529.804639 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13529.804639 # average overall miss latency
+system.cpu1.icache.replacements 86405 # number of replacements
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12498.635946 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26675.412808 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26675.412808 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11000 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11000 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7382.874016 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7382.874016 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17536.574324 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17536.574324 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
-system.cpu1.dcache.writebacks::total 30630 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37009 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 37009 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 57410 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 57410 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 57410 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 57410 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389699500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389699500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500101500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500101500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8687500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8687500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889801000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 889801000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889801000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 889801000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035646 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035646 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.857602 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.857602 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.577766 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.577766 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9087.343096 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9087.343096 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 30625 # number of writebacks
+system.cpu1.dcache.writebacks::total 30625 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37022 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 37022 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20409 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 20409 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 934 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 934 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 508 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 508 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 57431 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 57431 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 57431 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 57431 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 388680500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 388680500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 503600500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 503600500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8406000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8406000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2734500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2734500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 892281000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 892281000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 892281000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 892281000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 530266500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 530266500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 549654000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 549654000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.034282 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10498.635946 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10498.635946 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24675.412808 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24675.412808 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9000 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9000 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5382.874016 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5382.874016 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
-dtb_filename=
+dtb_filename=False
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:46:40
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 26 2013 15:15:53
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1182882156500 because m5_exit instruction encountered
+Exiting @ tick 1183437503500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.182958 # Number of seconds simulated
-sim_ticks 1182958259000 # Number of ticks simulated
-final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.183438 # Number of seconds simulated
+sim_ticks 1183437503500 # Number of ticks simulated
+final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332432 # Simulator instruction rate (inst/s)
-host_op_rate 423606 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6399087906 # Simulator tick rate (ticks/s)
-host_mem_usage 408760 # Number of bytes of host memory used
-host_seconds 184.86 # Real time elapsed on the host
-sim_insts 61454647 # Number of instructions simulated
-sim_ops 78309315 # Number of ops (including micro ops) simulated
+host_inst_rate 462248 # Simulator instruction rate (inst/s)
+host_op_rate 589061 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8900686287 # Simulator tick rate (ticks/s)
+host_mem_usage 440324 # Number of bytes of host memory used
+host_seconds 132.96 # Real time elapsed on the host
+sim_insts 61460532 # Number of instructions simulated
+sim_ops 78321652 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654489 # Total number of read requests seen
-system.physmem.writeReqs 821150 # Total number of write requests seen
-system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425887296 # Total number of bytes read from memory
-system.physmem.bytesWritten 52553600 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis
+system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654550 # Total number of read requests seen
+system.physmem.writeReqs 821204 # Total number of write requests seen
+system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425891200 # Total number of bytes read from memory
+system.physmem.bytesWritten 52557056 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182953705000 # Total gap between requests
+system.physmem.totGap 1183433014000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159600 # Categorize read packet sizes
+system.physmem.readPktSize::6 159661 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 756836 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 64314 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests
-system.physmem.totBusLat 33271885000 # Total cycles spent in databus access
-system.physmem.totBankLat 9050992500 # Total cycles spent in bank access
-system.physmem.avgQLat 22093.24 # Average queueing delay per request
-system.physmem.avgBankLat 1360.16 # Average bank access latency per request
+system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests
+system.physmem.totBusLat 33272265000 # Total cycles spent in databus access
+system.physmem.totBankLat 9048957500 # Total cycles spent in bank access
+system.physmem.avgQLat 22096.54 # Average queueing delay per request
+system.physmem.avgBankLat 1359.83 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28453.39 # Average memory access latency
-system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 28456.37 # Average memory access latency
+system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 12.52 # Average write queue length over time
-system.physmem.readRowHits 6612346 # Number of row buffer hits during reads
-system.physmem.writeRowHits 800481 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 11.75 # Average write queue length over time
+system.physmem.readRowHits 6612404 # Number of row buffer hits during reads
+system.physmem.writeRowHits 800418 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes
-system.physmem.avgGap 158241.15 # Average gap between requests
+system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes
+system.physmem.avgGap 158302.83 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 69480 # number of replacements
-system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use
-system.l2c.total_refs 1677464 # Total number of references to valid blocks.
-system.l2c.sampled_refs 134656 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.457403 # Average number of references to valid blocks.
+system.l2c.replacements 69541 # number of replacements
+system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use
+system.l2c.total_refs 1672596 # Total number of references to valid blocks.
+system.l2c.sampled_refs 134740 # Sample count of references to valid blocks.
+system.l2c.avg_refs 12.413507 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy
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+system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor
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+system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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-system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.031453 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.809346 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 3740 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 1661 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 419713 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 206323 # number of ReadReq hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.itb.inst_misses 2205 # ITB inst misses
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
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+system.cpu0.dcache.overall_misses::total 369194 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 3141338000 # number of ReadReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total 88637000 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency::total 44352500 # number of StoreCondReq miss cycles
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+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6832095 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6832095 # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::total 157207 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12328301 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12328301 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total 12328301 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033295 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.033295 # miss rate for ReadReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059350 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047740 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047740 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.029947 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029947 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.029947 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13809.657367 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13809.657367 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29362.387101 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29362.387101 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9495.125870 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5909.726849 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5909.726849 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19779.778382 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19779.778382 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks
-system.cpu0.dcache.writebacks::total 306714 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks
+system.cpu0.dcache.writebacks::total 306255 # number of writebacks
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system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8309714 # DTB read hits
-system.cpu1.dtb.read_misses 3643 # DTB read misses
-system.cpu1.dtb.write_hits 5826503 # DTB write hits
-system.cpu1.dtb.write_misses 1435 # DTB write misses
+system.cpu1.dtb.read_hits 8312224 # DTB read hits
+system.cpu1.dtb.read_misses 3649 # DTB read misses
+system.cpu1.dtb.write_hits 5828610 # DTB write hits
+system.cpu1.dtb.write_misses 1432 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8313357 # DTB read accesses
-system.cpu1.dtb.write_accesses 5827938 # DTB write accesses
+system.cpu1.dtb.read_accesses 8315873 # DTB read accesses
+system.cpu1.dtb.write_accesses 5830042 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14136217 # DTB hits
-system.cpu1.dtb.misses 5078 # DTB misses
-system.cpu1.dtb.accesses 14141295 # DTB accesses
-system.cpu1.itb.inst_hits 33189716 # ITB inst hits
+system.cpu1.dtb.hits 14140834 # DTB hits
+system.cpu1.dtb.misses 5081 # DTB misses
+system.cpu1.dtb.accesses 14145915 # DTB accesses
+system.cpu1.itb.inst_hits 33192056 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses
-system.cpu1.itb.hits 33189716 # DTB hits
+system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses
+system.cpu1.itb.hits 33192056 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33191887 # DTB accesses
-system.cpu1.numCycles 2364475282 # number of cpu cycles simulated
+system.cpu1.itb.accesses 33194227 # DTB accesses
+system.cpu1.numCycles 2365415230 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32579235 # Number of instructions committed
-system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses
+system.cpu1.committedInsts 32581554 # Number of instructions committed
+system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 962009 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37310899 # number of integer instructions
+system.cpu1.num_func_calls 962092 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 37318858 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
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-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles
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+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:07:24
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:12
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 15802500 because target called exit()
+Exiting @ tick 16032500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16039500 # Number of ticks simulated
-final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 16032500 # Number of ticks simulated
+final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1336 # Simulator instruction rate (inst/s)
-host_op_rate 1336 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3362323 # Simulator tick rate (ticks/s)
-host_mem_usage 225744 # Number of bytes of host memory used
-host_seconds 4.77 # Real time elapsed on the host
+host_inst_rate 34765 # Simulator instruction rate (inst/s)
+host_op_rate 34761 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87452252 # Simulator tick rate (ticks/s)
+host_mem_usage 269696 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 486 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 15803000 # Total gap between requests
+system.physmem.totGap 15819000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2921750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests
+system.physmem.totQLat 2907500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests
system.physmem.totBusLat 2430000 # Total cycles spent in databus access
system.physmem.totBankLat 8305000 # Total cycles spent in bank access
-system.physmem.avgQLat 6011.83 # Average queueing delay per request
+system.physmem.avgQLat 5982.51 # Average queueing delay per request
system.physmem.avgBankLat 17088.48 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28100.31 # Average memory access latency
-system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28070.99 # Average memory access latency
+system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.15 # Data bus utilization in percentage
+system.physmem.busUtil 15.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.85 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 396 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 32516.46 # Average gap between requests
+system.physmem.avgGap 32549.38 # Average gap between requests
system.cpu.branchPred.lookups 2896 # Number of BP lookups
system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 32080 # number of cpu cycles simulated
+system.cpu.numCycles 32066 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken
system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2753 # Number of cycles decode is running
+system.cpu.decode.RunCycles 2752 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2631 # Number of cycles rename is running
+system.cpu.rename.RunCycles 2630 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer
system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10806 # Type of FU issued
-system.cpu.iq.rate 0.336845 # Inst issue rate
+system.cpu.iq.rate 0.336992 # Inst issue rate
system.cpu.iq.fu_busy_cnt 118 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 86 # number of nop insts executed
system.cpu.iew.exec_refs 3233 # number of memory reference insts executed
system.cpu.iew.exec_branches 1613 # Number of branches executed
system.cpu.iew.exec_stores 1101 # Number of stores executed
-system.cpu.iew.exec_rate 0.316521 # Inst execution rate
-system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9710 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5134 # num instructions producing a value
-system.cpu.iew.wb_consumers 6919 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.316628 # Inst execution rate
+system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9709 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5133 # num instructions producing a value
+system.cpu.iew.wb_consumers 6918 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 25928 # The number of ROB reads
+system.cpu.rob.rob_reads 25930 # The number of ROB reads
system.cpu.rob.rob_writes 27481 # The number of ROB writes
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12888 # number of integer regfile reads
-system.cpu.int_regfile_writes 7343 # number of integer regfile writes
+system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12887 # number of integer regfile reads
+system.cpu.int_regfile_writes 7342 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use
system.cpu.icache.total_refs 1869 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:48:19
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:13
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 9059000 because target called exit()
+Exiting @ tick 9350000 because target called exit()
sim_ticks 9350000 # Number of ticks simulated
final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55287 # Simulator instruction rate (inst/s)
-host_op_rate 55271 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 216439769 # Simulator tick rate (ticks/s)
-host_mem_usage 224436 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 14656 # Simulator instruction rate (inst/s)
+host_op_rate 14654 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57391857 # Simulator tick rate (ticks/s)
+host_mem_usage 269408 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1328750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests
+system.physmem.totQLat 1327750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests
system.physmem.totBusLat 1360000 # Total cycles spent in databus access
system.physmem.totBankLat 5183750 # Total cycles spent in bank access
-system.physmem.avgQLat 4885.11 # Average queueing delay per request
+system.physmem.avgQLat 4881.43 # Average queueing delay per request
system.physmem.avgBankLat 19057.90 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28943.01 # Average memory access latency
+system.physmem.avgMemAccLat 28939.34 # Average memory access latency
system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s
system.cpu.numCycles 18701 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle
+system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking
system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1056 # Number of cycles rename is running
system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.rate 0.217368 # Inst issue rate
system.cpu.iq.fu_busy_cnt 46 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iew.exec_rate 0.205978 # Inst execution rate
system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3664 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1730 # num instructions producing a value
-system.cpu.iew.wb_consumers 2229 # num instructions consuming a value
+system.cpu.iew.wb_producers 1729 # num instructions producing a value
+system.cpu.iew.wb_consumers 2228 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back
+system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 71 # Number of function calls committed.
system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 11838 # The number of ROB reads
+system.cpu.rob.rob_reads 11840 # The number of ROB reads
system.cpu.rob.rob_writes 11181 # The number of ROB writes
system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses
system.cpu.icache.overall_misses::total 249 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12422499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 12422499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 12422499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 12422499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12422499 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49889.554217 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49889.554217 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49889.554217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49889.554217 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49873.489960 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9626999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 9626999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9626999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 9626999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9626999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 9626999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9624999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 9624999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9624999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 9624999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9624999 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 9624999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51481.278075 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51481.278075 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51470.582888 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51470.582888 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9439000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9437000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 13026500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 13024500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 9439000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 9437000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 14434500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 9439000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total 14432500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 9437000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 14434500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 14432500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50475.935829 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50465.240642 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52526.209677 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52518.145161 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 53068.014706 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 53060.661765 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 53068.014706 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 53060.661765 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7116144 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9954927 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7116144 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11068939 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7116144 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 11068939 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38054.245989 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40140.834677 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:43:45
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 26 2013 15:15:53
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13354000 because target called exit()
+Exiting @ tick 13706000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13709000 # Number of ticks simulated
-final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13706000 # Number of ticks simulated
+final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31817 # Simulator instruction rate (inst/s)
-host_op_rate 39697 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 94976589 # Simulator tick rate (ticks/s)
-host_mem_usage 239960 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 599 # Simulator instruction rate (inst/s)
+host_op_rate 748 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1788642 # Simulator tick rate (ticks/s)
+host_mem_usage 284080 # Number of bytes of host memory used
+host_seconds 7.66 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13651500 # Total gap between requests
+system.physmem.totGap 13648500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29826.14 # Average memory access latency
-system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 14.37 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34648.48 # Average gap between requests
-system.cpu.branchPred.lookups 2501 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.physmem.avgGap 34640.86 # Average gap between requests
+system.cpu.branchPred.lookups 2491 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBHits 700 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 27419 # number of cpu cycles simulated
+system.cpu.numCycles 27413 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2445 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2438 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
+system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.RunCycles 2238 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8986 # Type of FU issued
-system.cpu.iq.rate 0.327729 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8967 # Type of FU issued
+system.cpu.iq.rate 0.327108 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 230 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1444 # Number of branches executed
+system.cpu.iew.exec_refs 3301 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1438 # Number of branches executed
system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.312302 # Inst execution rate
-system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8106 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3904 # num instructions producing a value
-system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.311713 # Inst execution rate
+system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8089 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3894 # num instructions producing a value
+system.cpu.iew.wb_consumers 7825 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23072 # The number of ROB reads
-system.cpu.rob.rob_writes 23605 # The number of ROB writes
-system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23047 # The number of ROB reads
+system.cpu.rob.rob_writes 23560 # The number of ROB writes
+system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
-system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39366 # number of integer regfile reads
-system.cpu.int_regfile_writes 8019 # number of integer regfile writes
+system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39296 # number of integer regfile reads
+system.cpu.int_regfile_writes 8001 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
+system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use
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system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits
-system.cpu.dcache.overall_hits::total 2370 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits
+system.cpu.dcache.overall_hits::total 2369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:43:34
+gem5 compiled Mar 26 2013 15:15:23
+gem5 started Mar 26 2013 15:15:53
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13354000 because target called exit()
+Exiting @ tick 13706000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13709000 # Number of ticks simulated
-final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13706000 # Number of ticks simulated
+final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 36221 # Simulator instruction rate (inst/s)
-host_op_rate 45190 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 108117571 # Simulator tick rate (ticks/s)
-host_mem_usage 238932 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 7143 # Simulator instruction rate (inst/s)
+host_op_rate 8913 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21323596 # Simulator tick rate (ticks/s)
+host_mem_usage 284080 # Number of bytes of host memory used
+host_seconds 0.64 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13651500 # Total gap between requests
+system.physmem.totGap 13648500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29826.14 # Average memory access latency
-system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 14.37 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34648.48 # Average gap between requests
-system.cpu.branchPred.lookups 2501 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.physmem.avgGap 34640.86 # Average gap between requests
+system.cpu.branchPred.lookups 2491 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBHits 700 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 27419 # number of cpu cycles simulated
+system.cpu.numCycles 27413 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2445 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2438 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
+system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.RunCycles 2238 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8986 # Type of FU issued
-system.cpu.iq.rate 0.327729 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8967 # Type of FU issued
+system.cpu.iq.rate 0.327108 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 230 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1444 # Number of branches executed
+system.cpu.iew.exec_refs 3301 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1438 # Number of branches executed
system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.312302 # Inst execution rate
-system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8106 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3904 # num instructions producing a value
-system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.311713 # Inst execution rate
+system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8089 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3894 # num instructions producing a value
+system.cpu.iew.wb_consumers 7825 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits
-system.cpu.dcache.overall_hits::total 2370 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits
+system.cpu.dcache.overall_hits::total 2369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:16:55
+gem5 compiled Mar 26 2013 14:56:08
+gem5 started Mar 26 2013 14:56:29
gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 18578000 because target called exit()
+Exiting @ tick 19339000 because target called exit()
sim_ticks 19339000 # Number of ticks simulated
final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54855 # Simulator instruction rate (inst/s)
-host_op_rate 54842 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 182382541 # Simulator tick rate (ticks/s)
-host_mem_usage 224336 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 26477 # Simulator instruction rate (inst/s)
+host_op_rate 26474 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 88053451 # Simulator tick rate (ticks/s)
+host_mem_usage 270344 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use
-system.cpu.icache.total_refs 428 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 429 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits
-system.cpu.icache.overall_hits::total 428 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits
+system.cpu.icache.overall_hits::total 429 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 774 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 774 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.447028 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.447028 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency
system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:06
+gem5 compiled Mar 26 2013 14:56:08
+gem5 started Mar 26 2013 14:56:29
gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 16532500 because target called exit()
+Exiting @ tick 17026500 because target called exit()
sim_ticks 17026500 # Number of ticks simulated
final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44899 # Simulator instruction rate (inst/s)
-host_op_rate 44889 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 148205995 # Simulator tick rate (ticks/s)
-host_mem_usage 226388 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 19281 # Simulator instruction rate (inst/s)
+host_op_rate 19280 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63663526 # Simulator tick rate (ticks/s)
+host_mem_usage 270344 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2863000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests
+system.physmem.totQLat 2843000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests
system.physmem.totBusLat 2390000 # Total cycles spent in databus access
system.physmem.totBankLat 9363750 # Total cycles spent in bank access
-system.physmem.avgQLat 5989.54 # Average queueing delay per request
+system.physmem.avgQLat 5947.70 # Average queueing delay per request
system.physmem.avgBankLat 19589.44 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30578.97 # Average memory access latency
+system.physmem.avgMemAccLat 30537.13 # Average memory access latency
system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s
system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 35495.82 # Average gap between requests
-system.cpu.branchPred.lookups 2222 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2218 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups
system.cpu.branchPred.BTBHits 508 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing
+system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3094 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3093 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing
+system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing
+system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2958 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename
system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8325 # Type of FU issued
-system.cpu.iq.rate 0.244465 # Inst issue rate
+system.cpu.iq.FU_type_0::total 8318 # Type of FU issued
+system.cpu.iq.rate 0.244259 # Inst issue rate
system.cpu.iq.fu_busy_cnt 159 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1547 # number of nop insts executed
-system.cpu.iew.exec_refs 3203 # number of memory reference insts executed
+system.cpu.iew.exec_nop 1546 # number of nop insts executed
+system.cpu.iew.exec_refs 3202 # number of memory reference insts executed
system.cpu.iew.exec_branches 1355 # Number of branches executed
-system.cpu.iew.exec_stores 1078 # Number of stores executed
-system.cpu.iew.exec_rate 0.233042 # Inst execution rate
-system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7471 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2950 # num instructions producing a value
-system.cpu.iew.wb_consumers 4259 # num instructions consuming a value
+system.cpu.iew.exec_stores 1077 # Number of stores executed
+system.cpu.iew.exec_rate 0.232924 # Inst execution rate
+system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7467 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2949 # num instructions producing a value
+system.cpu.iew.wb_consumers 4258 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 87 # Number of function calls committed.
system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23973 # The number of ROB reads
-system.cpu.rob.rob_writes 22610 # The number of ROB writes
-system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23961 # The number of ROB reads
+system.cpu.rob.rob_writes 22589 # The number of ROB writes
+system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads
system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10756 # number of integer regfile reads
-system.cpu.int_regfile_writes 5239 # number of integer regfile writes
+system.cpu.int_regfile_reads 10750 # number of integer regfile reads
+system.cpu.int_regfile_writes 5236 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 150 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
-system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use
system.cpu.icache.total_refs 1566 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits
system.cpu.icache.overall_hits::total 1566 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses
-system.cpu.icache.overall_misses::total 447 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:33:02
-gem5 started Jan 23 2013 15:33:08
+gem5 compiled Mar 26 2013 14:59:37
+gem5 started Mar 26 2013 14:59:57
gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 14065500 because target called exit()
+Exiting @ tick 14724500 because target called exit()
sim_ticks 14724500 # Number of ticks simulated
final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 62176 # Simulator instruction rate (inst/s)
-host_op_rate 62167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 158021685 # Simulator tick rate (ticks/s)
-host_mem_usage 222660 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 11850 # Simulator instruction rate (inst/s)
+host_op_rate 11850 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30123505 # Simulator tick rate (ticks/s)
+host_mem_usage 266600 # Number of bytes of host memory used
+host_seconds 0.49 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.cpu.numCycles 29450 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken
system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle
+system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2083 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1969 # Number of cycles rename is running
system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.rate 0.302445 # Inst issue rate
system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3204 # number of memory reference insts executed
system.cpu.iew.exec_branches 1349 # Number of branches executed
system.cpu.iew.exec_stores 1531 # Number of stores executed
-system.cpu.iew.exec_rate 0.288353 # Inst execution rate
-system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8149 # cumulative count of insts written-back
+system.cpu.iew.exec_rate 0.288387 # Inst execution rate
+system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8150 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4198 # num instructions producing a value
system.cpu.iew.wb_consumers 6619 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21024 # The number of ROB reads
+system.cpu.rob.rob_reads 21027 # The number of ROB reads
system.cpu.rob.rob_writes 21246 # The number of ROB writes
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads
system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13466 # number of integer regfile reads
-system.cpu.int_regfile_writes 7036 # number of integer regfile writes
+system.cpu.int_regfile_reads 13468 # number of integer regfile reads
+system.cpu.int_regfile_writes 7037 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses
system.cpu.icache.overall_misses::total 441 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 198.145720 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 31.359554 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3170500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 20540500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 20541000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6078500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 23448500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6079000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23449000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6078500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 23448500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6079000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23449000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58712.962963 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51479.949875 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52576.233184 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52576.233184 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use
system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits
system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses
system.cpu.dcache.overall_misses::total 438 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:01:02
+gem5 compiled Mar 26 2013 15:04:14
+gem5 started Mar 26 2013 15:04:37
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 16286500 because target called exit()
+Hello World!Exiting @ tick 16783500 because target called exit()
sim_ticks 16783500 # Number of ticks simulated
final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48421 # Simulator instruction rate (inst/s)
-host_op_rate 48416 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 152524495 # Simulator tick rate (ticks/s)
-host_mem_usage 230316 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 18770 # Simulator instruction rate (inst/s)
+host_op_rate 18768 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59128079 # Simulator tick rate (ticks/s)
+host_mem_usage 276316 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2672750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests
+system.physmem.totQLat 2671750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests
system.physmem.totBusLat 2115000 # Total cycles spent in databus access
system.physmem.totBankLat 8208750 # Total cycles spent in bank access
-system.physmem.avgQLat 6318.56 # Average queueing delay per request
+system.physmem.avgQLat 6316.19 # Average queueing delay per request
system.physmem.avgBankLat 19406.03 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30724.59 # Average memory access latency
+system.physmem.avgMemAccLat 30722.22 # Average memory access latency
system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use
-system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use
+system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits
-system.cpu.icache.overall_hits::total 895 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits
+system.cpu.icache.overall_hits::total 896 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:21:58
+gem5 compiled Mar 26 2013 15:13:59
+gem5 started Mar 26 2013 15:14:41
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 15471000 because target called exit()
+Exiting @ tick 15474000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000015 # Number of seconds simulated
-sim_ticks 15471000 # Number of ticks simulated
-final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 15474000 # Number of ticks simulated
+final_tick 15474000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25126 # Simulator instruction rate (inst/s)
-host_op_rate 45518 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72243012 # Simulator tick rate (ticks/s)
-host_mem_usage 287412 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 16433 # Simulator instruction rate (inst/s)
+host_op_rate 29770 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47259450 # Simulator tick rate (ticks/s)
+host_mem_usage 286708 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1253198914 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 603851622 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1857050536 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1253198914 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1253198914 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1253198914 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 603851622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1857050536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 451 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 15455000 # Total gap between requests
+system.physmem.totGap 15458000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 19969.51 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29181.26 # Average memory access latency
-system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1857.05 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1857.05 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 14.51 # Data bus utilization in percentage
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34268.29 # Average gap between requests
-system.cpu.branchPred.lookups 2992 # Number of BP lookups
-system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted
+system.physmem.avgGap 34274.94 # Average gap between requests
+system.cpu.branchPred.lookups 2993 # Number of BP lookups
+system.cpu.branchPred.condPredicted 2993 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 2483 # Number of BTB lookups
system.cpu.branchPred.BTBHits 793 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 31.937173 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 30943 # number of cpu cycles simulated
+system.cpu.numCycles 30949 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles 8903 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14396 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2993 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles 3910 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2411 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 3703 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 286 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 18564 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.369856 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.872055 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 14753 79.47% 79.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 190 1.02% 80.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 168 0.90% 84.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 264 1.42% 85.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 161 0.87% 86.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2519 13.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total 18564 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.096707 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.465152 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9437 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3518 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle
+system.cpu.decode.RunCycles 3520 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 143 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1818 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 24283 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1818 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9780 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3304 # Number of cycles rename is running
+system.cpu.rename.RunCycles 3306 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 22784 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 24893 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 54727 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 54711 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 13830 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 34 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 2066 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 20310 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 17272 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 9822 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 18564 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.930403 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.788380 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13176 70.98% 70.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1404 7.56% 78.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1053 5.67% 84.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 694 3.74% 87.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 727 3.92% 91.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 623 3.36% 95.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 18564 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13885 80.39% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1904 11.02% 91.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17266 # Type of FU issued
-system.cpu.iq.rate 0.557994 # Inst issue rate
+system.cpu.iq.FU_type_0::total 17272 # Type of FU issued
+system.cpu.iq.rate 0.558079 # Inst issue rate
system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.010016 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 53478 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 30175 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 15918 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17438 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1818 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 20346 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions
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system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
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system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52285.478548 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52626.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52606.430155 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52606.430155 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3057807 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3057807 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6087848 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18179829 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6087848 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18179829 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40234.302632 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40234.302632 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 83.491215 # Cycle average of tags in use
system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 83.491215 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020384 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020384 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:39:20
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:13
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 19857000 because target called exit()
+Exiting @ tick 24422500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000024 # Number of seconds simulated
-sim_ticks 24473000 # Number of ticks simulated
-final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 24422500 # Number of ticks simulated
+final_tick 24422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87264 # Simulator instruction rate (inst/s)
-host_op_rate 87257 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 167537445 # Simulator tick rate (ticks/s)
-host_mem_usage 226344 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 26625 # Simulator instruction rate (inst/s)
+host_op_rate 26623 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51014333 # Simulator tick rate (ticks/s)
+host_mem_usage 270288 # Number of bytes of host memory used
+host_seconds 0.48 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory
system.physmem.num_reads::total 970 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1629972362 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 911945951 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2541918313 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1629972362 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1629972362 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1629972362 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 911945951 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2541918313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 970 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 24326500 # Total gap between requests
+system.physmem.totGap 24269500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 167 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 262 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 22645500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests
+system.physmem.totQLat 22107000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 52930750 # Sum of mem lat for all requests
system.physmem.totBusLat 4850000 # Total cycles spent in databus access
system.physmem.totBankLat 25973750 # Total cycles spent in bank access
-system.physmem.avgQLat 23345.88 # Average queueing delay per request
+system.physmem.avgQLat 22790.72 # Average queueing delay per request
system.physmem.avgBankLat 26777.06 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 55122.94 # Average memory access latency
-system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 54567.78 # Average memory access latency
+system.physmem.avgRdBW 2541.92 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2541.92 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 19.82 # Data bus utilization in percentage
-system.physmem.avgRdQLen 2.18 # Average read queue length over time
+system.physmem.busUtil 19.86 # Data bus utilization in percentage
+system.physmem.avgRdQLen 2.17 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 450 # Number of row buffer hits during reads
+system.physmem.readRowHits 449 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 46.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25078.87 # Average gap between requests
-system.cpu.branchPred.lookups 6101 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 1023 # Number of BTB hits
+system.physmem.avgGap 25020.10 # Average gap between requests
+system.cpu.branchPred.lookups 6091 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3456 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1235 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4406 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 1013 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 22.991375 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 798 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4461 # DTB read hits
-system.cpu.dtb.read_misses 100 # DTB read misses
+system.cpu.dtb.read_hits 4448 # DTB read hits
+system.cpu.dtb.read_misses 96 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4561 # DTB read accesses
-system.cpu.dtb.write_hits 2022 # DTB write hits
-system.cpu.dtb.write_misses 83 # DTB write misses
+system.cpu.dtb.read_accesses 4544 # DTB read accesses
+system.cpu.dtb.write_hits 2020 # DTB write hits
+system.cpu.dtb.write_misses 84 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2105 # DTB write accesses
-system.cpu.dtb.data_hits 6483 # DTB hits
-system.cpu.dtb.data_misses 183 # DTB misses
+system.cpu.dtb.write_accesses 2104 # DTB write accesses
+system.cpu.dtb.data_hits 6468 # DTB hits
+system.cpu.dtb.data_misses 180 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6666 # DTB accesses
-system.cpu.itb.fetch_hits 4836 # ITB hits
+system.cpu.dtb.data_accesses 6648 # DTB accesses
+system.cpu.itb.fetch_hits 4827 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 4885 # ITB accesses
+system.cpu.itb.fetch_accesses 4876 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 48947 # number of cpu cycles simulated
+system.cpu.numCycles 48846 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1375 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 33885 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6091 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1811 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5723 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1593 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 523 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 4827 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 28036 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.208625 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.641797 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 22313 79.59% 79.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 519 1.85% 81.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 362 1.29% 82.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 384 1.37% 84.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 439 1.57% 85.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 391 1.39% 87.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 437 1.56% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 371 1.32% 89.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2820 10.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total 28036 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.124698 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.693711 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38743 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 4956 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch
+system.cpu.decode.RunCycles 4948 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 475 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2422 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 482 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking
+system.cpu.decode.DecodedInsts 30410 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 547 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2422 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 39365 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6014 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4731 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 4720 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2126 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 28231 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 2058 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 21224 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 34730 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 34696 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 12084 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 5609 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2913 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1333 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.insertedLoads 2720 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1281 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 25056 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 20851 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11467 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 7098 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 28036 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.743722 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.323178 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 18861 67.27% 67.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3429 12.23% 79.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2549 9.09% 88.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1540 5.49% 94.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 935 3.33% 97.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 455 1.62% 99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 194 0.69% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 28036 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 2.99% 2.99% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.99% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.99% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.99% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 103 61.68% 64.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 59 35.33% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 6975 65.76% 65.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2523 23.79% 89.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1103 10.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10607 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10606 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 6760 65.98% 66.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2371 23.14% 89.18% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1109 10.82% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10268 # Type of FU issued
+system.cpu.iq.FU_type_1::total 10245 # Type of FU issued
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu 13735 65.87% 65.89% # Type of FU issued
+system.cpu.iq.FU_type::IntMult 2 0.01% 65.90% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv 0 0.00% 65.90% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
+system.cpu.iq.FU_type::MemRead 4894 23.47% 89.39% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite 2212 10.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 20875 # Type of FU issued
-system.cpu.iq.rate 0.426482 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type::total 20851 # Type of FU issued
+system.cpu.iq.rate 0.426872 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 81 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 167 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.004125 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.003885 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.008009 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 69931 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 36600 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 18226 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 20993 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1730 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 468 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1537 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedStores 416 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 292 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2853 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 25308 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 582 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5633 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2614 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 221 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions
+system.cpu.iew.branchMispredicts 1126 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 19605 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecLoadInsts::1 2207 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4555 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1246 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
system.cpu.iew.exec_nop::1 81 # number of nop insts executed
system.cpu.iew.exec_nop::total 179 # number of nop insts executed
system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1527 # Number of branches executed
+system.cpu.iew.exec_refs::1 3257 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6671 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1525 # Number of branches executed
system.cpu.iew.exec_branches::1 1521 # Number of branches executed
-system.cpu.iew.exec_branches::total 3048 # Number of branches executed
+system.cpu.iew.exec_branches::total 3046 # Number of branches executed
system.cpu.iew.exec_stores::0 1066 # Number of stores executed
-system.cpu.iew.exec_stores::1 1051 # Number of stores executed
-system.cpu.iew.exec_stores::total 2117 # Number of stores executed
-system.cpu.iew.exec_rate 0.401046 # Inst execution rate
-system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 4725 # num instructions producing a value
-system.cpu.iew.wb_producers::1 4632 # num instructions producing a value
-system.cpu.iew.wb_producers::total 9357 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value
+system.cpu.iew.exec_stores::1 1050 # Number of stores executed
+system.cpu.iew.exec_stores::total 2116 # Number of stores executed
+system.cpu.iew.exec_rate 0.401363 # Inst execution rate
+system.cpu.iew.wb_sent::0 9356 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9171 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 18527 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9033 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 18246 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 4732 # num instructions producing a value
+system.cpu.iew.wb_producers::1 4628 # num instructions producing a value
+system.cpu.iew.wb_producers::total 9360 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6204 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6054 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 12258 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.188613 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.184928 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.373541 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.762734 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.764453 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.763583 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 12541 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 961 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 27993 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.456507 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.239608 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 22231 79.42% 79.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 3185 11.38% 90.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1025 3.66% 94.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 479 1.71% 96.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 332 1.19% 97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 227 0.81% 98.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 194 0.69% 98.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 80 0.29% 99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 240 0.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 27993 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
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system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352307 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::total 65494771 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total 65494771 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
system.cpu.dcache.replacements::total 0 # number of replacements
-system.cpu.dcache.tagsinuse 202.984846 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4338 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 203.203118 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4334 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.465517 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.454023 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 203.203118 # Average occupied blocks per requestor
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+system.cpu.dcache.occ_percent::total 0.049610 # Average percentage of cache occupancy
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system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
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-system.cpu.dcache.overall_hits::total 4338 # number of overall hits
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system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses
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system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.192171 # miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 78707.430341 # average ReadReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76468.445199 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4608 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.086957 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013500 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 30297498 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055571 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.064865 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.064865 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89175.742574 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89175.742574 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84136.972603 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84136.972603 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:08:16
+gem5 compiled Mar 26 2013 15:04:14
+gem5 started Mar 26 2013 15:04:37
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 23180500 because target called exit()
+Exiting @ tick 23775500 because target called exit()
sim_ticks 23775500 # Number of ticks simulated
final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 69027 # Simulator instruction rate (inst/s)
-host_op_rate 69023 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 113671122 # Simulator tick rate (ticks/s)
-host_mem_usage 232284 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 12604 # Simulator instruction rate (inst/s)
+host_op_rate 12604 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20757401 # Simulator tick rate (ticks/s)
+host_mem_usage 277264 # Number of bytes of host memory used
+host_seconds 1.15 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.cpu.numCycles 47552 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 12221 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 8387 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles 12951 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9300 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8402 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 13601 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 8395 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8002 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:01:12
+gem5 compiled Mar 26 2013 15:04:14
+gem5 started Mar 26 2013 15:04:37
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
Init done
[Iteration 1, Thread 1] Got lock
[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
Iteration 1 completed
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
Iteration 2 completed
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
Iteration 3 completed
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 5, Thread 1] Got lock
[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
Iteration 5 completed
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 6, Thread 3] Got lock
[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
Iteration 6 completed
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 7, Thread 3] Got lock
[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
Iteration 8 completed
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
Iteration 9 completed
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
Iteration 10 completed
PASSED :-)
-Exiting @ tick 104832500 because target called exit()
+Exiting @ tick 105945500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000106 # Number of seconds simulated
-sim_ticks 105801500 # Number of ticks simulated
-final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 105945500 # Number of ticks simulated
+final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 173787 # Simulator instruction rate (inst/s)
-host_op_rate 173787 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17750545 # Simulator tick rate (ticks/s)
-host_mem_usage 247480 # Number of bytes of host memory used
-host_seconds 5.96 # Real time elapsed on the host
-sim_insts 1035849 # Number of instructions simulated
-sim_ops 1035849 # Number of ops (including micro ops) simulated
+host_inst_rate 48441 # Simulator instruction rate (inst/s)
+host_op_rate 48441 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4953275 # Simulator tick rate (ticks/s)
+host_mem_usage 291288 # Number of bytes of host memory used
+host_seconds 21.39 # Real time elapsed on the host
+sim_insts 1036095 # Number of instructions simulated
+sim_ops 1036095 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 660 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 661 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 42240 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 105773500 # Total gap between requests
+system.physmem.totGap 105917500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4076500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests
+system.physmem.totQLat 4080500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests
system.physmem.totBusLat 3305000 # Total cycles spent in databus access
system.physmem.totBankLat 13310000 # Total cycles spent in bank access
-system.physmem.avgQLat 6167.17 # Average queueing delay per request
+system.physmem.avgQLat 6173.22 # Average queueing delay per request
system.physmem.avgBankLat 20136.16 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31303.33 # Average memory access latency
-system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 31309.38 # Average memory access latency
+system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.12 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.20 # Average read queue length over time
+system.physmem.busUtil 3.11 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.19 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 465 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 160020.42 # Average gap between requests
-system.cpu0.branchPred.lookups 82232 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted
+system.physmem.avgGap 160238.28 # Average gap between requests
+system.cpu0.branchPred.lookups 82343 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits
+system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 211604 # number of cpu cycles simulated
+system.cpu0.numCycles 211892 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running
+system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename
+system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle
+system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued
-system.cpu0.iq.rate 1.891623 # Inst issue rate
+system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued
+system.cpu0.iq.rate 1.891860 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking
+system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 75651 # number of nop insts executed
-system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 79264 # Number of branches executed
-system.cpu0.iew.exec_stores 77169 # Number of stores executed
-system.cpu0.iew.exec_rate 1.886439 # Inst execution rate
-system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 236156 # num instructions producing a value
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+system.cpu0.iew.exec_nop 75778 # number of nop insts executed
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+system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back
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system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit
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system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 467088 # Number of instructions committed
-system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed
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+system.cpu0.commit.committedInsts 467838 # Number of instructions committed
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system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 228259 # Number of memory references committed
-system.cpu0.commit.loads 151835 # Number of loads committed
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system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 78311 # Number of branches committed
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system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 314822 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 315322 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 669667 # The number of ROB reads
-system.cpu0.rob.rob_writes 961765 # The number of ROB writes
+system.cpu0.rob.rob_reads 670698 # The number of ROB reads
+system.cpu0.rob.rob_writes 963274 # The number of ROB writes
system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 391961 # Number of Instructions Simulated
-system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated
-system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 714059 # number of integer regfile reads
-system.cpu0.int_regfile_writes 321926 # number of integer regfile writes
+system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 392586 # Number of Instructions Simulated
+system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated
+system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 715161 # number of integer regfile reads
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system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.replacements 298 # number of replacements
-system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use
-system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use
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system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks.
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+system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.overall_hits::total 5162 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total 744 # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles
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-system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor
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+system.cpu0.icache.overall_hits::total 5155 # number of overall hits
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+system.cpu0.icache.overall_misses::total 746 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits
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+system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits
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+system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses
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-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency
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+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
-system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits
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-system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits
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system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 153944 # number of overall hits
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+system.cpu0.dcache.overall_hits::total 154182 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1018 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles
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-system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles
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+system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses
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+system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses
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+system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses
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system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 58098 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits
+system.cpu1.branchPred.lookups 56473 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 174790 # number of cpu cycles simulated
+system.cpu1.numCycles 175078 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued
-system.cpu1.iq.rate 1.564203 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued
+system.cpu1.iq.rate 1.510424 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute
+system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 45600 # number of nop insts executed
-system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 54914 # Number of branches executed
-system.cpu1.iew.exec_stores 45718 # Number of stores executed
-system.cpu1.iew.exec_rate 1.557349 # Inst execution rate
-system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 156621 # num instructions producing a value
-system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value
+system.cpu1.iew.exec_nop 44011 # number of nop insts executed
+system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 53318 # Number of branches executed
+system.cpu1.iew.exec_stores 43665 # Number of stores executed
+system.cpu1.iew.exec_rate 1.503964 # Inst execution rate
+system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 150856 # num instructions producing a value
+system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 310743 # Number of instructions committed
-system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 300197 # Number of instructions committed
+system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 137689 # Number of memory references committed
-system.cpu1.commit.loads 92644 # Number of loads committed
-system.cpu1.commit.membars 3055 # Number of memory barriers committed
-system.cpu1.commit.branches 54067 # Number of branches committed
+system.cpu1.commit.refs 131930 # Number of memory references committed
+system.cpu1.commit.loads 88970 # Number of loads committed
+system.cpu1.commit.membars 3544 # Number of memory barriers committed
+system.cpu1.commit.branches 52469 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 213879 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 206526 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 483263 # The number of ROB reads
-system.cpu1.rob.rob_writes 648465 # The number of ROB writes
-system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.rob.rob_reads 472949 # The number of ROB reads
+system.cpu1.rob.rob_writes 627337 # The number of ROB writes
+system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 262828 # Number of Instructions Simulated
-system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated
-system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 478110 # number of integer regfile reads
-system.cpu1.int_regfile_writes 222397 # number of integer regfile writes
+system.cpu1.committedInsts 253388 # Number of Instructions Simulated
+system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated
+system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 460976 # number of integer regfile reads
+system.cpu1.int_regfile_writes 214498 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.replacements 317 # number of replacements
-system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use
-system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use
+system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits
-system.cpu1.icache.overall_hits::total 15102 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses
-system.cpu1.icache.overall_misses::total 482 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency
+system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits
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+system.cpu1.icache.overall_hits::total 16176 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::total 484 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
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system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 8302000 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 45099 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits
+system.cpu2.branchPred.lookups 48435 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 174459 # number of cpu cycles simulated
+system.cpu2.numCycles 174747 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued
-system.cpu2.iq.rate 1.143380 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued
+system.cpu2.iq.rate 1.246190 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 32635 # number of nop insts executed
-system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 41831 # Number of branches executed
-system.cpu2.iew.exec_stores 28461 # Number of stores executed
-system.cpu2.iew.exec_rate 1.136726 # Inst execution rate
-system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 108943 # num instructions producing a value
-system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value
+system.cpu2.iew.exec_nop 35937 # number of nop insts executed
+system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 45106 # Number of branches executed
+system.cpu2.iew.exec_stores 32695 # Number of stores executed
+system.cpu2.iew.exec_rate 1.239535 # Inst execution rate
+system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 120625 # num instructions producing a value
+system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 223981 # Number of instructions committed
-system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 245558 # Number of instructions committed
+system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 90122 # Number of memory references committed
-system.cpu2.commit.loads 62324 # Number of loads committed
-system.cpu2.commit.membars 7244 # Number of memory barriers committed
-system.cpu2.commit.branches 41003 # Number of branches committed
+system.cpu2.commit.refs 101851 # Number of memory references committed
+system.cpu2.commit.loads 69824 # Number of loads committed
+system.cpu2.commit.membars 6301 # Number of memory barriers committed
+system.cpu2.commit.branches 44289 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 153248 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 168258 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 398976 # The number of ROB reads
-system.cpu2.rob.rob_writes 475157 # The number of ROB writes
-system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.rob.rob_reads 421045 # The number of ROB reads
+system.cpu2.rob.rob_writes 518771 # The number of ROB writes
+system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 184944 # Number of Instructions Simulated
-system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated
-system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 335090 # number of integer regfile reads
-system.cpu2.int_regfile_writes 157371 # number of integer regfile writes
+system.cpu2.committedInsts 204183 # Number of Instructions Simulated
+system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated
+system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 370277 # number of integer regfile reads
+system.cpu2.int_regfile_writes 173276 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.replacements 319 # number of replacements
-system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use
-system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks.
+system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use
+system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks.
+system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits
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system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 47073 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits
+system.cpu3.branchPred.lookups 45379 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 174149 # number of cpu cycles simulated
+system.cpu3.numCycles 174437 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename
+system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle
+system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued
-system.cpu3.iq.rate 1.206438 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued
+system.cpu3.iq.rate 1.148908 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking
+system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 34512 # number of nop insts executed
-system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 43690 # Number of branches executed
-system.cpu3.iew.exec_stores 30979 # Number of stores executed
-system.cpu3.iew.exec_rate 1.199743 # Inst execution rate
-system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 115832 # num instructions producing a value
-system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value
+system.cpu3.iew.exec_nop 32807 # number of nop insts executed
+system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 41971 # Number of branches executed
+system.cpu3.iew.exec_stores 28736 # Number of stores executed
+system.cpu3.iew.exec_rate 1.142235 # Inst execution rate
+system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 109565 # num instructions producing a value
+system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle
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system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated
-system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads
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+system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction
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system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
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system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
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system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency
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system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:51:52
+gem5 compiled Mar 26 2013 15:04:14
+gem5 started Mar 26 2013 15:04:37
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 1, Thread 2] Got lock
[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
Iteration 1 completed
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 3, Thread 3] Got lock
[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
Iteration 3 completed
[Iteration 4, Thread 2] Got lock
[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
Iteration 5 completed
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 7, Thread 3] Got lock
[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
Iteration 7 completed
[Iteration 8, Thread 2] Got lock
[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 1] Got lock
[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
Iteration 8 completed
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
Iteration 9 completed
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
Iteration 10 completed
PASSED :-)
-Exiting @ tick 261623500 because target called exit()
+Exiting @ tick 262970500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000262 # Number of seconds simulated
-sim_ticks 261623500 # Number of ticks simulated
-final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000263 # Number of seconds simulated
+sim_ticks 262970500 # Number of ticks simulated
+final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 226128 # Simulator instruction rate (inst/s)
-host_op_rate 226126 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 89603226 # Simulator tick rate (ticks/s)
-host_mem_usage 289396 # Number of bytes of host memory used
-host_seconds 2.92 # Real time elapsed on the host
-sim_insts 660239 # Number of instructions simulated
-sim_ops 660239 # Number of ops (including micro ops) simulated
+host_inst_rate 110323 # Simulator instruction rate (inst/s)
+host_op_rate 110323 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43749084 # Simulator tick rate (ticks/s)
+host_mem_usage 287188 # Number of bytes of host memory used
+host_seconds 6.01 # Real time elapsed on the host
+sim_insts 663135 # Number of instructions simulated
+sim_ops 663135 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 523247 # number of cpu cycles simulated
+system.cpu0.numCycles 525941 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 158010 # Number of instructions committed
-system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses
+system.cpu0.committedInsts 158580 # Number of instructions committed
+system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 108832 # number of integer instructions
+system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 109212 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 73739 # number of memory refs
-system.cpu0.num_load_insts 48819 # Number of load instructions
-system.cpu0.num_store_insts 24920 # Number of store instructions
+system.cpu0.num_mem_refs 74024 # number of memory refs
+system.cpu0.num_load_insts 49009 # Number of load instructions
+system.cpu0.num_store_insts 25015 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 523247 # Number of busy cycles
+system.cpu0.num_busy_cycles 525941 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
-system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use
-system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use
+system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits
-system.cpu0.icache.overall_hits::total 157606 # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits
+system.cpu0.icache.overall_hits::total 158176 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
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system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles
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system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
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-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 523247 # number of cpu cycles simulated
+system.cpu1.numCycles 525940 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 173283 # Number of instructions committed
-system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 108736 # number of integer instructions
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system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read
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+system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency
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+system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
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-system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles
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-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency
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-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 160665 # Number of instructions committed
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system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
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-system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls
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system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
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-system.cpu2.num_load_insts 42488 # Number of load instructions
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-system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles
-system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles
-system.cpu2.icache.replacements 281 # number of replacements
-system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use
-system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks.
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-system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks.
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system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency
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-system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency
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-system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency
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system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
num_work_ids=16
readfile=
symbolfile=
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=16
master=system.physmem.port
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=16
master=system.l2c.cpu_side
-system.cpu4: completed 10000 read, 5213 write accesses @76807500
-system.cpu7: completed 10000 read, 5302 write accesses @79251000
-system.cpu3: completed 10000 read, 5351 write accesses @81062000
-system.cpu5: completed 10000 read, 5541 write accesses @82066500
-system.cpu1: completed 10000 read, 5479 write accesses @82140500
-system.cpu2: completed 10000 read, 5270 write accesses @82209500
-system.cpu6: completed 10000 read, 5352 write accesses @82224000
-system.cpu0: completed 10000 read, 5437 write accesses @83502000
-system.cpu4: completed 20000 read, 10638 write accesses @152852500
-system.cpu7: completed 20000 read, 10671 write accesses @153245500
-system.cpu5: completed 20000 read, 10802 write accesses @155921500
-system.cpu1: completed 20000 read, 10780 write accesses @157898500
-system.cpu3: completed 20000 read, 10762 write accesses @158207000
-system.cpu2: completed 20000 read, 10562 write accesses @158441500
-system.cpu6: completed 20000 read, 10817 write accesses @160812000
-system.cpu0: completed 20000 read, 10942 write accesses @162138000
-system.cpu4: completed 30000 read, 15885 write accesses @226882500
-system.cpu7: completed 30000 read, 16162 write accesses @230488000
-system.cpu1: completed 30000 read, 15996 write accesses @231220000
-system.cpu5: completed 30000 read, 16227 write accesses @232272500
-system.cpu3: completed 30000 read, 16181 write accesses @234012000
-system.cpu6: completed 30000 read, 16285 write accesses @236458500
-system.cpu2: completed 30000 read, 16117 write accesses @236552000
-system.cpu0: completed 30000 read, 16426 write accesses @240306500
-system.cpu4: completed 40000 read, 21151 write accesses @301825500
-system.cpu7: completed 40000 read, 21649 write accesses @305825500
-system.cpu1: completed 40000 read, 21293 write accesses @308437500
-system.cpu3: completed 40000 read, 21436 write accesses @308497500
-system.cpu5: completed 40000 read, 21614 write accesses @310554000
-system.cpu2: completed 40000 read, 21323 write accesses @312243500
-system.cpu6: completed 40000 read, 21541 write accesses @312536000
-system.cpu0: completed 40000 read, 21919 write accesses @320331000
-system.cpu4: completed 50000 read, 26446 write accesses @376676500
-system.cpu7: completed 50000 read, 26971 write accesses @382643500
-system.cpu1: completed 50000 read, 26742 write accesses @382692500
-system.cpu3: completed 50000 read, 26868 write accesses @383729000
-system.cpu5: completed 50000 read, 26982 write accesses @388892000
-system.cpu2: completed 50000 read, 26690 write accesses @389746500
-system.cpu6: completed 50000 read, 26890 write accesses @390639500
-system.cpu0: completed 50000 read, 27239 write accesses @394395001
-system.cpu4: completed 60000 read, 31859 write accesses @454814000
-system.cpu3: completed 60000 read, 32157 write accesses @455574000
-system.cpu1: completed 60000 read, 32039 write accesses @458833000
-system.cpu7: completed 60000 read, 32494 write accesses @460248000
-system.cpu2: completed 60000 read, 32094 write accesses @465749500
-system.cpu5: completed 60000 read, 32378 write accesses @466634000
-system.cpu6: completed 60000 read, 32333 write accesses @468161500
-system.cpu0: completed 60000 read, 32569 write accesses @469644500
-system.cpu3: completed 70000 read, 37524 write accesses @531095000
-system.cpu4: completed 70000 read, 37387 write accesses @531724000
-system.cpu1: completed 70000 read, 37455 write accesses @534864500
-system.cpu2: completed 70000 read, 37386 write accesses @539742500
-system.cpu7: completed 70000 read, 38025 write accesses @540171500
-system.cpu5: completed 70000 read, 37779 write accesses @540661000
-system.cpu0: completed 70000 read, 37912 write accesses @543002000
-system.cpu6: completed 70000 read, 37876 write accesses @544926000
-system.cpu4: completed 80000 read, 42765 write accesses @607648000
-system.cpu3: completed 80000 read, 42947 write accesses @608627500
-system.cpu1: completed 80000 read, 42804 write accesses @612176500
-system.cpu5: completed 80000 read, 43215 write accesses @614679500
-system.cpu2: completed 80000 read, 42837 write accesses @616130500
-system.cpu7: completed 80000 read, 43372 write accesses @618251000
-system.cpu0: completed 80000 read, 43388 write accesses @620992000
-system.cpu6: completed 80000 read, 43420 write accesses @622851000
-system.cpu4: completed 90000 read, 48066 write accesses @681361000
-system.cpu3: completed 90000 read, 48251 write accesses @683201500
-system.cpu1: completed 90000 read, 48377 write accesses @690035500
-system.cpu5: completed 90000 read, 48546 write accesses @692142000
-system.cpu2: completed 90000 read, 48240 write accesses @693946000
-system.cpu7: completed 90000 read, 48816 write accesses @696757000
-system.cpu0: completed 90000 read, 48758 write accesses @697163500
-system.cpu6: completed 90000 read, 48649 write accesses @698059000
-system.cpu4: completed 100000 read, 53418 write accesses @758619000
+system.cpu6: completed 10000 read, 5435 write accesses @79021500
+system.cpu0: completed 10000 read, 5363 write accesses @79194500
+system.cpu7: completed 10000 read, 5392 write accesses @79770500
+system.cpu2: completed 10000 read, 5375 write accesses @80689500
+system.cpu1: completed 10000 read, 5373 write accesses @81623500
+system.cpu4: completed 10000 read, 5458 write accesses @81916000
+system.cpu5: completed 10000 read, 5507 write accesses @81975000
+system.cpu3: completed 10000 read, 5421 write accesses @82381000
+system.cpu2: completed 20000 read, 10678 write accesses @153864500
+system.cpu0: completed 20000 read, 10854 write accesses @154789000
+system.cpu7: completed 20000 read, 10817 write accesses @154953500
+system.cpu1: completed 20000 read, 10781 write accesses @155855500
+system.cpu3: completed 20000 read, 10799 write accesses @157033000
+system.cpu4: completed 20000 read, 10854 write accesses @157158000
+system.cpu6: completed 20000 read, 10878 write accesses @157795000
+system.cpu5: completed 20000 read, 10963 write accesses @159866500
+system.cpu0: completed 30000 read, 16180 write accesses @228385000
+system.cpu2: completed 30000 read, 15995 write accesses @229109500
+system.cpu7: completed 30000 read, 16232 write accesses @231170000
+system.cpu1: completed 30000 read, 16165 write accesses @231658500
+system.cpu4: completed 30000 read, 16252 write accesses @232783000
+system.cpu6: completed 30000 read, 16228 write accesses @233712000
+system.cpu3: completed 30000 read, 16226 write accesses @236523000
+system.cpu5: completed 30000 read, 16456 write accesses @239602000
+system.cpu0: completed 40000 read, 21598 write accesses @305262000
+system.cpu2: completed 40000 read, 21332 write accesses @306571000
+system.cpu1: completed 40000 read, 21599 write accesses @307778500
+system.cpu4: completed 40000 read, 21599 write accesses @307971000
+system.cpu7: completed 40000 read, 21551 write accesses @308441000
+system.cpu6: completed 40000 read, 21597 write accesses @310397000
+system.cpu3: completed 40000 read, 21704 write accesses @312891000
+system.cpu5: completed 40000 read, 21914 write accesses @315565000
+system.cpu4: completed 50000 read, 26891 write accesses @381925000
+system.cpu0: completed 50000 read, 26990 write accesses @382095500
+system.cpu2: completed 50000 read, 26686 write accesses @382917500
+system.cpu1: completed 50000 read, 26983 write accesses @384289000
+system.cpu6: completed 50000 read, 27066 write accesses @384539000
+system.cpu7: completed 50000 read, 26943 write accesses @385136500
+system.cpu3: completed 50000 read, 27037 write accesses @389922000
+system.cpu5: completed 50000 read, 27423 write accesses @393691500
+system.cpu6: completed 60000 read, 32353 write accesses @457634500
+system.cpu4: completed 60000 read, 32228 write accesses @457992000
+system.cpu1: completed 60000 read, 32457 write accesses @460714000
+system.cpu2: completed 60000 read, 32178 write accesses @461196500
+system.cpu0: completed 60000 read, 32542 write accesses @461690000
+system.cpu7: completed 60000 read, 32302 write accesses @462388500
+system.cpu3: completed 60000 read, 32488 write accesses @466103000
+system.cpu5: completed 60000 read, 32744 write accesses @469778000
+system.cpu6: completed 70000 read, 37747 write accesses @533745000
+system.cpu2: completed 70000 read, 37532 write accesses @535320500
+system.cpu4: completed 70000 read, 37773 write accesses @535591500
+system.cpu7: completed 70000 read, 37639 write accesses @538124500
+system.cpu0: completed 70000 read, 37909 write accesses @538334500
+system.cpu1: completed 70000 read, 37921 write accesses @541231500
+system.cpu3: completed 70000 read, 37871 write accesses @542226500
+system.cpu5: completed 70000 read, 38229 write accesses @548322500
+system.cpu4: completed 80000 read, 42983 write accesses @610769500
+system.cpu6: completed 80000 read, 43020 write accesses @610776000
+system.cpu2: completed 80000 read, 42982 write accesses @611661000
+system.cpu0: completed 80000 read, 43374 write accesses @615085500
+system.cpu1: completed 80000 read, 43250 write accesses @615627500
+system.cpu7: completed 80000 read, 43033 write accesses @615746000
+system.cpu3: completed 80000 read, 43154 write accesses @619760000
+system.cpu5: completed 80000 read, 43738 write accesses @625688001
+system.cpu6: completed 90000 read, 48339 write accesses @685422000
+system.cpu2: completed 90000 read, 48272 write accesses @687608500
+system.cpu4: completed 90000 read, 48507 write accesses @688615500
+system.cpu7: completed 90000 read, 48310 write accesses @688789000
+system.cpu0: completed 90000 read, 48650 write accesses @689991000
+system.cpu1: completed 90000 read, 48621 write accesses @693117500
+system.cpu3: completed 90000 read, 48493 write accesses @697608000
+system.cpu5: completed 90000 read, 49008 write accesses @701381500
+system.cpu6: completed 100000 read, 53851 write accesses @761435500
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:00
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:12
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 758619000 because maximum number of loads reached
+Exiting @ tick 761435500 because maximum number of loads reached
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000758 # Number of seconds simulated
-sim_ticks 758227000 # Number of ticks simulated
-final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000761 # Number of seconds simulated
+sim_ticks 761435500 # Number of ticks simulated
+final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 200763174 # Simulator tick rate (ticks/s)
-host_mem_usage 353776 # Number of bytes of host memory used
-host_seconds 3.78 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory
-system.physmem.bytes_read::total 744485 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory
-system.physmem.bytes_written::total 538519 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 15709 # number of replacements
-system.l2c.tagsinuse 802.621152 # Cycle average of tags in use
-system.l2c.total_refs 152986 # Total number of references to valid blocks.
-system.l2c.sampled_refs 16508 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.267386 # Average number of references to valid blocks.
+host_tick_rate 112752764 # Simulator tick rate (ticks/s)
+host_mem_usage 399024 # Number of bytes of host memory used
+host_seconds 6.75 # Real time elapsed on the host
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+system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 695052962 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0 128328663 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 123113514 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 129364864 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu5 126939183 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::cpu6 11003 # number of ReadReq hits
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-system.l2c.ReadReq_hits::total 87631 # number of ReadReq hits
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-system.l2c.UpgradeReq_hits::cpu6 375 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu5 1995 # number of ReadExReq hits
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-system.l2c.ReadReq_misses::cpu5 911 # number of ReadReq misses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406697168 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412407125 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 410618544 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 412439590 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408986543 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406399119 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 3276320370 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229120490 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 221422480 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227576980 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223709488 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225472990 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232298486 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233243987 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227452978 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1820297879 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0 637960644 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1 631354607 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2 634274148 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3 636116613 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4 636091534 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5 644738076 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6 642230530 # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total 5096618249 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070942 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068114 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2 0.071947 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069464 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4 0.072790 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072121 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073016 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.068696 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.070893 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842915 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.843490 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.837585 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841486 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.845144 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844255 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.826718 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.848394 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.841191 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.670365 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679739 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680154 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.688666 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.678134 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.672005 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.668466 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.677572 # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.282801 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total 0.282801 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48576.767107 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48188.661250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48098.382181 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47668.238861 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48375.928489 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47145.583829 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 47976.462243 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47751.479804 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 47974.747647 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.037594 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40960.677235 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41009.295431 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40978.911195 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40998.869048 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40963.232323 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41031.923077 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41060.743564 # average UpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41753.018575 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41609.860005 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41682.097753 # average ReadExReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 98877 # number of read accesses completed
-system.cpu0.num_writes 53303 # number of write accesses completed
+system.cpu0.num_reads 99397 # number of read accesses completed
+system.cpu0.num_writes 53728 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.replacements 22594 # number of replacements
-system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks.
-system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks.
-system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks.
+system.cpu0.l1c.replacements 22406 # number of replacements
+system.cpu0.l1c.tagsinuse 396.107523 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 13328 # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs 22796 # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs 0.584664 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor
-system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9567 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses
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-system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses
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-system.cpu0.l1c.overall_misses::total 59203 # number of overall misses
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-system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles
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-system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles
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-system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses)
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-system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked
+system.cpu0.l1c.occ_blocks::cpu0 396.107523 # Average occupied blocks per requestor
+system.cpu0.l1c.occ_percent::cpu0 0.773648 # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::total 0.773648 # Average percentage of cache occupancy
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+system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits
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+system.cpu0.l1c.overall_hits::cpu0 9865 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9865 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36190 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36190 # number of ReadReq misses
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+system.cpu0.l1c.overall_misses::total 59195 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 1343389412 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 1343389412 # number of ReadReq miss cycles
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+system.cpu0.l1c.overall_miss_latency::total 2432907657 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 44941 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 24119 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses)
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+system.cpu0.l1c.overall_accesses::cpu0 69060 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 69060 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953812 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.953812 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.857153 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.857153 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.857153 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.857153 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37120.459022 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 37120.459022 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47360.062812 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 47360.062812 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 41099.884399 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 41099.884399 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 41099.884399 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 41099.884399 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 1437100 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 67352 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks
-system.cpu0.l1c.writebacks::total 9829 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses
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-system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses
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-system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses
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-system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses
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-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks
+system.cpu0.l1c.writebacks::total 9722 # number of writebacks
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+system.cpu0.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses
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+system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1271011412 # number of ReadReq MSHR miss cycles
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+system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2314525657 # number of overall MSHR miss cycles
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+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 712928581 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35120.514286 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35120.514286 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45360.323625 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45360.323625 # average WriteReq mshr miss latency
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+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 98330 # number of read accesses completed
-system.cpu1.num_writes 53283 # number of write accesses completed
+system.cpu1.num_reads 98684 # number of read accesses completed
+system.cpu1.num_writes 53281 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.replacements 22413 # number of replacements
-system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks.
-system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks.
-system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks.
+system.cpu1.l1c.replacements 21834 # number of replacements
+system.cpu1.l1c.tagsinuse 394.001606 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 13244 # Total number of references to valid blocks.
+system.cpu1.l1c.sampled_refs 22217 # Sample count of references to valid blocks.
+system.cpu1.l1c.avg_refs 0.596120 # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor
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-system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy
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-system.cpu1.l1c.overall_hits::total 9845 # number of overall hits
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-system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses
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-system.cpu1.l1c.overall_misses::total 58823 # number of overall misses
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-system.cpu1.l1c.ReadReq_miss_latency::total 1339256827 # number of ReadReq miss cycles
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-system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles
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-system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles
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-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency
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+system.cpu1.l1c.occ_percent::total 0.769534 # Average percentage of cache occupancy
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+system.cpu1.l1c.ReadReq_hits::total 8661 # number of ReadReq hits
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+system.cpu1.l1c.WriteReq_miss_rate::total 0.955070 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.857870 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.857870 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.857870 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.857870 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37247.868742 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 37247.868742 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47593.510968 # average WriteReq miss latency
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+system.cpu1.l1c.demand_avg_miss_latency::cpu1 41297.433119 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 41297.433119 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 41297.433119 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 41297.433119 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 1437849 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 66915 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.487693 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks
-system.cpu1.l1c.writebacks::total 9847 # number of writebacks
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-system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses
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-system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses
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-system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses
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-system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses
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-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks 9612 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1261597219 # number of ReadReq MSHR miss cycles
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+system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2311207435 # number of overall MSHR miss cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1137526156 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805165 # mshr miss rate for ReadReq accesses
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+system.cpu1.l1c.demand_mshr_miss_rate::total 0.857870 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.857870 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35248.022435 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35248.022435 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45593.597845 # average WriteReq mshr miss latency
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+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 98918 # number of read accesses completed
-system.cpu2.num_writes 53026 # number of write accesses completed
+system.cpu2.num_reads 99895 # number of read accesses completed
+system.cpu2.num_writes 53724 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.replacements 22091 # number of replacements
-system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks.
-system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks.
-system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks.
+system.cpu2.l1c.replacements 22670 # number of replacements
+system.cpu2.l1c.tagsinuse 395.972858 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 13513 # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs 23058 # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs 0.586044 # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor
-system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits
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-system.cpu2.l1c.demand_hits::total 9719 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9719 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9719 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 22782 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 22782 # number of WriteReq misses
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-system.cpu2.l1c.demand_misses::total 58574 # number of demand (read+write) misses
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-system.cpu2.l1c.overall_misses::total 58574 # number of overall misses
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-system.cpu2.l1c.ReadReq_miss_latency::total 1334540137 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 1086319531 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles
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-system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles
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-system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses
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-system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses
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-system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency
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-system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked
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+system.cpu2.l1c.occ_percent::total 0.773384 # Average percentage of cache occupancy
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+system.cpu2.l1c.ReadReq_hits::total 8816 # number of ReadReq hits
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+system.cpu2.l1c.overall_hits::total 9936 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36217 # number of ReadReq misses
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+system.cpu2.l1c.overall_misses::total 59358 # number of overall misses
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+system.cpu2.l1c.ReadReq_miss_latency::total 1347141340 # number of ReadReq miss cycles
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+system.cpu2.l1c.ReadReq_accesses::total 45033 # number of ReadReq accesses(hits+misses)
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+system.cpu2.l1c.overall_accesses::total 69294 # number of overall (read+write) accesses
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+system.cpu2.l1c.ReadReq_miss_rate::total 0.804232 # miss rate for ReadReq accesses
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+system.cpu2.l1c.WriteReq_miss_rate::total 0.953835 # miss rate for WriteReq accesses
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+system.cpu2.l1c.demand_miss_rate::total 0.856611 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.856611 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.856611 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37196.381257 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 37196.381257 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47088.166415 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 47088.166415 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 41052.740978 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 41052.740978 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 41052.740978 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 41052.740978 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 1437012 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 67454 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.303585 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks
-system.cpu2.l1c.writebacks::total 9590 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses
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-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles
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-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks 9964 # number of writebacks
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system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 53514 # number of write accesses completed
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system.cpu3.num_copies 0 # number of copy accesses completed
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-system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks.
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system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles
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+system.cpu3.l1c.demand_mshr_miss_rate::total 0.859054 # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total 0.859054 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35714.911557 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35714.911557 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45193.991020 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45193.991020 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99302 # number of read accesses completed
-system.cpu4.num_writes 53818 # number of write accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.replacements 22353 # number of replacements
-system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use
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-system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22398 # number of replacements
+system.cpu4.l1c.tagsinuse 394.185618 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 13312 # Total number of references to valid blocks.
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+system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu4.l1c.ReadReq_miss_latency::total 1336431585 # number of ReadReq miss cycles
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-system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles
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-system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency
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-system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency
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+system.cpu4.l1c.occ_percent::total 0.769894 # Average percentage of cache occupancy
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+system.cpu4.l1c.ReadReq_hits::total 8742 # number of ReadReq hits
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+system.cpu4.l1c.ReadReq_avg_miss_latency::total 37208.396467 # average ReadReq miss latency
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+system.cpu4.l1c.WriteReq_avg_miss_latency::total 47007.809416 # average WriteReq miss latency
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9680 # number of writebacks
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-system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses
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-system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses
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-system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses
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-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles
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-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency
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-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency
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+system.cpu4.l1c.writebacks::total 9672 # number of writebacks
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+system.cpu4.l1c.ReadReq_mshr_misses::total 36283 # number of ReadReq MSHR misses
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+system.cpu4.l1c.WriteReq_mshr_misses::total 23024 # number of WriteReq MSHR misses
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+system.cpu4.l1c.demand_mshr_misses::total 59307 # number of demand (read+write) MSHR misses
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+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 713854071 # number of ReadReq MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for overall accesses
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+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35208.506711 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35208.506711 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45007.983148 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45007.983148 # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98038 # number of read accesses completed
-system.cpu5.num_writes 52677 # number of write accesses completed
+system.cpu5.num_reads 98297 # number of read accesses completed
+system.cpu5.num_writes 53409 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.replacements 21614 # number of replacements
-system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks.
-system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks.
-system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks.
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system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency
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+system.cpu5.l1c.ReadReq_avg_miss_latency::total 37438.647860 # average ReadReq miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses
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-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles
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-system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles
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-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles
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-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles
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-system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses
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-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency
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-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu6.num_reads 100000 # number of read accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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+system.cpu6.l1c.tagsinuse 396.232181 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 13413 # Total number of references to valid blocks.
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+system.cpu6.l1c.avg_refs 0.585260 # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy
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-system.cpu6.l1c.overall_hits::total 9733 # number of overall hits
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-system.cpu6.l1c.ReadReq_miss_latency::total 1334639245 # number of ReadReq miss cycles
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-system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles
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-system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency
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+system.cpu6.l1c.ReadReq_avg_miss_latency::total 37113.734753 # average ReadReq miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.writebacks::total 9651 # number of writebacks
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-system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses
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-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles
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-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles
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-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles
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-system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses
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-system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency
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-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency
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-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 100000 # number of read accesses completed
-system.cpu7.num_writes 53815 # number of write accesses completed
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system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.l1c.replacements 22563 # number of replacements
-system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks.
-system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks.
-system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks.
+system.cpu7.l1c.replacements 22280 # number of replacements
+system.cpu7.l1c.tagsinuse 395.094392 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 13351 # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs 22696 # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy
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-system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency
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-system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked
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+system.cpu7.l1c.occ_percent::total 0.771669 # Average percentage of cache occupancy
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+system.cpu7.l1c.ReadReq_hits::total 8656 # number of ReadReq hits
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+system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks
-system.cpu7.l1c.writebacks::total 9844 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses
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-system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses
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-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles
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-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses
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-system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses
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-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
projects / gem5.git / commitdiff