Merge pull request #624 from trabucayre/emio_zynq

soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode

diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index 2fdda7184e2b636a9cea91711fc752dd4581a19f..21608831be539e04308bc7d77ee83299c016a83a 100644 (file)
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -82,11 +82,14 @@ class PlatformInfo:
         return "{}({})".format(self.__class__.__name__, repr(self.info))
 
 
-def _lookup(description, name, number):
+def _lookup(description, name, number, loose=True):
     for resource in description:
         if resource[0] == name and (number is None or resource[1] == number):
             return resource
-    raise ConstraintError("Resource not found: {}:{}".format(name, number))
+    if loose:
+        return None
+    else:
+        raise ConstraintError("Resource not found: {}:{}".format(name, number))
 
 
 def _resource_type(resource):
@@ -178,8 +181,10 @@ class ConstraintManager:
     def add_extension(self, io):
         self.available.extend(io)
 
-    def request(self, name, number=None):
-        resource = _lookup(self.available, name, number)
+    def request(self, name, number=None, loose=False):
+        resource = _lookup(self.available, name, number, loose)
+        if resource is None:
+            return None
         rt, ri = _resource_type(resource)
         if number is None:
             resource_name = name

diff --git a/litex/soc/cores/cpu/blackparrot/bp_litex/bp2wb_convertor.v b/litex/soc/cores/cpu/blackparrot/bp_litex/bp2wb_convertor.v
index d045f68c5a66b23bd8be4ca55836d785830ed143..c361e7c469384c1c6ad70a21648e343a1b21e258 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/bp_litex/bp2wb_convertor.v
+++ b/litex/soc/cores/cpu/blackparrot/bp_litex/bp2wb_convertor.v
@@ -97,14 +97,14 @@ module bp2wb_convertor
         set_stb <= 0;
         v_li <=0;
       end
-      else if (v_li)
-      begin
-        if (mem_resp_yumi_i)
+//      else if (v_li)
+//      begin
+      else if (mem_resp_yumi_i)
         begin
           v_li <= 0;
           ack_ctr <= 0;
         end
-      end
+//      end
       else if (mem_cmd_v_i)
       begin
         //data_li <= 0;

diff --git a/litex/soc/cores/cpu/blackparrot/bp_litex/fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_litex/fpga/ExampleBlackParrotSystem.v
index e1663b4789cad7d43be63132ca4eed3a70cbcdb0..a818ad2ebaa78a8fb779f76027baa3f1f6445608 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/bp_litex/fpga/ExampleBlackParrotSystem.v
+++ b/litex/soc/cores/cpu/blackparrot/bp_litex/fpga/ExampleBlackParrotSystem.v
@@ -213,6 +213,7 @@ bp_cce_mmio_cfg_loader
     ,.inst_ram_els_p(num_cce_instr_ram_els_p)
     ,.skip_ram_init_p(skip_init_p)
     ,.clear_freeze_p(!load_nbf_p)
+    ,.cce_ucode_filename_p("/tmp/cce_ucode.mem")
     )
   cfg_loader
   (.clk_i(clk_i)
@@ -229,6 +230,7 @@ bp_cce_mmio_cfg_loader
    ,.io_resp_ready_o(cfg_resp_ready_lo)
 
    ,.done_o(cfg_done_lo)
+ 
   );
 
 // CFG and NBF are mutex, so we can just use fixed arbitration here

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 54a4fe6050f97ee5081b853c2dc15e528d44c70f..0ab7d4c01d40825600d2c4a5a1c37d7016445f8b 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -46,7 +46,7 @@ GCC_FLAGS = {
 
 class BlackParrotRV64(CPU):
     name                 = "blackparrot"
-    human_name           = "BlackParrotRV64[ia]"
+    human_name           = "BlackParrotRV64[ima]"
     variants             = CPU_VARIANTS
     data_width           = 64
     endianness           = "little"

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index eb56d0e2805c6e697dea3153c0bde4305d9dc1df..cd45a0b4a029723cecf84787079d3eab87c62fb0 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1313,7 +1313,7 @@ class LiteXSoC(SoC):
         from liteeth.frontend.etherbone import LiteEthEtherbone
         # Core
         ethcore = LiteEthUDPIPCore(
-            phy         = self.ethphy,
+            phy         = phy,
             mac_address = mac_address,
             ip_address  = ip_address,
             clk_freq    = self.clk_freq)