[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transc...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Tue, 5 May 2020 17:02:11 +0000 (17:02 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Tue, 5 May 2020 17:02:13 +0000 (18:02 +0100)
4d/8cbb584b7a3e383fa3cc9e1382fb95f6b3724c [new file with mode: 0644]

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+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Tue, 05 May 2020 17:02:11 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: ALU (including IEEE754 16/32/64-bit FPU)
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: mtnolan2640@gmail.com
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-208-13-opKayy0Ev6@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-208-13@https.bugs.libre-soc.org/>
+References: <bug-208-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 208] implement CORDIC in a general way
+ sufficient to do transcendentals
+X-BeenThere: libre-riscv-dev@lists.libre-riscv.org
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