whoops truncated the mb and me fields

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 05969d31f858f62468e4bf0e051c50f07b36249f..8e5f9ecdd211f03e0b302d4cb4dd761eb90daee9 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -100,9 +100,9 @@ class Driver(Elaboratable):
         # clear left?
         with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCL)):
             with m.If(rec.is_32bit):
-                comb += mb.eq(m_fields.MB[0:-1])
+                comb += mb.eq(m_fields.MB)
             with m.Else():
-                comb += mb.eq(md_fields.mb[0:-1])
+                comb += mb.eq(md_fields.mb)
         with m.Else():
             with m.If(rec.is_32bit):
                 comb += mb.eq(b[0:6])
@@ -117,9 +117,9 @@ class Driver(Elaboratable):
         # clear right?
         with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCR)):
             with m.If(rec.is_32bit):
-                comb += me.eq(m_fields.ME[0:-1])
+                comb += me.eq(m_fields.ME)
             with m.Else():
-                comb += me.eq(md_fields.me[0:-1])
+                comb += me.eq(md_fields.me)
         with m.Else():
             with m.If(rec.is_32bit):
                 comb += me.eq(b[0:6])