Added link to pinmux

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index c91744b12f6133fb85a1625b483c050d38c5076d..cb5bb2c35d76b5f35b5565eb758acc147332d242 100644 (file)
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -2,6 +2,7 @@
 
 * NLnet page: [[nlnet_2021_crypto_router]]
 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+* Pinmux page: [[crypto_router_pinmux]]
 
 # Specifications
 

diff --git a/crypto_router_pinmux.mdwn b/crypto_router_pinmux.mdwn
index ba92da0340b1108d017aed67aa25dc3393c87605..48bcbbd39bbe66290b11081e17b57bc2ef94da4e 100644 (file)
--- a/crypto_router_pinmux.mdwn
+++ b/crypto_router_pinmux.mdwn
@@ -8,14 +8,16 @@
 * QFP 200 pin?
 
 # Functionality and Pincount:
-* 5x RGMII Ethernet - 5x12 = *60 pins*
-* 2x USB ULPI - 2x12 = *24 pins*
-* GPIO (plain and EINT) - *? pins*
-* SDRAM - 16-bit data, 9-bit addr, rd/wr - *approx 30 pins?*
-* I2C - *2 pins*
-* SPI - assuming 4-pin - *4 pins*
-* QSPI - *6 pins*
-* JTAG - Can't read nmigen well enough, assuming TCK, TDO, TMS, TDI - *4 pins*
-* Power Vdd and Vss - *? pins*
+* 5x RGMII Ethernet - 5x12 = **60 pins**
+* 2x USB ULPI - 2x12 = **24 pins**
+* GPIO (plain and EINT) - **? pins**
+* SDRAM - 16-bit data, 9-bit addr, rd/wr - **approx 30 pins?**
+* I2C - **2 pins**
+* SPI - assuming 4-pin - **4 pins**
+* QSPI - **6 pins**
+* JTAG - Can't read nmigen well enough, assuming TCK, TDO, TMS, TDI - **4 pins**
+* Power Vdd and Vss - **? pins**
 
-RGMII pinout count comes from [here] (https://web.pa.msu.edu/hep/atlas/l1calo/hub/hardware/components/micrel/rgmii_specification_hp_v1.3_dec_2000.pdf)
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+Total (**not including power and GPIO pins**): 130 pins
+
+RGMII pinout count comes from [here](https://web.pa.msu.edu/hep/atlas/l1calo/hub/hardware/components/micrel/rgmii_specification_hp_v1.3_dec_2000.pdf)
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