python3 setup.py install
cd ..
-3. Obtain MiSoC and install it:
- git clone https://github.com/m-labs/misoc --recursive
- cd misoc
- python3 setup.py install
- cd ..
-
-Note: in case you have issues with Migen/MiSoC, please retry
-with our forks at:
+Note: in case you have issues with Migen, please retry
+with our fork at:
https://github.com/enjoy-digital/misoc
- https://github.com/enjoy-digital/migen
until new features are merged.
-4. Obtain LiteScope and install it:
+3. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
cd litescope
python3 setup.py install
cd ..
-5. Obtain LiteSATA
+4. Obtain LiteSATA
git clone https://github.com/enjoy-digital/litesata
-6. Build and load BIST design (only for KC705 for now):
+5. Build and load BIST design (only for KC705 for now):
python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
-7. Test design (only for KC705 for now):
+6. Test design (only for KC705 for now):
go to ./test directory and run:
change com port in config.py to your com port
python3 bist.py
-8. Visualize Link Layer transactions (if BISTSoCDevel):
+7. Visualize Link Layer transactions (if BISTSoCDevel):
go to ./test directory and run:
python3 test_la.py [your_cond]
your_cond can be wr_cmd, id_cmd, rd_resp, ...
(open test_la.py to see all conditions or add yours)
-9. If you only want to build the core and use it with your
+8. If you only want to build the core and use it with your
regular design flow:
python3 make.py -t core build-core
- python3 setup.py install
- cd ..
+.. note::
+ In case you have issues with Migen, please retry with our fork at:
+ https://github.com/enjoy-digital/migen
+ until new features are merged.
+
3. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
- cd litescope
- python3 setup.py install
- cd ..
-4. Obtain MiSoC and install it:
- - git clone https://github.com/m-labs/misoc --recursive
- - cd misoc
- - python3 setup.py install
- - cd ..
-
-.. note::
- In case you have issues with Migen/MiSoC, please retry with our forks at:
- https://github.com/enjoy-digital/misoc
- https://github.com/enjoy-digital/migen
- until new features are merged.
-
-5. Obtain LiteSATA
+4. Obtain LiteSATA
- git clone https://github.com/enjoy-digital/litesata
-6. Build and load BIST design (only for KC705 for now):
+5. Build and load BIST design (only for KC705 for now):
- python3 make.py all
-7. Test design (only for KC705 for now):
+6. Test design (only for KC705 for now):
- go to ./test directory and run:
- python3 bist.py
+7. Visualize Link Layer transactions (if BISTSoCDevel):
+ - go to ./test directory and run:
+ - python3 test_la.py [your_cond]
+ - your_cond can be wr_cmd, id_cmd, rd_resp, ...
+ (open test_la.py to see all conditions or add yours)
+
8. If you only want to build the core and use it with your
regular design flow:
- - python3 make.py -t core build-core
\ No newline at end of file
+ - python3 make.py -t core build-core
from migen.util.misc import autotype
from migen.fhdl import verilog, edif
from migen.fhdl.structure import _Fragment
+from migen.bank.description import CSRStatus
from mibuild import tools
from mibuild.xilinx_common import *
-from misoclib.gensoc import cpuif
-
from litesata.common import *
+def get_csr_csv(regions):
+ r = ""
+ for name, origin, busword, obj in regions:
+ if not isinstance(obj, Memory):
+ for csr in obj:
+ nr = (csr.size + busword - 1)//busword
+ r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
+ origin += 4*nr
+ return r
+
def _import(default, name):
return importlib.import_module(default + "." + name)
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
- csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+ csr_csv = get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
tools.write_to_file("build/litesata.v", src)
if actions["build-bitstream"]:
- vns = platform.build(soc, build_name=build_name, run=False)
+ vns = platform.build(soc, build_name=build_name, run=True)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
+import subprocess
+
+from migen.fhdl.std import *
+from migen.bank.description import *
+
+def get_id():
+ output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
+ return int(output[:8], 16)
+
+class Identifier(Module, AutoCSR):
+ def __init__(self, sysid, frequency, revision=None):
+ self._r_sysid = CSRStatus(16)
+ self._r_revision = CSRStatus(32)
+ self._r_frequency = CSRStatus(32)
+
+ ###
+
+ if revision is None:
+ revision = get_id()
+
+ self.comb += [
+ self._r_sysid.status.eq(sysid),
+ self._r_revision.status.eq(revision),
+ self._r_frequency.status.eq(frequency),
+ ]
+
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.bank.description import *
-from misoclib import identifier
+from targets import *
from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
# CSR
- self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
+ self.submodules.identifier = Identifier(0, int(clk_freq))
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))
from migen.genlib.resetsync import AsyncResetSynchronizer
+from targets import *
+
from litesata.common import *
from litesata.phy import LiteSATAPHY
from litesata import LiteSATA
projects / litex.git / commitdiff