add separate buffermode=false single pipe test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Apr 2019 06:51:18 +0000 (07:51 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Apr 2019 06:51:18 +0000 (07:51 +0100)
src/add/test_buf_pipe.py

index 6f81998a81c78288c75c6738563dcf2006ed95ea..089b3bef243087bdcbd701ce33b4dfba739ec4af 100644 (file)
@@ -625,7 +625,7 @@ class ExampleStageDelayCls(StageCls):
 class ExampleBufDelayedPipe(BufferedPipeline):
 
     def __init__(self):
-        stage = ExampleStageDelayCls(valid_trigger=3)
+        stage = ExampleStageDelayCls(valid_trigger=2)
         BufferedPipeline.__init__(self, stage, stage_ctl=True,
                                     buffermode=True)
 
@@ -699,6 +699,10 @@ class ExampleBufModeAdd1Pipe(BufferedPipeline):
         BufferedPipeline.__init__(self, stage, buffermode=False)
 
 
+######################################################################
+# Test 16
+######################################################################
+
 class ExampleBufModeUnBufPipe(ControlBase):
 
     def elaborate(self, platform):
@@ -894,9 +898,9 @@ if __name__ == '__main__':
         f.write(vl)
 
     print ("test 15)")
-    dut = ExampleBufModeUnBufPipe()
+    dut = ExampleBufModeAdd1Pipe()
     data = data_chain1()
-    test = Test5(dut, test9_resultfn, data=data)
+    test = Test5(dut, test12_resultfn, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
     ports = [dut.p.i_valid, dut.n.i_ready,
              dut.n.o_valid, dut.p.o_ready] + \
@@ -905,6 +909,18 @@ if __name__ == '__main__':
     with open("test_bufunbuf15.il", "w") as f:
         f.write(vl)
 
+    print ("test 16)")
+    dut = ExampleBufModeUnBufPipe()
+    data = data_chain1()
+    test = Test5(dut, test12_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufunbuf16.il", "w") as f:
+        f.write(vl)
+
     print ("test 999 (expected to fail, which is a bug)")
     dut = ExampleBufUnBufPipe()
     data = data_chain1()