[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Tue, 9 Jun 2020 12:43:36 +0000 (12:43 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Tue, 9 Jun 2020 12:43:37 +0000 (13:43 +0100)
7d/18baf282ba1e4c8984e6cb4ab7a1bd65ff6fea [new file with mode: 0644]

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+Date: Tue, 09 Jun 2020 12:43:36 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-UI4jwkUnqS@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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