Merge pull request #263 from antonblanchard/reset-pid

Initialize PID register

diff --git a/dmi_dtm_xilinx.vhdl b/dmi_dtm_xilinx.vhdl
index ed92e959a27d066bb7a8fef6bc16f004f884cf0f..69d8996073c09795ee096e96fb7a8466dc512828 100644 (file)
--- a/dmi_dtm_xilinx.vhdl
+++ b/dmi_dtm_xilinx.vhdl
@@ -222,11 +222,12 @@ begin
     -- jtag_req latch. Could be split into 3 processes but it's probably
     -- not worthwhile.
     --
-    shifter: process(jtag_clk, jtag_reset)
+    shifter: process(jtag_clk, jtag_reset, sys_reset)
     begin
-       if jtag_reset = '1' then
+       if jtag_reset = '1' or sys_reset = '1' then
            shiftr <= (others => '0');
            jtag_req <= '0';
+           request <= (others => '0');
        elsif rising_edge(jtag_clk) then
 
            -- Handle jtag "commands" when sel is 1

diff --git a/execute1.vhdl b/execute1.vhdl
index 4f85f3d1f874de92cbdc4eb924eda27792c0e57a..f9b46c1a62e9db2c07835280bfb2cfba4e5c4bf3 100644 (file)
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -282,6 +282,8 @@ begin
        if rising_edge(clk) then
             if rst = '1' then
                 r <= reg_type_init;
+                ctrl.tb <= (others => '0');
+                ctrl.dec <= (others => '0');
                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
                 ctrl.irq_state <= WRITE_SRR0;
             else

diff --git a/spi_rxtx.vhdl b/spi_rxtx.vhdl
index acb5becb23323f0483fff26238fc6e948de7399e..b2de245413108ea9711586a9d4c5fd697ea68051 100644 (file)
--- a/spi_rxtx.vhdl
+++ b/spi_rxtx.vhdl
@@ -177,6 +177,7 @@ begin
                 sck_send <= '0';
                 sck_recv <= '0';
                 clk_div  <= 0;
+                counter := 0;
             elsif counter = clk_div then
                 counter := 0;
 
@@ -257,12 +258,16 @@ begin
     count_bit: process(clk)
     begin
         if rising_edge(clk) then
-            if start_cmd = '1' then
-                bit_count <= cmd_clks_i;
-            elsif state /= DATA then
-                bit_count <= (others => '1');
-            elsif sck_recv = '1' then
-                bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+            if rst = '1' then
+                bit_count <= (others => '0');
+            else
+                if start_cmd = '1' then
+                    bit_count <= cmd_clks_i;
+                elsif state /= DATA then
+                    bit_count <= (others => '1');
+                elsif sck_recv = '1' then
+                    bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+                end if;
             end if;
         end if;
     end process;