Convert yet another few tests to be able to use latest cxxsim

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index 1e5aa8fc51ebc4817dc1fcd92477762a29aa20cd..0a18c77bbe329cb0f28ece7bc826af9084acfbe0 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import os

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 3b4c562ec4b0dc57ea1f0ca941f076c2d53d63d8..2ed244f02a80d3c78470a66c4c966e14e37158a2 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -17,11 +17,10 @@ from soc.experiment.compalu_multi import MultiCompUnit
 from soc.decoder.power_enums import MicrOp
 from nmigen import Module
 from nmigen.cli import rtlil
-cxxsim = False
-if cxxsim:
-    from nmigen.sim.cxxsim import Simulator, Settle
-else:
-    from nmigen.back.pysim import Simulator, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 def wrap(process):

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index cb827907b1ae859102c58f9f6b2fcaa58816cce2..2e4d7a8928559b6a167f0cd3e9ffbb552dd7ab2e 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 82dac1481599405d3b467e892275e6f3ee4c1676..7e0df81ee8f33aec2562f99e0baa26e10e12c863 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index f94feceaacae2a0743f3b10a685d8f6f91727583..82e05e98561fde7fececbaad52724d0e6d0040af 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -14,19 +14,10 @@ from soc.decoder.isa.caller import ISACaller, special_sprs
 import unittest
 from nmigen.cli import rtlil
 from nmigen import Module, Signal
-from nmigen.back.pysim import Delay, Settle
-# NOTE: to use this (set to True), at present it is necessary to check
-# out the cxxsim nmigen branch
-cxxsim = False
-if cxxsim:
-    try:
-        from nmigen.sim.cxxsim import Simulator
-    except ImportError:
-        print("nope, sorry, have to use nmigen cxxsim branch for now")
-        cxxsim = False
-        from nmigen.back.pysim import Simulator
-else:
-    from nmigen.back.pysim import Simulator
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 def get_cu_inputs(dec2, sim):
@@ -314,12 +305,8 @@ class TestRunner(unittest.TestCase):
                     yield from self.execute(alu, instruction, pdecode2, test)
 
         sim.add_sync_process(process)
-        print(dir(sim))
-        if cxxsim:
+        with sim.write_vcd("shift_rot_simulator.vcd"):
             sim.run()
-        else:
-            with sim.write_vcd("shift_rot_simulator.vcd"):
-                sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):