increase delay on ECP5 ulx3s

diff --git a/src/crg.py b/src/crg.py
index 1141b26a2e0cadfc1e0b088839d66aa1a53064d2..af2ccb1ea04909dfe44ae5bdbf955a74030b7052 100644 (file)
--- a/src/crg.py
+++ b/src/crg.py
@@ -206,7 +206,7 @@ class ECPIX5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
 
         # Power-on delay (655us)
-        podcnt = Signal(18, reset=-1)
+        podcnt = Signal(23, reset=-1)
         pod_done = Signal()
         with m.If((podcnt != 0) & pll.locked):
             m.d.rawclk += podcnt.eq(podcnt-1)

diff --git a/src/ls2.py b/src/ls2.py
index e4a7188489e2337870331ecf4fa5ec811f65d926..e4589897f192cc57ecb8d124c964247c5b204d45 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -589,7 +589,7 @@ def build_platform(fpga, firmware):
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
-        clk_freq = 12.5e6
+        clk_freq = 25.0e6
 
     # select a firmware address
     fw_addr = None